JPH06223036A - Serial communication device - Google Patents

Abstract

PURPOSE:To securely input data and save output-side registers even if processing by a CPU is complex by sharing one register for serial output even for multiple serial inputs and output and providing registers for serial input corresponding to serial input/output parts one to one. CONSTITUTION:The serial communication device is provided with one register (P-S register) 12 for serial output which is used in common by the serial input/ output parts (unit) 16 and 17 and the registers (S-P register) 13 and 14 corresponding to the input/output parts one to one. Namely, one output buffer (P-S register) 12 is provided and the input buffers (S-P register) 13 and 14 as many as the opposite units are provided. Further, the CPU 11 writes data directly in the P-S register 12 through a data bus and data are written from the S-P registers 13 and 14. Further, a timing and switching control part 15 generates clock timing signals for the loading and shifting of the registers 12-14 and functions to switch shift clocks by the opposite-side units.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus in which a main CPU performs serial communication with a plurality of destinations, and more particularly to a serial communication apparatus suitable for saving registers.

[0002]

2. Description of the Related Art Conventionally, a serial interface requires less signal lines than a parallel interface, and is used as an interface when high speed is not required. Further, when the main CPU performs a serial interface with respect to a plurality of destinations, the output buffers (parallel / serial registers) and the input buffers (serial / parallel registers) are originally required for the number of destinations. Therefore, in order to save these registers, a method is used in which the parallel / serial register and the serial / parallel register are made common and the interface is switched by switching to the other party. A device related to this type is disclosed in, for example, Japanese Patent Laid-Open No. 62-
There is 286148.

[0003]

In the above prior art, when the parallel / serial register and the serial / parallel register are used in common, the data is output to one destination and then to another destination. In this case, it is necessary to wait for the shift time of the previous data output. The same applies to data input, and if there is data input from another party before the CPU stores the data held in the serial / parallel register, the data will be lost. In other words, if the processing of the CPU becomes complicated and the other party performs serial communication in the main processing or by the interruption, the CPU correctly takes in the data for each other party from one register by managing the time and order correctly. Becomes difficult. However, the data output can be realized relatively easily because it only guarantees the shift time. An object of the present invention is to provide a serial communication device that solves such a problem, can reliably input data even if the processing of the CPU is complicated, and can save registers on the output side. In addition, depending on the processing method of the CPU, if the input can be controlled collectively for several destinations, one serial / parallel register is used for each grouped serial input / output unit, so that the register on the input side can be controlled. Aim to save.

[0004]

To achieve the above object, the serial communication device of the present invention is commonly used by a plurality of serial input / output units (units 16 and 17 in FIG. 1).
Number of serial output registers (P → S register 12)
And a serial input register (S → P registers 13 and 14) corresponding to the input / output unit and one-to-one. Further, one serial output register (P → S register 12) commonly used by a plurality of serial input / output units (units 18 to 21 in FIG. 3) and a plurality of groups are divided according to the processing of the CPU. The serial input / output unit and the serial input registers (S → P registers 33 and 34) corresponding to each group are provided.

[0005]

In the present invention, one serial output register is shared by a plurality of serial input / output units. The serial input register is provided in a one-to-one correspondence with the serial input / output unit. Then, the timing & switching control unit generates clock timings for loading and shifting each register, and switches the shift clock for each destination. As a result, the number of registers on the output side can be reduced and data input can be reliably performed. Further, by grouping the serial input / output units according to the processing of the CPU and arranging one serial input register for each group, the number of registers can be reduced on the input side.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram of a serial communication apparatus according to the first embodiment of the present invention. In FIG. 1, 1
1 is multiple destinations (unit (1) to unit (N))
Is a CPU that performs synchronous serial input / output with respect to.
12 is a parallel / serial (P → S) register,
Reference numerals 13 and 14 denote serial / parallel (S → P) registers (1) and (N), and 15 denotes a timing & switching control section for switching a shift clock for each input destination unit, which constitute an interface section. Also, 1
Reference numerals 6 and 17 denote input / output target units (1) and (N). Also, SOD (Serial Output Data) is output data,
SID (Serial Input Data) 1, N is input data, SC
K (Serial Clock) 1 and N indicate shift clocks, respectively. In this embodiment, the number of output buffers (P → S registers) is one, and the number of input buffers (S → P registers) is equal to the number of destination units (N). In addition, the CPU 11
Data is directly written to the P → S register 12 via the data bus, and data is read from the S → P registers 13 and 14. Further, the timing & switching control unit 15
It has a function of generating clock timings for loading and shifting the registers 12 to 14 and switching the shift clock for each destination unit. The identification of the other party is performed by dividing the address in advance and decoding the address when the P → S register 12 is written.

The timing of each signal in serial communication will be described with reference to FIG. In this embodiment, CP
When U11 writes to the P → S register 12, after that, a shift clock is generated at the same timing.
On the other hand, SOD is a shift clock (SCK1, SCKN)
Is output in synchronization with, but this is output regardless of the other party. Also, the output destination of the shift clock changes depending on the address when writing to the P → S register 12, and for example, when writing to the address “1”, the unit (1) is selected and only SCK1 is output. Also, SID
1, SIDN are signals output from the units 16 and 17 in synchronization with the shift clock, and the S → P register 1
3 and 14 are stored. The contents of the S → P registers 13 and 14 will not be erased if they are read before the data is output to the same unit next time.

(Second Embodiment) FIG. 3 is a block diagram of a serial communication device according to a second embodiment of the present invention. Figure 3
In the figure, 31 is a switch corresponding to the group 1 including a plurality of units 18 and 19, and 32 is a switch corresponding to a group N including a plurality of units 20 and 21. 18 and 19 are group 1 respectively
(1a) and unit (1b), which belong to
0 and 21 are units (Na) and units (Nb) belonging to the group N. Further, 33 and 34 are S → P registers (G1) and (GN) corresponding to the units belonging to the group 1 and the group G, respectively. Also,
SID1a and SID1b are input data from group 1, SIDNa and SIDNb are input data from group N, SCK1a and SCK1b are shift clocks for group 1, SCKNa and SCKN.
b shows the shift clocks for the respective groups.
In this embodiment, one S → P register (S → P register 33 or S → P register 34) is divided into a plurality of grouped units (units 18 and 19 belonging to group 1 or units belonging to group N). Two
0, 21) are selected and connected by the switches 31, 32. This is because, depending on the processing of the CPU 11, it is not necessary to separate the S → P registers when controlling with the same interrupt, and several destination units can be grouped into one group and data can be fetched with one register. This is because.

[0009]

According to the present invention, since there is only one serial output register, the number of registers can be saved. Further, by providing the serial input registers only for the number of destinations, the held data is not erased by the input from other destinations, and the control is easy. Further, by grouping the serial input / output units according to the processing of the CPU and providing the corresponding number of serial input registers, it is possible to save registers as compared with the case of having only the number of destinations.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a serial communication device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a serial communication method according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a serial communication device according to a second embodiment of the present invention.

[Explanation of symbols]

 11 CPU 12 Parallel / Serial Register 13 Serial / Parallel Register (1) 14 Serial / Parallel Register (N) 15 Timing & Switching Control Unit 16 Unit (1) 17 Unit (N) 18 Unit (1a) 19 Unit (1b) 20 Unit (Na) 21 Unit (Nb) 31 Switch 32 Switch 33 Serial / Parallel Register (G1) 34 Serial / Parallel Register (GN)

Claims (2)

[Claims] 1. A CPU for a plurality of serial input / output units
In a device for performing serial communication is provided with one serial output register commonly used by the input / output unit and a serial input register corresponding to the input / output unit in a one-to-one correspondence. Serial communication device. 2. A CPU for a plurality of serial input / output units
In a device for performing serial communication, one serial output register commonly used in the input / output unit and a CPU
The serial communication device, wherein the input / output unit divided into a plurality of groups according to the processing of 1. and a serial input register corresponding to each group.