JPH06232201A - Semiconductor apparatus - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a semiconductor device of flip-chip structure having an electrode structure that is strong against thermal and mechanical stress and has a small power supply voltage drop. [Construction] Signal, power supply, and GND C on a ceramic substrate
A CB bump and a plurality of large-area and circular power source / GND connecting portions having the same structure as the CCB bump are provided around the CB bump, and the semiconductor chips are connected by soldering. CCB
The bump has a built-in copper core.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a flip chip structure for face down bonding a semiconductor chip to a substrate.

[0002]

2. Description of the Related Art A so-called CCB in which a solder bump for connecting an electrode is formed on a semiconductor chip, a connecting electrode corresponding to the solder bump is provided on a substrate, and the solder bump and the connecting electrode are collectively joined As an example of a semiconductor device having a flip chip structure by the method, for example, Japanese Patent Laid-Open No.
16159, JP-A-3-49246, and JP-A-3-18585, which will be described. FIG. 5 is an example of JP-A-3-16159. First, a through hole 5 is provided in the substrate 1, and a plurality of electrodes 3 are formed in a region around the through hole 5 to which the semiconductor chip 2 is connected.
A solder joint 4 is provided so as to surround them. A metallization 6 is formed on the side of the through hole 5 opposite to the chip connection surface so as to be sealed with solder. The semiconductor chip 2 has solder bumps 7 formed on pads, and a solder frame 8 is attached around the chip so as to correspond to the solder joint portion 4. (FIG. 5A) After positioning the semiconductor chip 2 on the electrode 3 of the substrate 1, the semiconductor chip 2 is passed through a heating furnace to simultaneously perform electrode connection and sealing (hereinafter referred to as a chip seal). (FIG. 5b) After that, the through hole 5 is closed by the solder 28 and hermetically sealed. (FIG. 5c) FIG.
It is an example of the gazette. The semiconductor chip 2 is mounted on the central portion of the silicon wiring board 9 via the CCB bumps 10. The element forming surface of the semiconductor chip 2 is hermetically sealed by a sealing portion 11 provided so as to surround the periphery of the solder bump 7. The silicon wiring substrate 9 is connected to the leads 14 of the film carrier 12 via the TAB bumps 13 to form a so-called TAB structure. FIG. 7, FIG. 8 and FIG. 9 are examples of Japanese Patent Laid-Open No. 3-18585. FIG. 7 is a state diagram in which the cooling plate 24 is in pressure contact with the semiconductor chip 2 in the liquid cooling state. The semiconductor chip 2 is connected to the substrate 1 by solder bumps 7 and solder frames 8. Similarly, the board 1 is connected to the circuit board 23.
The cooling plate 24 is pressed against the back surface of the semiconductor chip 2 by the spring 27 to perform heat transfer cooling. FIG. 8 is a view corresponding to the semiconductor chip 2 or the substrate 1 and seen from the connection surface thereof.
Speaking of a semiconductor chip, a solder frame 8 is provided so as to surround the solder bump 7 and its periphery. FIG. 9 shows an example in which the solder frame 8 of FIG. 8 is divided and provided on each side of the semiconductor chip, and in this case, the chip seal structure is not formed.
The use of the chip seal structure in these conventional techniques has the purpose of preventing contamination of the chip element formation surface in the use state of the product. Further, the purpose of the invention is to increase the connection area as much as possible to obtain a heat dissipation effect by heat conduction and to prevent the solder bumps 7 from being broken by dispersing the pressure applied to the semiconductor chip in the solder frame 8.

[0003]

In the conventional semiconductor device having the flip chip structure described above, solder bumps are formed on the electrodes of the semiconductor chip and the electrodes of the substrate are thermally connected. At this time, flux is used so that the two can be connected perfectly, but the conventional structure with chip sealing has a drawback that flux cleaning cannot be performed. In addition, semiconductor chips used in recent flip-chip mounting are highly integrated, high-speed,
Since it has high power, it is necessary to fully consider the heat dissipation method. In that case, a method of directly cooling by creating an air flow or a liquid flow in the gap where the substrate and the chip are connected is an efficient method, but there is a drawback that this method cannot be adopted. In addition, since the conventional solder bump structure consists of bumps made only of solder, it is possible to prevent the pressure from the surface of the substrate and the semiconductor chip due to the temperature rise during operation, or the planar displacement due to thermal stress such as temperature cycle. There was a risk that the solder joints would be weakly deformed and short-circuited or broken. Further, since the power supply to the inside of the chip is performed only from the CCB bumps or solder bumps, the wiring resistance of the substrate is high and the resistance of the minute CCB bumps or solder bumps is also high, so that it has a considerable resistance as a whole. Had the drawback of causing a descent. Also with respect to GND, there is a drawback that high resistance causes noise generation. Further, in recent chips, the wiring structure has become a complicated multi-layer wiring structure in accordance with high integration, and there is a problem that the wiring of the chip is destroyed by handling when forming bumps on the chip.

[0004]

The semiconductor device of the present invention comprises:
CCB bumps for signal / power / GND and a plurality of large-area circular power / GND connecting parts provided on the periphery of the board, and chips for signal / power / GND CCB bumps and power / GND It is characterized in that a connecting portion is provided at a position corresponding to each connecting portion, and the substrate and the chip are connected by soldering.

Further, the wiring conductor on the substrate for connecting the power / GND connecting portion and the signal / power / GND CCB bump is soldered to the wiring conductor on the chip over the entire length.

Also, any signal, power supply, GND CC
A feature is that a copper core is embedded inside the B bump and the power supply / GND connection portion.

[0007]

According to the above-described structure, the organic solvent can enter the solder connection portion between the chip and the substrate, and the flux attached to the solder connection portion can be removed by cleaning during reflow. In addition, since a large-area power source and a plurality of GND connection portions are provided around the chip, the power supply voltage drop and noise generation can be minimized.
Further, since the solder connection area increases, the connection strength between the substrate and the chip increases, and the amount of heat conduction to the substrate also increases, contributing to improved heat dissipation. In addition, it is possible to prevent the destruction of solder bump connections by mechanical pressure tests such as static pressure, vibration, impact, constant acceleration tests, etc. from the backside of the semiconductor chip or substrate surface, and thermal stress generation due to thermal expansion difference such as temperature cycle. It becomes possible by incorporating the core, and the reliability can be improved. Further, since the solder bumps are formed not on the chip side but on the substrate side which is easier to handle, there is no problem of breaking the wiring of the chip.

[0008]

Embodiment 1 FIGS. 1 and 2 are a partial sectional view and a partial plan view of Embodiment 1 of the present invention. (FIG. 1 is a partial cross-sectional view taken along the line AA 'in FIG. 2.) The semiconductor device of the first embodiment will be described below with reference to FIGS. A circular signal on the surface of the substrate 1 made of ceramic such as alumina or aluminum nitride.
The power source / GND CCB bump 10 is formed by solder plating on the surface of the copper core 15. Further, a CCB bump having the same structure and a large diameter is formed around the CCB bump 10 as a power source / GND connecting portion 17. And
The semiconductor chip 2 is connected to the substrate 1 by soldering with the element formation surface facing downward. The connection electrodes to the bumps of the semiconductor chip 2 are formed by laminating titanium, titanium nitride and gold in this order on the surface of the semiconductor chip 2. The frame-shaped seal ring 16 portion around the substrate and the cap 18 made of a ceramic such as alumina or aluminum nitride are connected by an Au-Sn eutectic alloy for hermetic sealing. The cap 18 has a recessed shape in which the semiconductor chip 2 can be mounted, and the recessed lower surface 19 and the backside of the semiconductor chip are connected by solder, Au—Sn eutectic alloy, or the like. Tungsten metallization for connecting to the back surface of the semiconductor chip 2 is applied to the lower surface 19 of the recess in advance, and the metallized portion is electrically connected to the cap seal portion 20 through the through hole 21. Board 1
A copper core plated with nickel and gold in this order is formed on the side opposite to the chip connection surface, and the copper core and the circuit board 23 made of ceramic or glass-epoxy are connected by soldering. The CCB bumps on both sides of the substrate 1 are connected to each other through the through holes 21. In order to reliably connect the semiconductor chip and the substrate, it is important that the height and surface condition of each CCB bump are uniform. Therefore, the through hole 21 is provided at a position deviated from immediately below the CCB bump.

To assemble such a semiconductor device, for example, the following is performed. First, the substrate 1 and the semiconductor chip 2 are aligned with a flip chip bonder, and then heated in a nitrogen atmosphere while using flux to apply CCB on the substrate.
The bumps 10, the large-diameter power source / GND connecting portion 17 and the connecting electrodes of the semiconductor chip 2 are connected. Then, it is washed with an organic solvent to remove the flux used for connection. Next, an Au-Sn preform is placed on the seal ring 16 and on the back surface of the chip, and then the cap 18 is placed and heated in a nitrogen atmosphere while pressurizing and sealing the cap seal portion 20. Next, the substrate 1 having the semiconductor chip 2 mounted on the circuit board 23 made of ceramic or glass-epoxy is soldered by the ordinary reflow method to complete the semiconductor device of the present invention.

A method of forming CCB bumps on the substrate 1 will be described here. First, a substrate made of alumina or aluminum nitride is prepared. Tungsten paste is embedded in the portion of the substrate to be the through hole 21 and is baked. In addition, the metallization of tungsten is applied to the portion where the bump is formed in order to increase the adhesion strength between the bump and the substrate. A thin copper underlayer serving as a plating electrode is attached to the entire surface of this substrate by sputtering or the like. Next, a dry film (resist film) is attached to the substrate and CCB
Bump 10, power supply / GND connection part 17, seal ring 1
6, exposure is performed using a mask having a copper core pattern of the wiring conductor 22, and development is performed. Next, copper is deposited by electrolytic plating, and the dry film and the underlayer are removed to complete the copper core. Next, the copper core on the semiconductor chip side is plated with solder for connecting to the chip. The copper core on the circuit board 23 side is also formed in the same manner, but nickel and gold are sequentially plated on the copper core on the circuit board side to complete the board 1.

According to the first embodiment of the present invention described above,
The following effects can be obtained. Since the CCB bump of the present invention is connected to the substrate by the solder coated with the copper and having the copper core built-in, the whole bump is not melted by the heating at the time of connection and the solder short circuit can be prevented. This also facilitates manufacturing work and stabilizes the quality.

Further, between the chip and the substrate and between the substrate and the circuit board, the copper cores of all the bumps receive a force in response to an external force or an internal stress in a direction perpendicular to the surface, and the stress is dispersed, so that the copper core of the bump is horizontal to the surface. With respect to external force or internal stress, the copper core 15 of the large-diameter power source / GND connecting portion 17 receives most of the force and has the effect of preventing the internal CCB bumps 10 from being broken, thereby improving reliability.

[0013]

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 3 is a partial sectional view of the second embodiment, and FIG. 4 is a partial plan view of the second embodiment. (FIG. 3 is a partial cross-sectional view taken along the line AA ′ in FIG. 4.) The difference from the first embodiment is that the power supply / GND connecting portion 17 and the power supply / GND connecting portion 17 on the opposite side are directly connected by the wiring conductor 22. In addition to being connected, it is also soldered to the semiconductor chip 2. This further strengthens the power supply and GND,
The power supply voltage drop and noise generation in the semiconductor chip are suppressed. Other parts are the same as those in the first embodiment.

[0014]

As described above, according to the present invention, the power source and the GND connection portion are constituted by the large-diameter CCB bumps around the semiconductor chip, whereby 1) the flow of the organic solvent for cleaning the flux at the time of solder connection can be prevented. Since it can be secured, flux can be removed. 2) Similarly, at the time of cooling, an air-cooled or liquid-cooled air flow or liquid flow can be passed through the gap between the substrate and the semiconductor chip, so that a cooling effect can be obtained. 3) Power supply GND
By providing a large number of devices, it is possible to prevent the power supply voltage drop in the substrate and the semiconductor chip and to supply a large current, thus suppressing noise generation. 4) Mechanical stress applied to the CCB bump connection between the semiconductor chip and the substrate, and between the substrate and the circuit substrate,
The large-diameter power supply / GND connection portion receives the thermal stress and has an effect of preventing the CCB bump connection portion from being broken. For example, in a temperature cycle test (-65 ° C to + 150 ° C) using an aluminum nitride substrate, a large-diameter power source, GN
Without the D connection, the 100% CCB bump connection broke in 100 cycles. However, if yes, 100
Even in the 0th cycle, no breakage of the CCB bump connection portion occurred. Regarding the heat dissipation, the difference in thermal resistance between the chip-sealed (securing the airtightness) and the divided and soldered is 20 to 20 for the divided and soldered.
A value of 30% lower was obtained. Further, the wiring resistance of the power supply / GND is 100 mΩ in the conventional example, but is 10 to 20 m in the present invention.
It has been reduced to Ω.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a plan view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a first example of conventional flip-chip connection.

FIG. 6 is a perspective view of a second example of conventional flip-chip connection.

FIG. 7 is a cross-sectional view of a third example of conventional flip-chip connection.

8 is a plan view showing the structure of the semiconductor chip or substrate in FIG.

9 is a plan view showing the structure of the semiconductor chip or substrate in FIG. 7. FIG.

[Explanation of symbols]

 1 Substrate 2 Semiconductor Chip 3 Electrode 4 Solder Joint 5 Through Hole 6 Metallization 7 Solder Bump 8 Solder Frame 9 Silicon Wiring Board 10 CCB Bump 11 Sealing Part 12 Film Carrier 13 TAB Bump 14 Lead 15 Copper Core 16 Seal Ring 17 Power Supply・ GND connection portion 18 Cap 19 Bottom surface of recess 20 Cap seal portion 21 Through hole 22 Wiring conductor 23 Circuit board 24 Cooling plate 25 Cooling pipe 26 Bellows 27 Spring 28 Solder

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroaki Uchida 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation

Claims (5)

[Claims] 1. A flip-chip structure semiconductor device in which a bump provided on a substrate and an electrode provided on a semiconductor chip are connected to each other, and a plurality of large-diameter copper cores provided so as to surround an outer periphery of the semiconductor chip are incorporated. A semiconductor device having a flip chip structure, characterized in that a semiconductor chip is connected to a substrate having a bump and a plurality of small diameter copper core built-in bumps surrounded by the large diameter copper core built-in bump. 2. A wiring conductor is provided on the substrate from the large diameter copper core built-in bump to the small diameter copper core built-in bump connected to an electrode inside the semiconductor chip, and a surface of the wiring conductor is on the chip. The flip-chip structure semiconductor device according to claim 1, wherein the semiconductor device is connected to the semiconductor device. 3. The semiconductor device having a flip chip structure according to claim 1, wherein the bump having a large diameter copper core is used for supplying power to the semiconductor chip. 4. The copper core built-in bumps on the front surface of the substrate having the copper core built-in bumps formed on both sides are connected to the semiconductor chip, and the copper core built-in bumps on the back surface of the substrate are connected to a circuit board. A semiconductor device having a flip-chip structure. 5. The copper core built-in bumps on the front surface of the substrate and the copper core built-in bumps on the back surface of the substrate are connected by through holes, and the through holes are provided at positions deviated from directly below the copper core built-in bumps. The semiconductor device having a flip-chip structure according to claim 4.