JPH06233264A - Clock regenerator - Google Patents

Abstract

PURPOSE:To stabilize the regeneration of a clock by transmitting a sampling clock by inserting it into a horizontal synchronizing signal or a vertical synchronizing signal, and separating it at a display device side, and regenerating the sampling clock synchronized with a video signal. CONSTITUTION:At the time of transmitting a display control signal 15 or the video signal 16 from a controller 1 to the picture display device 2 for the sake of the regeneration of the clock, the sampling clock 12 is transmitted while being inserted into the horizontal synchronizing signal 11 in advance by a multiplexing part 3. After this signal is received by the receiving part 5 of the picture display device 2, a branching filter part 6 separates the sampling clock in a period when a display timing signal 13 is a 'H' level from the horizontal synchronizing signal. The sampling clock separated in this way is inputted to a clock regenerating part 7. This clock regenerating part 7 outputs the clock synchronized with that sampling clock as long as the sampling clock exists, and regenerates the clock, but during the period when no sampling clock exists, it makes a PLL run freely.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device connected to a workstation or the like, and to a clock reproducing device for reproducing a sampling clock required for capturing a video signal on the display device side.

[0002]

2. Description of the Related Art In recent years, flat display devices such as liquid crystal display devices and EL display devices have been attracting attention as a substitute for CRT (Cathod Ray Tube) display devices for display devices such as workstations. In these flat type display devices, the scanning cycle output from a workstation or the like is often different from the scanning cycle on the display device side due to problems such as display panel performance. In this case, the frame memory is used to store the data once, and the data is output in synchronization with the scanning cycle on the display device side.
Although the scanning cycle is converted, a sampling clock is required on the display device side to capture a video signal. At this time, when a high-frequency sampling clock is transmitted from a system device such as a workstation, when the transmission cable becomes long, the waveform is distorted and jitter occurs, which causes a problem that the video signal cannot be accurately captured. For this reason,
It is necessary to reproduce the sampling clock on the display device side. A means for reproducing the sampling clock is described in, for example, the document "Digital Technology in Broadcasting" (publisher: Japan Broadcast Publishing Association, published December 20, 1982, pages 164-165), as shown in FIG. PLL like
There is a method using (Phase Lock Loop). In FIG. 5, 10 is a voltage controlled oscillator.
Reference numeral 8 is a phase comparator, 18 is a frequency divider, 11 is a horizontal synchronizing signal, and 14 is a sampling signal for capturing a video signal. Here, if the horizontal scanning period of the display device is 800 times the cycle of the sampling clock for capturing the video signal, the frequency division value of the frequency divider is 800. At this time, the output 14 of the voltage controlled oscillator 10 is divided into 1/8 by the frequency divider, and then input to the phase comparator 8 to detect the phase difference from the horizontal synchronizing signal 11. The voltage controlled oscillator 10 is controlled by the output of the phase comparator 8 so as to eliminate the phase difference, and as a result, the sampling clock 14 synchronized with the horizontal synchronizing signal 11 is transmitted.

[0003]

The method of regenerating the sampling clock by using the PLL from the horizontal synchronizing signal as described above is generally known as a clock regenerating method. However, as the screen size of the display device increases and the number of pixels increases, the frequency of the sampling clock increases, and when reproducing the sampling clock from the horizontal synchronizing signal, the frequency division value by the frequency divider becomes very large. When the frequency division value is large like this, the PLL is not stable and it is difficult to reproduce the sampling clock.

An object of the present invention is to provide a clock reproducing device for an image display device which can always obtain a stable sampling clock.

[0005]

In order to solve the above problems, the present invention provides a system comprising an image display device and a control device for transmitting a signal to the display device, in which a video signal and a display control signal are transmitted from the control device. When transmitting, insert the sampling clock required for capturing the video signal into the horizontal synchronization signal or the vertical synchronization signal in advance on the control device side, separate it on the display device side, and reproduce the sampling clock. Constitute.

[0006]

According to the present invention, the sampling clock necessary for capturing the video signal is inserted into the horizontal synchronizing signal or the vertical synchronizing signal on the control device side, and this is separated on the receiving device side to reproduce the clock. Since the clock is reproduced, the clock can be reproduced more stably and in synchronization with the video signal than the method of reproducing the clock using the PLL from the horizontal synchronization signal. Therefore, the video signal can be accurately captured in the display device. It is possible to prevent the dot shift of the display screen.

[0007]

1 and 3 are block diagrams of a signal transmission system from a control device 1 to an image display device 2 according to an embodiment of the present invention. In FIG. 1, a sampling clock 12 for capturing a video signal is inserted into a horizontal synchronizing signal 11 and the
2 is a system for reproducing a clock by the LL system, and FIG. 2 is a system for inserting the sampling clock 12 into the vertical synchronization signal 17. Further, these time charts are shown in FIGS. The operation of the embodiment shown in FIG. 1 will be described below.
In the present invention, when the display control signal 15 and the video signal 16 are transmitted from the control device 1 to the image display device 2 for clock reproduction, the sampling clock 12 is inserted into the horizontal synchronizing signal 11 in advance by the multiplexing unit 3. Send. At this time,
In the synthesizing unit 3, the display timing signal 13 indicating the effective period of the video signal to be transmitted to the image display device is “H”.
The sampling clock 12 can be inserted only during the level period. This is the receiving unit 5 of the image display device 2.
After the reception, the demultiplexing unit 6 separates the sampling clock of the display timing signal 13 during the "H" level period from the horizontal synchronizing signal. The sampling clock thus separated is input to the clock recovery unit 7. The clock regeneration unit is a PLL circuit including a phase comparator 8, a loop filter 9, and a voltage controlled oscillator 10. While the sampling clock is present, the clock regeneration unit outputs a clock synchronized with this clock to regenerate the clock. During the period when the clock runs out, the PLL self-runs so that a stable sampling clock synchronized with the video signal can be obtained even when the input sampling clock runs out.

In the embodiment of FIG. 2, the period of the vertical synchronizing signal is detected by counting the horizontal synchronizing signal 11 instead of the display timing signal 13, and this is used to detect the vertical synchronizing signal 17 and the sampling clock 12.
Are combined and demultiplexed.

In the second embodiment, a PLL without a frequency divider is used for clock recovery, but a PL with a large frequency division ratio is used.
Since the operation is more stable than L, it is resistant to waveform distortion and jitter during long-distance transmission, and stable clock reproduction is possible.

[0010]

According to the present invention, a sampling clock required for capturing a video signal on the display device side is inserted into a horizontal synchronization signal or a vertical synchronization signal and transmitted, and the display device side separates the sampling clock. Since a sampling clock synchronized with a video signal is reproduced, a stable clock that is stronger against external noise and changes in ambient temperature than a method of reproducing a clock by a PLL method using a generally known horizontal synchronization signal as a reference signal. Can be reproduced. Further, even in the case of long-distance transmission, it is possible to use a PLL with a small frequency division ratio, so that the PLL is stable and it is possible to reproduce a clock that is strong against waveform distortion and jitter. As a result, the video signal can be accurately taken in by the display device, and it becomes possible to prevent dot shift and the like on the display screen.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a time chart of a horizontal synchronizing signal and a sampling clock.

FIG. 4 is a time chart of a vertical synchronizing signal and a sampling clock.

FIG. 5 is an explanatory diagram of a conventional clock recovery method.

[Explanation of symbols]

1 ... System device, 2 ... Image display device, 3 ... Multiplexing unit, 4
... transmission section, 5 ... reception section, 6 ... demultiplexing section, 7 ... clock recovery section, 8 ... phase comparator (PC), 9 ... low-pass filter (LP)
F), 10 ... Voltage controlled oscillator (VCO), 11 ... Horizontal synchronizing signal, 12 ... Sampling clock, 13 ... Display timing signal, 14 ... Reproduction sampling clock, 15 ... Other display control signal, 16 ... Video signal, 1
9 ... Composite signal of 11 and 12.

Claims (2)

[Claims] 1. A system comprising an image display device and a control device for transmitting a video signal and a display control signal to the image display device, wherein a video signal is added to a horizontal synchronization signal transmitted from the control device to the image display device. A clock reproducing device characterized by inserting and transmitting a sampling clock for capturing, separating the horizontal synchronizing signal and the sampling clock on the image display device side, and further reproducing the sampling clock using the sampling clock as a reference signal. . 2. A vertical synchronization signal transmitted from a control device to an image display device by inserting and transmitting a sampling clock for capturing a video signal, and the image display device side separates the vertical synchronization signal from the sampling clock. A clock reproducing device, which reproduces a sampling clock using the sampling clock as a reference signal.