JPH06245144A - Method for driving solid-state image pickup device - Google Patents

Abstract

PURPOSE:To attain high speed reset of floating diffusion. CONSTITUTION:At first levels of phiH, phiR are set to high levels respectively to store a signal charge Q under a gate electrode 3 and to reset the potential of an impurity region 6. At that time lots of charges stored in the impurity region 6 are swept out to an impurity region 7 but untransferred charges QR remain. Then a drain voltage VRD of a reset transistor(TR) RT goes to a low level and the potential of the impurity region 7 is set lower than that of the impurity region 6. The potential of the impurity region 6 is fixed to a low level of VRD by the injection of the charge from the impurity region 7. Then the phiR goes to a low level and the impurity region 6 is in the floating state. Then the phiH goes to a low level, the signal charge under the gate electrode 3 flows to the impurity region 6 to change the potential of the impurity region 6. The change in the potential is outputted through a source follower circuit SF.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a solid-state image pickup device using a charge transfer device.

[0002]

2. Description of the Related Art A solid-state image pickup device using a charge transfer device represented by a charge-coupled device (CCD) has recently been put into practical use due to its superiority in low noise characteristics. A charge detection circuit called a floating diffusion amplifier that performs charge-voltage conversion is used in such a solid-state imaging device. Hereinafter, a conventional solid-state imaging device and a driving method thereof will be described with reference to the drawings.

FIG. 3 shows the sectional structure and potential of each part when the floating diffusion amplifier is used in the output circuit of the CCD, and FIG. 4 shows the clock timing of the voltage applied to each terminal. In FIG. 3, a second conductive type diffusion layer 2 is formed on a first conductive type semiconductor substrate 1. A CCD final gate electrode 3 and a potential barrier forming gate electrode 4 are arranged on the diffusion layer 2.
A clock φ _H for charge transfer is applied to the CCD final gate electrode 3.
Is applied, and a DC voltage V is applied to the potential barrier forming gate electrode 4.
_OG is applied.

Adjacent to the potential barrier forming gate electrode 4, a MOS transistor including a gate electrode 5 and second-conductivity-type high-concentration impurity regions 6 and 7 is formed. This is the reset transistor RT, the clock phi _R is applied to the gate electrode 5 becomes an ON state when the clock phi _R to the high level. A DC voltage V _RD is applied to the impurity region 7. The impurity region 6 is called a floating diffusion and is connected to the gate of the output source follower transistor Tr ₁ .

Next, the operation will be described. The potential diagrams at times t1 to t3 in FIG. 3 correspond to times t1 to t3 in FIG. 4, respectively. At time t1, φ _H is at high level, and as shown in FIG. 3, a potential well is formed under the CCD final gate electrode 3 and the signal charge Q is accumulated. Also,
φ _{R is} also at high level, the reset transistor RT is in the ON state, and the impurity region 6 is reset to the voltage V _RD applied to the impurity region 7.

Next, at time t2, the reset clock φ _R becomes low level, and the reset transistor RT is turned off. When the reset clock φ _R changes from the high level to the low level, the potential of the impurity region 6 is slightly lowered due to the capacitive coupling between the gate electrode 5 and the impurity region 6, and then the floating state is established. Next, at time t3, the CCD drive clock φ _H becomes low level, the signal charges Q stored under the CCD final gate electrode 3 cross over the potential barrier under the potential barrier forming gate electrode 4, and the impurity region 6 and changes the potential of the impurity region 6. This change in potential is due to the source follower circuit S
It is output through F.

The charge detector of the solid-state image pickup device must output a voltage proportional to the amount of signal charge for one bit transferred from the CCD to the impurity region 6. In the conventional solid-state imaging device as described above, the signal charge for one bit transferred to the floating diffusion (impurity region 6) is completely swept out by the time the signal charge for the next bit is transferred. It is about to be reset.

[0008]

The conventional solid-state image pickup device has the following drawbacks. The impurity region 6 is made to have a high concentration because the source follower transistor Tr ₁ for output is used.
In order to make contact with the aluminum wiring for connecting to the gate, the smaller area of the impurity region 6 is better in terms of charge-voltage conversion efficiency. Therefore, the gate electrode 5 of the reset transistor RT and the impurity region 6 do not overlap in position. Therefore, even if the reset transistor RT is turned on, it takes a long time for the signal charge accumulated in the impurity region 6 to move to the impurity region 7 which is the drain of the reset transistor RT, which makes it difficult to perform high-speed reset.

An object of the present invention is to provide a driving method of a solid-state image pickup device which enables high-speed resetting of floating diffusion and can output a voltage proportional to the amount of signal charges.

[0010]

According to the method of driving a solid-state image pickup device of the present invention, while the voltage applied to the gate electrode of the reset transistor is at a high level, that is, while the reset transistor is in the ON state, the reset transistor Lower the drain potential.

[0011]

According to the driving method of the solid-state image pickup device of the present invention,
By injecting a fixed amount of charge from the drain of the reset transistor to the source at high speed, the charge detection unit can be reset at high speed and an output proportional to the amount of signal charge can be obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the structure of a solid-state image pickup device according to the present invention and the potential state of each part. The structure is the same as the conventional one. FIG. 2 is a diagram showing a driving method of the solid-state imaging device according to the present invention. The difference from the prior art is that the voltage V _RD applied to the impurity region 7 that is the drain of the reset transistor RT has a clock waveform instead of a direct current.

Next, the operation will be described. The potential diagrams at times t1 to t4 in FIG. 1 correspond to times t1 to t4 in FIG. 2, respectively. At time t1, φ _H is at high level, and as shown in FIG. 1, a potential well is formed under the CCD final gate electrode 3 and the signal charge Q is accumulated. Also,
φ _{R is} also at high level, and the reset transistor RT is in the on state. Since the barrier between the impurity region 6 and the impurity region 7 disappears, the signal charge accumulated in the impurity region 6 is swept out to the impurity region 7 due to the potential difference. A certain amount of time is required for the movement of the signal charges, and the untransferred charges Q _R remain in the impurity region 6 when operating at high speed. In particular, in order to increase the charge-voltage conversion efficiency, the diffusion layer 2
This is conspicuous when the diffusion layer 2 is depleted by lowering the impurity concentration of.

Next, at time t2, the drain voltage V _RD of the reset transistor RT is at low level,
The potential of the impurity region 7 becomes lower than that of the impurity region 6. That is, the source and drain of the reset transistor RT formed of the impurity regions 6 and 7 and the gate electrode 5 have been replaced with each other as compared with the time t1.
Then, charges flow from the impurity region 7 toward the impurity region 6, and the charge Q _C is accumulated in the impurity region 6.

The charge transfer is much faster than the charge transfer at the time t1 because the high-concentration impurity region is on the side operating as the source of the transistor RT. Although electric charges accumulated in the impurity region 6 becomes to the combined charge Q _C from untransferred charge Q _R and the drain, so that the potential of the impurity region 6 by total charge amount becomes equal to the drain voltage V _RD charge Q _C is naturally determined. From the above, the potential of the impurity region 6 is the drain voltage V
It is fixed at the low level of _RD .

The operation at the times t3 and t4 is the same as that at the times t2 and t3 in the conventional example. That is, the reset clock φ _R becomes low level, the reset transistor RT is turned off, and the impurity region 6 is brought into a floating state. Next, the CCD driving clock φ _H becomes low level, the signal charge Q stored under the CCD final gate electrode 3 gets over the potential barrier under the potential barrier forming gate electrode 4, and flows into the impurity region 6. , The potential of the impurity region 6 is changed. This change in potential is output through the source follower circuit SF. In the output waveform, the potential change due to the inflow of the charge Q _C appears in the reset period and does not affect the potential change due to the signal charge Q.

Further, as a result, although it is similar to the operation in which a part of the signal charge is not discharged and remains in the floating diffusion (impurity region 6), that is, the state of incomplete reset, the driving method of the present invention Since a fixed amount of charge is accumulated in the floating diffusion regardless of the amount of signal charge, it is a complete reset. As described above, while the reset clock φ _R is at the high level, charges are injected from the drain (impurity region 7) of the reset transistor RT to the floating diffusion (impurity region 6), and the floating
The electric potential of the diffusion can be fixed quickly.

[0018]

According to the method for driving a solid-state image pickup device of the present invention, high-speed reset operation is possible by injecting charges from the drain of the reset transistor into the floating diffusion while the reset transistor is in the ON state. .

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration and a potential state of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a diagram showing clock timing of a drive voltage of the solid-state imaging device which is an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional solid-state imaging device and its potential state.

FIG. 4 is a diagram showing clock timings of drive voltages of a conventional solid-state imaging device.

[Explanation of symbols]

1 Semiconductor Substrate 6 Impurity Region (Source, Floating Diffusion) 7 Impurity Region (Drain) 5 Gate Electrode RT Reset Transistor SF Source Follower Circuit

Claims (1)

[Claims] 1. A second conductivity type diffusion region formed on a first conductivity type semiconductor substrate or a semiconductor layer, a potential barrier forming gate electrode adjacent to the diffusion region, and a potential barrier forming gate electrode adjacent to the potential barrier forming gate electrode. Of a CCD final gate electrode, a reset transistor of the diffusion region formed by using the diffusion region as a source electrode, and a source follower circuit that operates with the potential of the diffusion region as an input and outputs an output signal. A driving method, wherein a binary pulse changing from a high level to a low level is applied to a drain electrode of the reset transistor while a voltage applied to the gate electrode of the reset transistor is at a high level. Driving method for solid-state imaging device.