JPH0627131Y2 - Receiver circuit of ultrasonic diagnostic equipment - Google Patents

Description

The present invention relates to a receiving circuit of an ultrasonic diagnostic apparatus, and more particularly to a receiving circuit of an ultrasonic diagnostic apparatus that prevents transmission pulses from leaking to the receiving circuit.

(Prior Art) An ultrasonic diagnostic apparatus is an apparatus that irradiates ultrasonic waves into a subject, receives ultrasonic waves reflected from a tissue, a lesion, or the like, forms an image, and diagnoses. An ultrasonic diagnostic apparatus normally transmits and receives pulsed ultrasonic waves, and a probe, which is an electroacoustic transducer for transmitting and receiving waves, uses the same type for both transmission and reception. The same transducer element is used for both transmission and reception because of different timings. Therefore, for the purpose of preventing damage to the receiving circuit during transmission, a protection circuit is provided so that large-power transmission pulses do not enter the receiving circuit.

A configuration example of a conventional receiving circuit is shown in FIG. The figure shows the continuously variable aperture portion in the receiving circuit. In the description of the drawing, description of the resistance capacitor that does not perform a special operation for protecting the receiving circuit will be omitted. In the figure, 1a is an N-channel junction type field effect transistor (hereinafter referred to as FET) whose drain terminal is connected to the element CH0, and whose source terminal is connected to the base of a buffer amplifier transistor 2a which is an NPN transistor. . Similarly, in 1b, the drain terminal is the CH1 element and the source terminal is the buffer amplifier transistor 2
An FET 1n connected to the base of b is an FET inserted between the CHn element and the buffer amplifier transistor 2n. The input control voltage is divided by a voltage dividing resistor group and applied to each gate of the FETs 1a to 1n. A control voltage is applied to one end of this voltage dividing resistor group,
The other end is connected to the ground potential. Then, the control voltage is changed from a negative potential to a zero potential to control the gate voltage of each FET 1a to 1n. At the time of transmission, a negative potential of a predetermined magnitude is applied to close the gate of the variable aperture circuit. During reception, the magnitude of the negative potential is reduced to open the gate and at the same time weighting is performed to enable reception. FETs 1a to 1n are N-channel junction type FETs
Therefore, when a signal of a certain negative potential is supplied to the control voltage, the gate voltage is F at the ground potential.
The signal of CH0 connected to ET1a is most easily passed, and the larger the channel number of CH1, CH2, ..., CHn in the figure, the more the signal is attenuated to realize the weighting for the reception aperture.

(Problems to be solved by the invention) However, in the conventional circuit shown in FIG. 4, the control voltage applied to one end of the voltage dividing resistor group is the FET.
Even if the negative potential is sufficient to turn off the gate of, the negative potential applied to the gate by the FET 1a of the CH0 path and the FET of the channel close to it is close to the ground potential. Almost always on. Therefore, the strong transmitted high-voltage pulse leaked to the receiving circuit immediately after the transmission is CH0 and FE near it.
There is a drawback in that the receiving circuit that passes through T and receives it is saturated, which causes noise in the finally displayed image.

The present invention has been made in view of the above-mentioned points, and its purpose is to change the components of high-voltage pulse leakage immediately after transmission to the variable aperture portion without changing the variable aperture portion or the portion generating the control voltage. It is to realize a receiving circuit of an ultrasonic diagnostic apparatus that prevents noise from appearing on an image by shutting out and preventing saturation of the receiving circuit.

(Means for Solving the Problem) The above-mentioned problem is that the control voltage applied to one end of the resistance voltage dividing means is divided and applied to the control input terminal of the semiconductor element of each channel, and weighting is performed for each channel. Also, in the receiving circuit of the ultrasonic diagnostic apparatus having the variable opening means for opening and closing the gate, the semiconductor element, which is connected to the other end of the resistance voltage dividing means, closes the gate before starting the transmission and is set from the start of the transmission. This is solved by a receiving circuit of an ultrasonic diagnostic apparatus, which is provided with a leakage voltage cutoff means for generating an electric potential for closing a gate every predetermined time.

(Operation) The control voltage is divided by the resistance voltage dividing means and applied to the control input terminal of the semiconductor element of each channel, whereby the opening and closing of the gate of the semiconductor element of each channel is controlled. Further, the potential generated by the leakage voltage cutoff means is applied to the control input terminal of the semiconductor element from the other end of the resistance voltage dividing means, and is applied to the control input terminal of the semiconductor element from the wave transmission, and the wave transmission is started before the wave transmission is started. The gate of the variable opening means is controlled to be surely closed until a predetermined time later.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In the figure, the same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, reference numeral 3 is a leakage voltage cutoff circuit according to the present invention, which is composed of the following members. Reference numeral 4 is a non-inverting amplifier that amplifies the phase of the signal supplied to the point A without inverting it, and applies an output to the base of the PNP transistor 5. Reference numeral 6 denotes an NPN transistor in which the collector terminal of the PNP transistor 5 is connected to the base terminal, and the capacitor 7 and the resistor 8 are connected to the collector terminal thereof, and this point is designated as B. The capacitor 7 is an NPN transistor 6
Is charged, the voltage is charged by the power supply of -V through the emitter and collector of the NPN transistor 6. The resistor 8 discharges the electric charge charged in the capacitor 7 when the NPN transistor 6 is not conducting due to the time constant with the capacitor 7. Reference numeral 9 denotes an emitter follower PNP transistor for transmitting this potential to a subsequent stage when the charge charged in the capacitor 7 is discharged through the resistor 8 and the potential at the point B rises. PNP
This is a potential correction NPN transistor for correcting the potential that has changed by the base-emitter voltage V _{BE of the} transistor 9. When the emitter current sufficiently flows through the NPN transistor 10, the emitter potential approaches from the negative potential to the ground potential, so that the FET 1a ~ 1n starts conduction. C is FET
A signal input point for supplying a control signal to each gate of 1a to 1n, and D is a connection point between the emitter of the NPN transistor 10 and the gate of the FET 1a. That is, a voltage dividing resistor group is arranged between the points C and D, and the divided control voltage is applied to the gate terminals of the FETs 1a to 1n. The output of the leakage voltage cutoff circuit 3 is applied to the other end point D of the resistor group.

Next, the operation of the embodiment configured as described above will be described with reference to FIGS. 2 and 3. In FIG. 2, (a) is a time chart of the voltage change of the system timing signal supplied to the point A of the above circuit, which is transmitted at the rising time of the voltage waveform. (B) is a time chart of the control signal supplied to point C, and (c) is a time chart of the voltage waveform appearing at point D. FIG. 3 is an enlarged view of the period of X including the transmission time point of FIG. 2, where (a) shows the time chart of the voltage of the system timing signal at point A, and (b) shows the control signal at point C. The voltage time chart, (C) is a time chart of the voltage waveform appearing at point D. (A) The wave transmission is started at the rising time t ₀ of the system timing signal shown in the figure, and the wave transmission is finished within a short time of the wave transmission pulse width. The control signal in (b) gradually rises, but is almost -Vc during the X period.
And -Vc is a negative voltage sufficient to turn off the FET.

First, the operation of the circuit before and after the application of the system timing signal supplied to the point A will be described. Before the transmission timing point t _0, the signal given to the point A is 0V, and P
The NP transistor 5 is turned on, the base voltage of the NPN transistor 6 becomes a positive voltage from the voltage -V, and the NPN transistor 6 is turned on. Therefore, the capacitor 7 is charged by the conduction of the NPN transistor 6, and the voltage V ₀ across the capacitor 7 becomes −V + V _S.
Here, + V _S is the emitter-collector voltage when the NPN transistor 6 is saturated. Since this V ₀ is the base voltage of the PNP transistor 9, the PNP transistor 9 is sufficiently in the ON state, the voltage of the base of the NPN transistor 10 connected to its emitter is lowered, and the NPN transistor 10 is turned off. It is in the near ON state. Therefore, the voltage at point D is -V + V _S , which is equal to the base voltage of the PNP transistor 9. VS _is-
It is extremely smaller than V, that is, the source voltages of the FETs 1a to 1n are close to -V, so the FETs 1a to 1n are off. This is the state before t ₀ in FIG.

After the wave transmission timing point, the system timing signal at point A is a positive voltage and the PNP transistor 5 is turned off, as shown in FIG. Along with this, the NPN transistor 6 is also turned off, but due to the influence of the electric charge accumulated in the base of the NPN transistor 6, it is N
PN transistor 6 is not conducting, the voltage across the capacitor 7 is also maintained -V + V _S. When the above-mentioned base charge is discharged, the NPN transistor 6 is turned off, the charge charged in the capacitor 7 is discharged through the resistor R with the time constant of CR, and the voltage across the capacitor 7 changes according to the following equation.

V ₀ = (− V + V _S (e ^{−t / CR} )) As the capacitor 7 discharges and the voltage rises, the emitter current of the PNP transistor 9 decreases and the collector current of the NPN transistor 10 increases. The voltage gradually rises as shown in Fig. 3. (c) In the figure, t _S is the time from when the wave is transmitted until the voltage at point D begins to rise. The voltage at point D goes up and V _ON
The gate voltage of the FETs 1a to 1n rises to reach FE
T1a to 1n are turned on. This time is the t _OFF time shown in FIG. 3C and is determined by the time constant CR of the capacitor 7 and the resistor 8. In this way, the FETs 1a to 1n do not operate for the time t _Off after the wave is transmitted, and the leakage component of the high-voltage pulse immediately after the wave is transmitted is shut out to prevent saturation of the receiving circuit.

The present invention is not limited to the above embodiment. As each transistor, an NPN transistor and a PNP transistor were used in the order shown in FIG. 1, but this is not limited to the circuit of the embodiment, and the transistor can be used in any way as long as it has the same effect. it can.

(Effect of the Invention) As described in detail above, according to the present invention, by adding the leakage voltage cutoff circuit, it is possible to prevent the transmission pulse from leaking without changing the variable opening portion or the circuit portion generating the control voltage. The variable aperture can surely block the light, so that saturation of the receiving circuit can be prevented, and finally noise can be prevented from appearing on the image, which is a great practical effect.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a time chart of signals supplied to points A and C of the circuit of the embodiment, and FIG. 3 is an enlarged view of an X portion of the chart of FIG. FIG. 4 is a circuit diagram of the conventional variable aperture section. 1a to 1n ... FET 2a to 2n ... Buffer amplifier transistor 3 ... Leakage voltage prevention circuit 5, 9 ... PNP transistor 6, 10 ... NPN transistor 7 ... Capacitor, 8 ... Resistor

Claims (1)

[Scope of utility model registration request] 1. A variable opening means for dividing a control voltage applied to one end of a resistance voltage dividing means and applying the divided voltage to a control input terminal of a semiconductor element of each channel to perform weighting for each channel and opening / closing of a gate. In the receiving circuit of the ultrasonic diagnostic apparatus having the above, a potential that is connected to the other end of the resistance voltage dividing means, closes the gate before the semiconductor element starts transmitting, and closes the gate after a predetermined time set from the start of transmitting. A receiver circuit for an ultrasonic diagnostic apparatus, comprising: a leakage voltage cutoff means for generating a noise.