JPH06290136A - Duplex adaptor - Google Patents

Abstract

(57) [Abstract] [Purpose] In a computer system, eliminate the hardware settings when connecting a single CPU to a dual adapter that is specified for dual CPU. [Structure] Alarm signal lines 3a, 3 on which the alarm signal goes
b is provided with resistors 31 and 32 for pulling them up to a level indicating that the alarm signal is active ("H"). Alarm signal line to which the CPU is not connected
The presence of this resistor 31 or 32 causes 3a or 3b to function in the same manner as the abnormal occurrence related to the alarm signal generation, and is only connected.
The CPU will live.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a computer system.
The present invention relates to a dual adapter used for dual CPU.

[0002]

2. Description of the Related Art In a large-scale or important computer system, a CPU is duplicated to ensure non-stop. The duplex adapter is used for that purpose and is interposed between the two CPUs and other hardware such as input / output devices and memory. The dual adapter is the main CPU
Detects the abnormality and detects an alarm that is issued,
The bus is switched so that the CPU side becomes valid.

Such a duplex adapter is used in a future CPU 2
There is a case where it is inserted in advance between one CPU and other hardware in preparation for duplication, or one of the two CPUs is removed for some reason. In order to operate the system without problems even in such a case, the conventional duplex adapter was equipped with pins and switches for setting a single CPU connection.

[0004]

[Problems to be solved by the invention] However, forgetting to set
This may result in a setting error and a poor connection, thus impairing the reliability of the system. The present invention has been made in order to eliminate such inconvenience, and does not require any setting operation.
It is an object of the present invention to provide a duplex adapter which can connect U and two CPUs.

[0005]

The duplex adapter according to the present invention is capable of connecting two CPUs, monitors the state of the two connected CPUs, and selects one healthy CPU. In a duplex adapter for transmitting and receiving data between the CPU and another device, a line through which a signal representing each of the states of the two CPUs is propagated and a logic level when the state of the CPU is abnormal in the line. And a potential holding circuit for holding a potential corresponding to

[0006]

When the connected main CPU is normal, the line is at "L" level. When this CPU becomes abnormal, the line becomes "H" level and the abnormality is detected.
Switch to CPU. When a single CPU is connected, the line on the sub CPU side is held at "H" level. Therefore, the data on the main CPU side is transmitted as valid data.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 shows a duplex adapter 3 of the present invention, a main CPU 1 and a sub CPU 2 connected to the duplex adapter 3, and an input device 41.
The output device 42 and the memory 43 are shown. Main CPU 1, sub CP
U 2 is connected to bus 2 via bus 11,21 and alarm signal lines 12,22
It is connected to the duplication adapter 3. When an abnormality occurs in the CPU 1 or 2, the CPU 1 or 2 outputs an "H" active alarm signal to the alarm signal lines 12 and 22. Alarm signal lines 12 and 22 are alarm signal lines in the duplex adapter 3.
It is connected to 3a and 3b and gives an alarm signal to the alarm identification section 33.

The alarm signal lines 3a and 3b are set to "H" level by the pull-up resistors 31 and 32. Bus 11,21
Is connected to the inputs of AND gates 34 and 35 via the bus in the duplex adapter 3. As shown in FIG. 2, the alarm identification unit 33 is composed of inverters 33a and 33b to which the alarm signal lines 3a and 3b are respectively connected, and an AND gate 33c whose inputs are the alarm signal line 3a and the output of the inverter 33b.
The output of the inverter 33a is given as α, and the output of the AND gate 33c is given as β to the AND gates 34 and 35. Table 1 is a truth table of the alarm identification unit 33.

[0009]

[Table 1]

The outputs of the AND gates 34 and 35 are connected to the bus to which the input device 41, the output device 42 and the memory 43 are connected, and the OR gate 36.
Given through.

In the device of the present invention having the above-described structure, when the main CPU is operating normally, no alarm signal is issued and the alarm signal line 3a is at "L" level, so α = "H". ", Β =" L ", and the data on the AND gate 34 side, that is, the data drop from the main CPU 1 is the output device.
It will be sent to 42 mag (Table 1). On the other hand, the main
Alarm signal line 3a when CPU 1 issues an alarm signal
Becomes "H" level. At this time, when the alarm signal line 3b of the sub CPU 2 is "L" (Table 1), α = "L"
, Β = “H”, and only the data on the side of the AND gate 35, that is, the data from the sub CPU 2 is sent to the output device 42 or the like.
At this time, when the alarm signal of the sub CPU 2 is also at "H" level (Table 1), both α and β of both signals are at "L" level, so that data from neither CPU 1 nor CPU 2 is output.

Next, when the sub CPU 2 is not connected to the duplication adapter 3, the line 3b operates by the pull-up resistor 32.
Holds to "H" level. Therefore, in this case, the AND gate 34 permits the data transmission from the main CPU 1, which corresponds to the state of Table 1. In other words, it is possible to send data from one CPU simply by connecting it to one CPU without any special settings. This is the same as in the state of Table 1, the alarm signal line 3a becomes "H" level by the action of the pull-up resistor 31 even when the main CPU 1 does not exist and the sub CPU 2 is only connected. Become secondary CPU 2
It is only possible to send data from. When the alarm signal is "L" active, a pull-down resistor may be used instead of the pull-up resistor.

FIG. 3 shows a part of a communication system in which a duplicating device similar to that described above is connected to a plurality of devices via extension adapters. Two devices A and B each having a CPU and an I / O unit are connected to the extension adapter 5 using their respective line units. The extension adapter 5 includes an alarm monitoring unit 51 and an alarm status notification unit 52. If the devices A and B are abnormal, the devices A and B output different alarm signals as will be described later. In response to this, the alarm monitoring unit 51 determines which device the alarm signal is from, and reports the result to the alarm state notification unit 52.

The extension adapter 5 is the duplex adapter 3 described above.
As with the above, it switches the circuit in the alarm state,
When an alarm is issued from the alarm state notifying unit 52 and the state of which device A, B is issued, switching of the modems A, B connected to the lines A, B is established in accordance with the standard. According to.

FIG. 4 shows an output signal of the alarm state notifying section 52. When both the devices A and B are normal, pulses of duty 1/2 are continuously output as shown in (A). Device A
When an alarm signal is input from, as shown in (B)
It becomes "L" level, and when an alarm signal is input from device B, it becomes "H" level as shown in (C). The switching device 6 sends such a signal to the alarm state identification unit 60.
It is determined by.

FIG. 5 shows another alarm state notification signal. This is a coded pulse. If both devices A and B are normal, 3 pulses as shown in (a), and if an alarm signal is input from device A, as shown in (b), 1
When an alarm signal is input from the pulse or device B
As shown in (c), two pulses are used, and when both alarm signals are input from devices A and B, long pulses are used.

When using the extension adapter 5 and the switching device 6 as described above, the switching device 6 can individually recognize the abnormality of the devices A and B, and can perform the switching corresponding to each of the abnormal devices. Become.

[0018]

When the device of the present invention as described above is used, the CPU
When using the dual adapter of with a single CPU connected, no hardware settings are required,
Therefore, the reliability of the system is improved without causing inconveniences such as forgetting setting, setting error, and contact failure.

[Brief description of drawings]

FIG. 1 is a block diagram of a device of the present invention.

FIG. 2 is a circuit diagram of an alarm identification unit.

FIG. 3 is a block diagram showing an example of use of an extension adapter.

FIG. 4 is a waveform diagram of an alarm status notification signal.

FIG. 5 is a waveform diagram of an alarm status notification signal.

[Explanation of symbols]

 1 Main CPU 2 Sub CPU 3 Duplex adapter 31,32 Pull-up resistor 3a, 3b Alarm signal line 33 Alarm identification section

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yasuo Tanaka 3-22-8 Hakataekimae, Hakata-ku, Fukuoka City, Fukuoka Prefecture Fujitsu Kyushu Digital Technology Co., Ltd. (72) Go Miura Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1015 Kamiodanaka, Fujitsu Limited

Claims (1)

[Claims] 1. A connection between two CPUs (1, 2) is possible, the state of the two connected CPUs (1, 2) is monitored, and one healthy CPU is selected and the other CPUs are selected. Equipment (41,
42, 43) in the duplex adapter (3) for transmitting and receiving data to and from the line (3a, 3b) through which signals representing the respective states of the two CPUs (1, 2) are propagated, and the line (3a, 3
A duplicated adapter comprising b) and a potential holding circuit (31, 32) for holding a potential corresponding to a logic level when the state of the CPU (1, 2) is abnormal.