JPH0629355A - Large-scale wiring board and manufacture thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To obtain a large-scale wiring board capable of compact and high-speed electrical signal processing by mounting LSI chips on a multilayer wiring board at high density without gaps. [Structure] A plurality of LSI chips 1 are fixed on a smooth support substrate 2 so as to be adjacent to each other with no space therebetween, and an insulating layer 4 and a wiring layer 5 are formed on the surface of this LSI chip group to provide a first substrate 30. Then, the wiring board 40 having the through holes 7a and the wiring patterns 8 formed thereon is mounted and fixed by adhesion, and the inside of the through holes 7a is filled by plating, and the upper and lower wiring layers 5 are formed through the plating layer 9. And 8 are electrically connected. The mounting of the wiring board 40, the adhesion fixing, and the electrical connection by the plating process are repeated to form a multilayer wiring of a desired number of layers. If the cooling mechanism housing 18 is provided on the back surface of the support substrate 2, the LSI chip can be effectively cooled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention requires high-density integration of a large-scale circuit such as an electronic device such as an electronic computer or an electronic exchange that needs to process an electrical signal at high speed. The present invention relates to a large-scale wiring board suitable for an electronic device, a method for manufacturing the same, and an electronic device using the same.

[0002]

2. Description of the Related Art In recent years, the performance of electronic equipment has come to be greatly influenced by a mounting technique for incorporating a large number of large-scale integrated circuits (LSIs) in a limited space. Already LSI
The external circuit and the connection part with the LSI are required to have a fine wiring pattern that cannot be formed with the wiring pitch in the printed circuit board which has been most used in the past, and the multilayer formed by the ceramic thick film printing technology. LSIs that use a thin film technology that enables the formation of finer circuit patterns on a wiring board, and a high heat resistant resin tape that uses a similar thin film technology to form the connection area
A technique called Tape-Automated Bonding (TAB), which is provided between a substrate and a substrate, has begun to be applied.
Generally, a connection method called wire bonding using a thin wire such as Au or a connection method using solder is used for connecting the wiring formed by the thin film technique and the LSI. In particular, among the connection methods using solder, the control-collapse-bonding (CCB) method is suitable for VLSI having a large number of terminals because the terminals can be drawn from the entire surface of the LSI chip. It has come to be used for substrates.

However, in the above-mentioned connection method, since the required area of the connection portion is several tens of μm in diameter, it is becoming more difficult to connect the wiring at a higher density, and moreover, the connection is required. However, there is also a drawback that the number of processes is increased because the special wiring layer structure is required. On the other hand, a technique of mechanically pressing the upper and lower electrodes with an adhesive to make electrical connection is being put to practical use. In this case, basically 20 μm
It is shown that the connection at the following wiring pitch is also possible. The problem with this connection method is that the adhesive remains between the upper and lower electrodes, so the electrical resistance of the connection is relatively high. Also, because the connection is made with an adhesive, the connection reliability under actual use conditions is basically not high, so it is difficult to apply to products that require high reliability such as communication devices and calculators. Is also a big problem.

In response to these problems, a bondingless interconnection method for electrically connecting an LSI chip and a wiring board without using a so-called bonding technique has been proposed and studied. As is typical in IC cards, by embedding an LSI chip in a thermoplastic resin, the surface of the LSI and the surface of the resin portion are flattened,
As a result, a technique has been reported in which a substrate in which the connection pads of the LSI are located on the surface of the substrate is formed and wiring between the connection pads is easily formed.

Further, as shown in FIG.
The SI chips 1 are arranged at a predetermined interval, a resin 23 is embedded between adjacent chips to fix the chips to the support plate 2, and the resin surface is flattened. At this time, the electrode pad 3 of the chip 1
The resin is removed so as not to remain on the upper surface, and then the insulating layer 4 is formed on the entire surface of the resin to provide a predetermined through hole. Next, a wiring metal is formed on the entire surface and then patterned by selective etching to form the wiring 5. The steps of forming the insulating layer 4 and the wiring 5 are repeated to form the wiring 5 of two layers in this example.

As a technique related to this kind of technique, for example, I-Y-I-Transaction CHM Vol. 10, No. 3 (1987).
Pages 310-313 [IEEE Transactions on C
onponents, Hybrids, and Manufacturing Tecnolog
y, Vol. CHMT-10, No. 3 Sept. 198
7, pp. 310-313] and JP-A-62-8174.
No. 5 publication is mentioned.

[0007]

Considering the original purpose of the high-density wiring board, it is to arrange electrical elements in a high density and connect them with the shortest wiring. The direction is the LSI itself. Therefore, multiple L
When connecting SI on a wiring board, it is necessary to arrange LSI chips themselves in high density. However, each of the above techniques is a wiring board connection method in the case where the size of the connection pad on one LSI and the distance between the pads are small, and until a plurality of LSI chips are densely connected to the wiring board. Was not considered. Therefore, in any of the examples, there was some difficulty in reducing the distance between the LSI chips.

Therefore, an object of the present invention is to solve the above-mentioned conventional problems, and the first object thereof is to provide a plurality of L's.
A second object is to provide a large-scale wiring board in which SI chips are mounted and fixed on a support substrate at high density with no gaps and a multilayer wiring structure is provided on the surface thereof. Especially.

[0009]

In order to solve the above-mentioned problems, in order to arrange the LSI chips at the highest density, the LSI chips of uniform thickness are adjacent to each other on the supporting substrate without any space, and the LSI chip group itself is formed. It should be fixed as if it were a single board. And the LSI on this board
When fixing chips, the electrode pads on which the chips are formed face up, the back surface is fixed to a supporting substrate, and the electrode pads on the substrate are placed between adjacent chips or through the same through through holes provided in the insulating layer. Wirings connected to the electrode pads in the chip are formed. The large-scale wiring board of the present invention has a structure in which wiring boards prepared separately are laminated in multiple layers on the board on which the LSI chip is fixed.

That is, when stacking wiring boards in multiple layers on a board on which a group of LSI chips is fixed, LS
A wiring board (for example, one formed on an insulating film) having a through hole in which a part of the wiring of the multilayer wiring such as the wiring in the I-chip or the wiring between the adjacent LSI chips is formed individually in advance, A wiring board is laminated and fixed on a board on which a group of the above LSI chips is fixed using an adhesive, and every time one layer is laminated, it is electrically connected to the lower layer wiring on the LSI chip side through a through hole by plating. To do. A desired large-scale wiring board can be realized by repeating the number of times of laminating the wiring board a desired number of times.

Specific means for achieving the object of the present invention will be described below. First, the first purpose is to arrange a plurality of LSI chips on a support substrate with the surface on which the electrode pads are formed facing upward without any gap, and to arrange the back surface on the surface of the LSI chip group fixed to the support substrate. A first substrate formed by forming a wiring layer connected to the electrode pad through a through hole arranged in an insulating layer, and a wiring substrate in which a wiring pattern is formed on an insulating sheet in which a through hole is formed in advance. The wiring board is fixed and laminated on the first board with an adhesive, and the wiring layer of the first board and the wiring pattern on the wiring board are electrically connected through the through holes of the wiring board. This is achieved by a large-scale wiring board having a plated metal layer for connection.

The wiring substrate to be laminated on the first substrate is not limited to a single layer (one), but a plurality of layers are fixed and laminated according to the circuit scale to form a multilayer wiring structure. In order to connect this large-scale wiring board to an external circuit, it is practical and preferable to connect a connector with a pin with a conductor on the wiring pattern on the outermost surface to form a wiring board with a connector. The connector is composed of a thick-film wiring board made of ceramics or the like, the connection pins are implanted on one surface, and the electrodes connected to the wiring pattern are formed on the other surface. This is connected to a wiring board by soldering and fixed to form a large-scale wiring board with a connector.

Further, it is desirable to dispose a cooling mechanism casing, for example, by water cooling, on the back surface of the support substrate, and the support substrate is good in heat conduction and L in order to improve heat dissipation of the LSI chip.
It is desirable to use an inorganic insulating substrate having a thermal expansion coefficient close to that of the SI chip. An unevenness may be provided on the back surface of the support substrate so that the support substrate is also used as a part of the cooling mechanism casing to directly cool the support substrate.

It is desirable that the insulating layer of the first substrate is formed of a coating film of an organic insulating layer such as polyimide so that the surface can be easily flattened. In addition, it is desirable that the insulating sheet of the wiring board be made of an organic insulating film such as polyimide, and that the shape of the through hole be tapered in a funnel shape in order to facilitate electrical connection by plating.

The second object is to arrange a plurality of LSI chips on a supporting substrate with the surface on which the electrode pads are formed facing upward without any gaps, and to fix the back surface to the supporting substrate at the time of each chip. A step of arranging the upper surfaces to be flush with each other and fixing the LSI chip group, and forming an insulating layer on the surface of the LSI chip group, and then forming a through hole in the insulating layer corresponding to the position on the electrode pad. Forming a wiring layer for electrically connecting electrode pads in the same chip or between adjacent chips through the through hole to prepare a first substrate, and an insulating sheet, A through hole is formed at a position corresponding to the wiring layer on the first substrate, and a wiring pattern including the through hole as one of wiring circuits is formed on an insulating sheet to form a wiring board. Forming the wiring board, fixing the wiring board to the first board with an adhesive, and stacking the wiring board, plating the stacked wiring board, and wiring the first board through the through holes. It is achieved by a method for manufacturing a large-scale wiring board, which comprises a step of electrically connecting a layer and a wiring pattern on the wiring board.

Depending on the circuit scale of the large-scale wiring board, the above steps to the steps are repeated a plurality of times to form a multilayer circuit board by laminating a plurality of wiring boards on the first board. desirable. A further preferable step is to add a step of removing unnecessary adhesive remaining on the wiring layer at the bottom of the through hole after the above-mentioned stacking step, thereby ensuring the reliability of electrical connection. can do.

As a preferable example of forming the wiring layer in the step of preparing the first substrate, Cr / Cu / Cr are sequentially formed into a three-layer film in the film forming step, or
Alternatively, a three-layer film of Ti / Cu / Cr is formed, and after the above-mentioned lamination step, a step of removing Cr of the outermost layer of the wiring layer appearing at the bottom of the through hole by etching to expose the underlying Cu layer is added. It is preferable that the plating treatment of No. 2 is a Cu or Ni plating treatment step. The first layer of Cr is formed as an underlayer of Cu,
The Cr of the layer is formed as an anti-oxidation film of Cu.

As a preferable example, the insulating layer as described above is formed by applying and curing a polyimide precursor to form an insulating layer having a flat surface,
It is desirable to form the insulating sheet of polyimide with a polyimide film.

[0019]

By adhering LSI chips of uniform thickness to each other with no gaps and fixing them to a support substrate, it is possible to reduce the step difference between chips on the surface of a group of LSI chips to 20 μm or less. This step difference can be reduced by forming an organic insulating layer or an inorganic insulating film formed by a coating / curing process on a group of LSI chips, and even when wiring cannot be completely flattened, wiring can be formed between chips. It is possible to form a step having a size that does not cause a defect such as disconnection.

When a material having a high thermal conductivity is used as the supporting substrate used for fixing the chip group, a cooling plate or a cooling mechanism for dissipating the heat generated from the LSI chip as it is after the multilayer wiring board is completed is used. It can be used as a part. The supporting substrate is made of a single metal, alloy, ceramics or the like, but one having a thermal expansion coefficient close to that of the LSI chip is preferable. For example, a single metal such as Zr or W or an alloy having a small thermal expansion coefficient known as an Invar alloy is used. Used.

Further, on a substrate having wirings connected in advance to the electrode pads on the LSI chip group via an insulating layer,
When stacking wiring boards with through holes in multiple layers, a film substrate having a through hole in which a part of the multilayer wiring such as the wiring inside the LSI chip or the wiring between adjacent LSI chips is already formed separately is manufactured. Then, the wiring on the board and the through hole of the wiring board are aligned with each other, and the both boards are bonded and fixed with an adhesive, and the through hole is filled by plating each time one layer of the wiring board is laminated. The lower layer wiring is electrically connected. This process is repeated multiple times according to the number of layers. This allows
It is possible to inspect the wiring defects of the individual wiring boards to be stacked in advance, select only the good wiring layers and stack them, and it is possible to prevent a reduction in the manufacturing yield of the wiring boards. Also, by forming an electrical connection by plating,
Since it can be laminated on the substrate at a relatively low temperature, various problems due to thermal stress can be prevented when the wiring layers are laminated in multiple layers.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. <Embodiment 1> FIGS. 1 and 2 are process drawings showing an example of a basic manufacturing method for manufacturing a large-scale wiring board of the present invention.
First, as shown in FIG. 1A, a single metal such as Zr or W having a thermal expansion coefficient close to that of the LSI chip 1 or an alloy having a small thermal expansion coefficient known as an inver alloy is used as the support plate 2
As one side, a large number of the side with the electrode pads 3 of the LSI chip 1 are arranged without any gaps on this one side, and the back side is supported by a metal bonding material such as an adhesive or solder. Stick to 2. When fixing, individual LSI
LS a smooth plate so that the surface of chip 1 is as flat as possible.
It is advisable to take measures such as pressing against the surface of the I-chip 1. Further, for the purpose of eliminating the gaps between the LSI chips as much as possible, the front surface side of the LSI chips may be temporarily fixed to this smooth plate in advance and then the back surface of the LSI chip may be pressed and fixed to the support plate.

Next, as shown in FIG. 1B, a polyimide precursor is applied and cured as an insulating layer 4 on the entire surface of the LSI chip 1 to flatten the surface. If the level difference between the LSI chips is 20 μm or less, the level difference can be reduced to such an extent that the wiring formation is not hindered by repeating the coating / curing process a plurality of times. A through hole 4a for taking out the electrode pad 3 is formed on a predetermined portion of the formed polyimide insulating layer 4 by a photo etching technique.

As shown in FIG. 1C, a three-layer film is formed on the insulating layer 4 in the order of Cr / Cu / Cr or Ti / Cu / Cr by using a film forming method such as sputtering or vapor deposition. The wiring layer 5 is continuously formed. Thereafter, the wiring layer 5 is sequentially processed by a photoetching technique using a predetermined mask pattern to form the wiring pattern 5. By this step, electrical connection between the connection pad 3 on the surface of the LSI chip 1 and the wiring 5 on the surface of the insulating layer 4 is formed through the through hole 4a. It is desirable that the polyimide layer as the insulating layer 4 formed here has a coefficient of thermal expansion equal to that of the LSI chip in terms of reliability of the wiring board and manufacturing. The substrate formed in this manner is referred to as a first substrate and is indicated by reference numeral 30.

When the LSI chip 1 becomes extremely high in density and the electrode pad 3 becomes minute accordingly, the insulating layer 4
The through hole 4a also becomes minute and the electrical connection with the electrode pad 3 may be incomplete only by the film forming process by sputtering or vapor deposition. Therefore, in such a case, it is desirable to add a plating step after the formation of the wiring layer 5 to ensure the conduction in order to improve the reliability of the connection.

Next, as shown in FIGS. 2 (a) to 2 (c),
Separated from the first substrate 30, a wiring substrate 4 serving as a second substrate
Form 0. First, as shown in FIG. 3A, a polyimide film is prepared as the insulating film 7, and the through-hole 7a is formed at this predetermined position by the laser ablation technique or the photo-etching technique. The expansion coefficient of the polyimide film used here is preferably the same as that of the LSI chip 1.

Next, as shown in FIG. 3B, a wiring metal layer 8 is formed on the film 7 by sputtering or vapor deposition. Cr / Cu / Cr as the wiring metal layer 8
Alternatively, three wiring layers of Ti / Cu / Cr are sequentially and continuously formed. Next, as shown in FIG. 3C, the wiring metal layer 8 is patterned by using a photoetching technique to form a single-layer wiring board 40 having a through hole 7a.
To form.

Next, as shown in FIG. 3D, the wiring substrate 40 formed in the previous step (c) is mounted on the first substrate 30 formed in FIG. Both are joined and fixed using. At the time of this bonding, the wiring board 40
After applying the adhesive 6 to the back surface of the wiring board 40, the polyimide film of the wiring board 40 and the board 30 are positioned so that the through holes 7a overlap the predetermined wiring layer 5 on the first board 30. To glue. Room temperature to 200 ° C for the adhesive 6
It is desirable that it solidifies at the following temperatures and does not generate water and gas during the reaction. Further, in bonding, it is better to expel the excess adhesive 6 by using a roll or the like before the adhesive is solidified so that the excess adhesive between the substrate 30 and the polyimide film 40 is reduced. Good results are obtained in the process of forming the physical connection.

The unnecessary adhesive 6 remaining on the bottom of the through-hole 7a at the point where the bonding is completed is removed by a solvent or O ₂ ashing treatment, and then the slurry is prepared for the plating treatment in the next step (e). -The Cr layer on the outermost surface of the wiring layer 5 exposed at the bottom of the hole 7a is removed by etching to remove the underlying Cu layer.
Expose the layer surface. Note that the removal of this Cr layer is performed by
It can also be performed at the end of step (c). That is, the substrate 30 with which the through hole 7a of the wiring substrate 40 comes into contact in advance
The uppermost Cr layer of the upper wiring layer 5 is removed by photoetching using a predetermined mask pattern to expose the underlying Cu layer.

Finally, as shown in FIG. 6 (e), a plating process is performed to form a metal film 9 of Ni, Cu or the like on the through hole 7a.
On the bottom and sides. The plating layer 9 establishes electrical continuity between the wiring 5 of the first substrate 30 and the wiring 8 formed on the wiring substrate 40. In this way, the large-scale wiring board 50 that is the object of the present invention can be manufactured.

Since a basic manufacturing example is shown in this embodiment, one layer of the wiring substrate 40 is laminated on the substrate 30 in FIG. 2D, but in reality, a plurality of layers are repeated. A large-scale wiring structure is formed by stacking layers to form a multilayer structure.

<Embodiment 2> FIG. 3 shows the uppermost wiring layer 9a of the large-scale multilayer wiring board 50 (however, the wiring board 40 has a repetitive multilayer structure) manufactured by the process of Embodiment 1 and the outside. It is a principal part sectional view which showed the structural example for connector connection with the wiring of a circuit. 60 is a connector, 15
Is a socket for connector connection, pin 1 of connector 60
4 is inserted into the insertion port 16 of the socket 15 and the circuit of the large-scale multilayer wiring board 50 is connected to an external circuit (not shown).

The connector 60 is composed of a thick film wiring board (for example, a ceramic multilayer board), and the conductor 11 is embedded in a through-hole 62 provided at a predetermined position of the insulating board 61 as shown in the drawing, followed by firing, and the back surface. A pin 14 for connecting the connector is fixed to the pad 12 by a brazing material 13. The surface of the connector 60 is connected to the uppermost wiring layer 9a of the large-scale multilayer wiring board 50 by the solder 10 using the CCB connection technique. This enables electrical connection with an external circuit without significantly reducing the wiring density.
The coefficient of thermal expansion of the thick film wiring board forming the connector 60 is preferably the same as that of the LSI chip.

<Third Embodiment> FIG. 4 shows that the cooling structure housing 18 is provided on the back surface of the supporting plate 2 of the large-scale multilayer wiring board 50 formed in the first and second embodiments with the adhesive 21 having good thermal conductivity, or FIG. 2 is a schematic cross-sectional view of a main part of a large-scale wiring board that is configured to be able to efficiently dissipate heat generated from a group of LSI chips by connecting and arranging with a brazing material.

Also in FIG. 5, the large-scale multilayer wiring board 5 is also shown.
It is a principal part schematic sectional drawing which showed the modification which provided the cooling structure housing | casing 18 on the back surface of the support plate 2 of 0. In this example, the back surface of the support plate 2 is processed into an uneven shape, and this is also used as a part of the cooling structure housing 18, and the protruding outer peripheral portion 2a of the support plate 2 remains through the sealing material 22. The cooling structure is connected to the casing 18 to directly cool the support plate 2, and the cooling effect can be further improved as compared with the configuration of FIG.

In any of the cooling structure casings 18, the refrigerant 19 flows from the blowing nozzle 20 in the direction of the arrow and is circulated by exchanging heat with a heat radiating portion (not shown). As the coolant, for example, cooling water is practical, but is not limited to this, and other commonly used gaseous or liquid coolant is used.

<Embodiment 4> FIG. 6 shows the same LSI chip 1
FIG. 1 shows the large-scale multilayer wiring board 50 in which the electrode pads 3 therein can be connected to each other by the wiring layer 5 disposed on the insulating layer 4 as shown in FIG. The modification of FIG. 2 is shown. The manufacturing method is basically the same as that of the first embodiment. In the manufacturing process of FIGS. 1B to 1C, after forming a polyimide layer as the insulating layer 4 on the LSI chip group by coating and curing. As the wiring 5 formed on the insulating layer 4, the wiring 5 connecting the electrode pads 3 in one LSI chip 1 to each other is formed. After that, the substrate 30 is processed through the steps of forming FIGS.
The wiring board 40 was formed on the top.

By adopting such a wiring pattern, it is possible to avoid wirings over the step remaining between the adjacent LSI chips 1 in this layer, and therefore even if there is a step that cannot be covered by the polyimide layer 4. It is possible to prevent the defective shape of the wiring. In addition, since a part of the wiring in the LSI chip 1 is taken over by the wiring layer 5 and the long wiring in the LSI chip is performed by the multilayer wiring portion having a small wiring resistance, the propagation delay of the electric signal is reduced, resulting in As a result, since there is an advantage that the LSI can operate at high speed, it is possible to compensate for an increase in the propagation delay of electric signals due to the miniaturization of wiring due to the high integration of LSI in the future.

<Embodiment 5> This example describes an example of an inspection circuit for an LSI chip and a multilayer wiring layer provided on the LSI chip. The large-scale multilayer wiring board 50 shown in the first embodiment is an LSI because the wiring board 40 is laminated on the LSI chip 1 in a single layer or a plurality of layers to directly form a circuit.
The circuit inspection of the chip 1 is most preferably performed when the single LSI chip is completed, but in consideration of the case where this is difficult, a spare LSI chip is included in the LSI chip group shown in FIG. Or a preliminary circuit is provided in the LSI chip itself, and the surface of the insulating layer 4 formed by coating and curing, or the film-like wiring board 40.
A circuit for inspecting the circuit on the LSI chip and the circuit on the wiring board 40 is provided on the top. Further, by disconnecting the defective portion of the circuit from the circuit and providing a so-called redundant circuit for connecting the spare circuit to the circuit on the wiring board 40, the defect of the LSI chip 1 is remedied, and the large-scale wiring board 50 fails. Prevent from becoming.

[0040]

According to the present invention, since it is possible to arrange LSI chips without gaps and to form wiring between chips, it is possible to minimize the wiring length in a multilayer wiring board. The electrical signal delay in the wiring can be minimized. As a result, it is possible to greatly improve the function of a device such as an electronic calculator or an electronic exchanger that needs to propagate an electric signal at high speed, and it is possible to reduce the size of the device.

As a method of manufacturing a multilayer wiring board, a wiring board on which wiring is formed in advance is separately manufactured, and this wiring board is bonded to a first board on which an LSI is mounted without a gap, and wiring of the wiring board is performed. By forming the electrical connection between the lower layer and the lower layer wiring (wiring on the first substrate) by the plating process, a high temperature process of more than 250 ° C. is not required during the manufacturing process of the multilayer wiring part. become. This makes it possible to prevent the occurrence of wiring failure due to thermal stress, and also makes the choice of organic materials for forming the multi-layer wiring very wide, and it is possible to use an adhesive. Further, by adopting this step, it is possible to prevent deterioration of the manufacturing yield of the multilayer wiring board by inspecting the wiring in each layer in advance and using only good products for the multilayer wiring board. Further, by incorporating a redundant circuit in the wiring board, it is possible to prevent a decrease in manufacturing yield of the multilayer wiring board.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process of a large-scale wiring board according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the large-scale wiring board.

FIG. 3 is a sectional view showing a structure of a connection portion of the large-scale wiring board with an external circuit.

FIG. 4 is a sectional view showing a cooling mechanism of an LSI chip group of the large-scale wiring board.

FIG. 5 is a sectional view showing a different cooling mechanism of the LSI chip group of the large-scale wiring board.

FIG. 6 is a cross-sectional view showing interconnection between LSI chips and between chips in the same multilayer wiring board.

FIG. 7 is a sectional view showing the structure of a conventional resin-embedded wiring board.

[Explanation of symbols]

1 ... LSI chip, 2 ... Support substrate, 3 ...
LSI electrode pad, 4 ... Insulating layer, 4a ... Through hole, 5 ... Wiring layer, 6 ... Adhesive,
7 ... Insulating film (organic insulating film), 7a ... Through hole, 8 ... Wiring metal layer, 9 ... Plating layer, 9a ... Wiring metal layer + plating layer, 10 ... Connection solder, 11 ... Thick film conductor, 12 ... Connection pad, 13 ... Connection brazing material, 14 ... Connector connection pin, 15 ... Connector connection socket, 16 ... Pin insertion hole, 1
7 ... Multilayer wiring part, 18 ... Cooling mechanism housing, 19
... Cooling medium, 20 ... Refrigerant blowing nozzle, 21 ... Cooling mechanism adhesive, 22 ... Seal material, 23
... Chip embedding resin, 30 ... First substrate,
40 ... Wiring board, 50 ... Large-scale wiring board, 60
... Connector, 61 ... Insulating substrate, 62 ... Through hole.

Claims (12)

[Claims] 1. A plurality of LSI chips are arranged on a support substrate with the surface on which the electrode pads are formed facing upward, and the back surface of the LSI chip is arranged on an insulating layer on the surface of the LSI chip group fixed to the support substrate. A first layer formed by forming a wiring layer connected to the electrode pad through a through hole provided
Board, a wiring board in which a wiring pattern is formed on an insulating sheet in which through holes are formed in advance, and the wiring board is fixed and laminated on the first board with an adhesive, and the wiring board is inserted through the through holes of the wiring board. And a plated metal layer for electrically connecting the wiring layer of the first substrate and the wiring pattern on the wiring substrate. 2. The large-scale wiring board according to claim 1, wherein a plurality of the wiring boards are fixed and laminated on the first board. 3. The large-scale wiring board according to claim 1, wherein a connector with pins is connected to the uppermost wiring layer of the wiring board by a conductor to form a wiring board with a connector. 4. The large-scale wiring board according to claim 1, wherein a cooling mechanism housing is provided on the back surface of the support board. 5. The large-scale wiring board according to any one of claims 1 to 4, wherein the support board is composed of an inorganic insulating board having a good thermal conductivity and a thermal expansion coefficient close to that of an LSI chip. 6. The large-scale wiring board according to claim 1, wherein the insulating layer of the first substrate is composed of a coating film of an organic insulating layer. 7. The large-scale wiring board according to claim 1, wherein the insulating sheet of the wiring board is formed of an organic insulating film, and the through holes are tapered in a funnel shape. 8. A plurality of LSI chips are arrayed on a support substrate with the surface having the electrode pads facing upward, without any gaps, and when the back surface is fixed to the support substrate, the upper surfaces of the chips are flush with each other. The step of arranging and fixing the LSI chip group, and forming an insulating layer on the surface of the LSI chip group, and then forming a through hole in the insulating layer corresponding to the position on the electrode pad. A step of forming a wiring layer for electrically connecting electrode pads in the same chip or between adjacent chips through the step of preparing a first substrate, and preparing an insulating sheet; Forming a through hole at a position corresponding to the wiring layer and forming a wiring pattern including the through hole as one of wiring circuits on an insulating sheet to form a wiring board; A step of fixing and laminating the wiring board to the first board with an adhesive; a plating process is applied to the laminated wiring board; and a wiring layer of the first board and wiring on the wiring board through through holes. A method of manufacturing a large-scale wiring board, the method including the step of electrically connecting to a pattern. 9. A wiring layer of the first board and a wiring pattern on the wiring board are electrically connected to each other through a through hole by plating the wiring board of the step of forming the wiring board, the stacking step, and the wiring step. 9. The method for manufacturing a large-scale wiring board according to claim 8, further comprising the step of forming a multi-layer circuit board by stacking a plurality of wiring boards on the first board by repeating a plurality of steps up to the step of connecting to. 10. The method of manufacturing a large-scale wiring board according to claim 8, further comprising a step of removing unnecessary adhesive remaining on the wiring layer at the bottom of the through hole after the stacking step. 11. When forming a wiring layer in the step of preparing the first substrate, Cr is sequentially formed in a film forming step.
/ Cu / Cr to form a three-layer film, or Ti
/ Cu / Cr three-layer film, after the above-mentioned lamination step,
10. The step of removing the Cr of the outermost layer of the wiring layer appearing at the bottom of the through hole by etching to expose the underlying Cu layer is added, and the plating is performed as a Cu or Ni plating step. Manufacturing method of large-scale wiring board. 12. The insulating layer is formed by applying and curing a polyimide precursor to form an insulating layer whose surface is flattened, and forming the insulating sheet with a polyimide film. Alternatively, the method for manufacturing a large-scale wiring board according to Item 9.