JPH0629501A - Gate array manufacturing apparatus and manufacturing method - Google Patents

Abstract

(57) [Summary] [Object] With regard to a gate array manufacturing apparatus, it is an object of the present invention to eliminate errors in pattern creation, to reduce the time and effort required for creation, and to shorten the development period. [Structure] The calculation unit 9 includes a chip size, the number of basic cells,
Either one of the number of input / output cells or the number of pads is input, and based on the technology information of the technology information reading unit 6, the pattern information of each component of the pattern information reading unit 7, and the layout information of the layout information reading unit 8,
Calculate the number of other components or chip size. The pattern arranging unit 10 includes the technology information of the technology information reading unit 6, the pattern information of each component of the pattern information reading unit 7, the layout information of the layout information reading unit 8, the chip size, the number of basic cells, the number of input / output cells or the number of pads. Any one of the conditions and the calculation result of the calculation unit 9 are input, and various components such as the basic cell, the input / output cell, and the pad are arranged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array manufacturing apparatus and manufacturing method for forming a bulk pattern of a gate array.

Due to recent advances in LSI technology, even in a gate array in which a bulk is formed in advance, the type, size, etc. according to the use are required. or,
It is desired to be able to create an error-free bulk pattern in a short period of time.

[0003]

2. Description of the Related Art Conventionally, in developing a new type of gate array, a bulk pattern in which various parts such as a basic cell, an input / output cell, and a pad for an input / output signal of the gate array are arranged is manually created. .

[0004]

However, as the scale of today's LSIs increases, the number of parts mounted in bulk also increases. Therefore, there is a problem that it takes a lot of time and effort to manually create a bulk pattern, and mistakes easily occur.

Further, there has been a problem that the bulk structure created by the level of experience and knowledge of the operator varies. Furthermore, due to the increase in the number of parts mounted in the bulk, it has become difficult to manually set the wiring width or the number of power supply lines so that the power supply can meet the demand.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to eliminate the occurrence of mistakes in the formation of the bulk pattern of the gate array, and to significantly reduce the time and effort required for the production, thereby achieving a development period. The purpose is to be able to shorten the.

It is another object of the present invention to make it possible to supply a power supply that meets the demand by adjusting the wiring width or the number of power supply lines.

[0008]

In order to achieve the above object, the first aspect of the present invention is to arrange various components of a plurality of basic cells, a plurality of input / output cells, and a plurality of pads for input / output signals on a semiconductor chip. A gate array manufacturing apparatus configured to form a bulk of a gate array by performing the above, and a technology information storage unit that stores technology information of a grid pitch for each technology, a basic cell, an input / output cell, and a pad for each technology. Based on the pattern information storage unit that stores the pattern information of each component, the layout information storage unit that stores the layout information of the minimum guaranteed interval between each component in each technology series, and the technology conditions for creating the gate array. Technology information that reads the technology information corresponding to that technology from the technology information storage unit Reading unit and pattern information reading unit that reads pattern information of each part of the basic cell, I / O cell, and pad corresponding to the technology from the pattern information storage unit based on the technology condition for creating the gate array, and the gate array creation Layout information reading unit that reads the layout information corresponding to the series of the technology from the layout information storage unit based on the technology condition and the layout condition, and the gate array of the chip size, the number of basic cells, the number of input / output cells or the number of pads Enter any one of the creation conditions and enter the technology information from the technology information reading section.
Pattern information of each part from the pattern information reading unit,
And a calculation unit that calculates the number of other components or chip size of the gate array to be created based on the layout information from the layout information reading unit, technology information from the technology information reading unit, and each component from the pattern information reading unit. Input the pattern information, the layout information from the layout information reading unit, and any one of the gate array creation conditions such as the chip size, the number of basic cells, the number of input / output cells, or the number of pads, and calculate the calculation result of the calculation unit. A gate array manufacturing apparatus is configured by including a pattern arranging unit for arranging various components such as a basic cell, an input / output cell and a pad.

According to a second aspect of the invention, the technology information storage unit has a power supply bus line width for each technology, a power supply wire adjacency condition, a generated via condition, a power consumption per basic cell, and a power supply wire per unit width. It is assumed that the technology information of the supplied power is stored. The layout information storage unit stores the minimum guaranteed interval between the power bus and the basic cell for each series in each technology, the minimum guaranteed interval between the power bus and the input / output cells, and the power supply to the power bus. It is assumed that the layout information of the position where the power supply line can be generated is stored. Then, the technology information of the power supply bus width, the power supply wiring adjacency condition, and the generated via condition read from the technology information storage unit based on the technology condition, and the power supply bus line read from the layout information storage unit based on the technology condition. Based on the layout information of the minimum guaranteed interval between the power supply bus and the basic cell, and the minimum guaranteed interval between the power supply bus and the input / output cell, and the placement result of various parts by the pattern placement unit. An arrangement unit, power consumption per basic cell read from the technology information storage unit based on technology conditions, and power supply per unit width of power supply wiring;
Number of power supply lines or wiring width condition as creation condition,
Based on the number of basic cells as the creation condition or the number of basic cells calculated by the calculation unit, the power supply line calculation unit that calculates the wiring width or the number of power supply lines, and the placement result of various components by the pattern placement unit, Power supply for arranging the power supply lines calculated by the power supply line calculation unit based on the result of the power supply bus bar arrangement by the power supply bus arrangement unit and the adjacency condition of the power supply lines read from the technology information storage unit according to the technology condition. A gate array manufacturing apparatus was configured with a line arrangement section.

According to a third aspect of the present invention, a bulk of a gate array is formed by arranging various components of a plurality of basic cells, a plurality of input / output cells, and a plurality of pads for input / output signals on a semiconductor chip. The method for manufacturing a gate array according to claim 1, wherein the technology information storage unit stores in advance the technology information of the grid pitch for each technology, and the pattern information that stores the pattern information for each part of the basic cell, the input / output cell, and the pad for each technology. A storage unit and a layout information storage unit that stores layout information of the minimum guaranteed interval between parts of each series in each technology are prepared.

Then, a grid of the technology conditions inputted according to any one of the technology conditions of the gate array inputted from the outside, the layout conditions, and the chip size, the number of basic cells, the number of input / output cells or the number of pads. Pitch technology information is read from the technology information storage unit, circuit pattern information is read from the pattern information storage unit according to any one of the input chip size, basic cell, input / output cell, or pad,
A step of reading layout information of the minimum guaranteed interval between the respective parts from the layout information storage section according to the input layout condition, the technology information read from the technology information storage section, the pattern information read from the pattern information storage section, and the layout A step of calculating the chip size or the number of parts based on the layout information read from the information storage unit and any one of the chip size, the number of basic cells, the number of input / output cells or the number of pads, and the process of reading the layout information storage unit A gate array manufacturing method is configured including a step of arranging a basic cell, an input / output cell or a pad on a chip with a minimum guarantee interval.

Further, in the fourth aspect of the invention, the technology information storage unit has a power supply bus line width for each technology, a power supply line adjacency condition, a generated via condition, a power consumption per basic cell, and a power supply line per unit width. The power supply technology information is stored, and the layout information storage unit stores the minimum guaranteed interval between the power supply bus bar and the basic cell for each series in each technology, the minimum guaranteed interval between the power supply bus line and the input / output cells, and the power supply. The layout information of the position where a power supply line for supplying power to the bus bar can be generated is stored.

Then, the technology information such as the wiring width of the power supply bus, the adjacency condition of the power supply wiring, and the generated via condition is read from the technology information storage unit based on the technology condition, and the technology information between the power supply bus and the basic cell is read based on the technology condition. The process of reading the layout information of the minimum guaranteed interval and the minimum guaranteed interval between the power supply bus and the input / output cells from the layout information storage unit, arranging the power supply bus around the basic cell area, and the technology information based on the technology conditions. Based on the power consumption per basic cell read from the storage unit and the power supply per unit width of the power supply wiring, the number of power supply lines or the wiring width condition as the creating condition, and the number of basic cells, the power supply line Calculating the wiring width or the number of wires, and arranging the power supply line so as to be connected to the power bus. In to constitute a gate array manufacturing method.

[0014]

According to the first and third aspects of the present invention, any one of the conditions for creating the gate array such as the chip size, the number of basic cells, the number of input / output cells or the number of pads, and the technology information from the technology information reading section, Based on the pattern information of each component from the pattern information reading unit and the layout information from the layout information reading unit, the number of other components or the chip size of the gate array to be created is calculated.

The technology information from the technology information reading unit, the pattern information of each part from the pattern information reading unit, the layout information from the layout information reading unit, the chip size, the number of basic cells,
Various parts such as a basic cell, an input / output cell, and a pad are arranged based on any one of the conditions for creating the gate array of the number of input / output cells or the number of pads and the number of parts or the chip size.

Therefore, an error does not occur in the formation of the bulk pattern of the gate array, and the labor required for the formation is greatly reduced, and the development period is shortened. or,
According to the second and fourth inventions, the technology information of the wiring width of the power bus, the power wiring adjacency condition, and the generated via condition read from the technology information storage unit and the layout information storage unit based on the technology condition are read. Layout information of the minimum guaranteed interval between the issued power bus and the basic cell, and the minimum guaranteed interval between the power bus and the input / output cell,
A power bus that surrounds the basic cell region is arranged based on the arrangement result of various components. In addition, based on the power consumption per basic cell read from the technology information storage unit and the power supply per unit width of the power supply wiring, the number of power supply lines or wiring width conditions as creation conditions, and the number of basic cells. Thus, the wiring width or the number of power supply lines is calculated.

Then, based on the placement result of various components, the placement result of the power supply bus by the power supply bus placement unit, and the adjacency condition of the power supply wiring read from the technology information storage unit,
The power supply line is arranged so as to be connected to the power bus.

Therefore, the wiring width or the number of power supply lines is
It will be possible to supply power that meets demand.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a gate array manufacturing apparatus embodying the present invention will be described below with reference to the drawings.

FIG. 3 shows the bulk structure of the gate array 30 produced in this embodiment. An internal cell region 32 is formed in the center of the semiconductor chip 31, and a large number of internal basic cells 32a are laid out in the region 32. An annular power supply bus 33 is laid out around the internal cell region 32 with a minimum guarantee interval G1 between the internal cell region 32 and the internal region 32. In addition, a large number of input / output cells 35 are laid out around the internal cell region 32 with a minimum guaranteed interval G2 between them. Predetermined input / output cell 35
From the above, a plurality of power supply lines 34 for supplying power to the power bus 33 are laid out.

Around the input / output cells 35, pads 36 for input / output signals corresponding to the input / output cells 35 on a one-to-one basis.
Is laid out. Pad 36 and input / output cell 35
A minimum guarantee interval G3 is provided between the and. Further, a minimum guarantee interval G4 is provided between the input / output cell 35 and the outer peripheral edge of the semiconductor chip 31. Further, corner portions 37a to 37d are laid out at the four corner portions of the semiconductor chip 31. A test pattern for determining whether or not there is a pattern shift of the gate array 30 is formed on each of the corner portions 37a to 37d.

FIG. 1 shows a gate array manufacturing apparatus 1 for forming a bulk pattern of the gate array 30. The gate array manufacturing apparatus 1 includes a technology library 2 as a technology information storage unit, a pattern library 3 as a pattern information storage unit, a layout library 4 as a layout information storage unit, a creation condition setting unit 5, a technology information reading unit 6, and a pattern. The information reading unit 7, the layout information reading unit 8, the calculating unit 9, the pattern arranging unit 10, the power supply busbar arranging unit 11, the power supply line calculating unit 12, the power supply line arranging unit 13, and the like are configured.

Then, the gate array manufacturing apparatus 1 is configured to form a bulk of the gate array by arranging various parts based on the technology condition and the layout condition as the condition for forming the gate array. Various parts include a plurality of internal basic cells, a plurality of input / output cells, a plurality of pads for input / output signals, and the like.

In this embodiment, the difference in technology is defined by the difference in process (for example, bipolar technology and MOS technology), the type of minimum wiring width, and the like. The technology library 2 stores technology information such as the grid pitch for each technology, the wiring width of the power supply bus 33, the adjacency condition of the power supply wiring, and the generated via condition. The technology library 2 also stores technology information such as the power consumption per internal basic cell 32a and the power supply per unit width of the power supply wiring.

The pattern library 3 stores pattern information of each component such as the internal basic cell 32a, the input / output cell 35, the pad 36 and the corner portions 37a to 37d for each technology.

The layout library 4 stores the minimum guaranteed intervals between the same parts such as the internal basic cells 32a, the input / output cells 35, and the pads 36 for each series in each technology. Layout library 4
The minimum guaranteed interval G2 between the input / output cell 35 and the internal cell region 32 and the minimum guaranteed interval G3 between the input / output cell 35 and the pad 36 are stored in the table. Further, the layout library 4 includes an input / output cell 35 and corner portions 37a to 37d.
, And the minimum guaranteed interval between different parts such as between the pad 36 and the internal cell region 32 are stored.

The layout library 4 also stores a minimum guaranteed interval G1 between the power supply bus 33 and the internal cell region 32 and a minimum guaranteed interval G4 between the input / output cells 35 and the outer peripheral edge of the semiconductor chip 31. Further, the layout library 4 stores layout information such as a position where a power supply line 34 for supplying power to the power bus 33 can be generated.

In the creation condition setting section 5, technology conditions and layout conditions for creating a gate array are set from the outside. Further, one of the chip size of the gate array to be created, the number of internal basic cells 32a, the number of input / output cells 35, or the number of pads 36 is set in the creating condition setting unit 5. Further, the number of power supply lines 34 or the wiring width is set in the creation condition setting unit 5.

Based on the technology conditions set in the creation condition setting unit 5, the technology information reading unit 6 uses the technology library 2 to select the grid pitch corresponding to the technology, the wiring width of the power supply bus 33, the adjacent condition of the power supply wiring, and the generated via condition. , Technology information such as power consumption per internal basic cell 32a and power supply per unit width of power supply wiring is read.

Based on the technology condition set in the creation condition setting unit 5, the pattern information reading unit 7 uses the pattern library 3 for each component such as the internal basic cell 32a, the input / output cell 35, and the pad 36 corresponding to the technology and the corner. The pattern information of the parts 37a to 37d is read.

Based on the technology condition and layout condition set in the creation condition setting unit 5, the layout information reading unit 8 determines from the layout library 4 the minimum guaranteed interval between the same components corresponding to the series of the technology and the minimum guarantee interval between different components. Layout information such as a guaranteed interval, a minimum guaranteed interval between the power bus and the internal cell region, and a position where a power supply line for supplying power to the power bus can be generated is read.

The calculation unit 9 inputs any one of the creation conditions set in the creation condition setting unit 5 among the creation conditions such as the chip size, the number of internal basic cells, the number of input / output cells, and the number of pads. The calculation unit 9 inputs the technology information read by the technology information reading unit 6. Further, the calculation unit 9 inputs the pattern information of each component read by the pattern information reading unit 7 and the layout information read by the layout information reading unit 8.

Then, the calculating unit 9 calculates the number of other components or the chip size of the gate array to be created based on the creating conditions and the above-mentioned information. For example, in the gate array 30 shown in FIG. 3, when the chip size is set as the creation condition, the size of the area where a large number of input / output cells 35 can be arranged is required. That is, the input / output cell 35 and the semiconductor chip 3 in the layout information from the chip size
The size of the area in which the input / output cells 35 can be arranged is obtained by subtracting the minimum guaranteed distance G4 from the outer peripheral edge.
The number of arranged input / output cells 35 is calculated based on the size of the area in which the input / output cells 35 can be arranged, the size of the input / output cells 35 in the pattern information, and the minimum guaranteed interval between the input / output cells 35 in the layout information. .

Next, based on the size of the area in which the input / output cells 35 can be arranged and the minimum guaranteed spacing G3 between the input / output cells 35 and the pads 36 in the layout information, a large number of pads 36 can be arranged in the area. Is required. The number of pads 36 to be arranged is calculated based on the size of the area in which the pads 36 can be arranged, the size of the pads 36 in the pattern information, and the minimum guaranteed interval between the pads 36 in the layout information.

Then, the size of the internal cell area 32 is determined based on the size of the area in which the input / output cell 35 can be arranged and the minimum guaranteed interval G2 between the input / output cell 35 and the internal cell area 32 in the layout information. Desired. The number of arranged internal basic cells is calculated based on the size of the internal cell region 32, the size of the internal basic cells 32a in the pattern information, and the minimum guaranteed interval between the internal basic cells 32a in the layout information.

Further, in the gate array 30, when the number of internal basic cells is set as a production condition, the size of the internal cell region 32 is obtained. That is, the size of the internal cell region 32 is obtained based on the number of internal basic cells 32a, the size of the internal basic cells 32a in the pattern information, and the minimum guaranteed interval between the internal basic cells 32a in the layout information. Based on the size of the internal cell area 32 and the minimum guaranteed interval G2 between the input / output cell 35 and the internal cell area 32 in the layout information, the size of the area in which a large number of input / output cells 35 can be arranged is obtained. . The size of the area in which the input / output cell 35 can be arranged, the size of the input / output cell 35 in the pattern information, and the input / output cell 3 in the layout information.
The number of arranged input / output cells 35 is calculated based on the minimum guaranteed interval between 5 and 5.

Next, the size of the area in which the pad 36 can be arranged is determined based on the size of the area in which the input / output cell 35 can be arranged and the minimum guaranteed interval G3 between the input / output cell 35 and the pad 36 in the layout information. Is required. The number of pads 36 to be arranged is calculated based on the size of the area in which the pads 36 can be arranged, the size of the pads 36 in the pattern information, and the minimum guaranteed interval between the pads 36 in the layout information.

Then, the chip size of the semiconductor chip 31 is determined based on the size of the area in which the input / output cell 35 can be arranged and the minimum guaranteed interval G4 between the input / output cell 35 and the outer peripheral edge of the semiconductor chip 31 in the layout information. Desired.

In addition, in the gate array 30, when the number of input / output cells is set as a production condition, the size of the area where a large number of input / output cells 35 can be arranged is obtained. That is, the size of the area in which the input / output cells 35 can be arranged is determined based on the number of input / output cells 35, the size of the input / output cells 35 in the pattern information, and the minimum guaranteed interval between the input / output cells 35 in the layout information. The size of the internal cell area 32 is obtained based on the size of the area in which the input / output cell 35 can be arranged and the minimum guaranteed interval G2 between the input / output cell 35 and the internal cell area 32 in the layout information. The number of arranged internal basic cells 32a is calculated based on the size of the internal cell region 32, the size of the internal basic cells 32a in the pattern information, and the minimum guaranteed interval between the internal basic cells 32a in the layout information.

Next, the size of the area in which the pad 36 can be arranged is based on the size of the area in which the input / output cell 35 can be arranged and the minimum guaranteed interval G3 between the input / output cell 35 and the pad 36 in the layout information. Is required. The number of pads 36 to be arranged is calculated based on the size of the area in which the pads 36 can be arranged, the size of the pads 36 in the pattern information, and the minimum guaranteed interval between the pads 36 in the layout information.

Then, the chip size of the semiconductor chip 31 is determined based on the size of the area where the input / output cells 35 can be arranged and the minimum guaranteed interval G4 between the input / output cells 35 and the outer peripheral edge of the semiconductor chip 31 in the layout information. Desired.

Further, in the gate array 30, when the number of pads is set as a preparation condition, the size of the area where a large number of pads 36 can be arranged is obtained. That is, the number of pads 36 and the pad 3 in the pattern information
The size of the area in which the pads 36 can be arranged is calculated based on the size of 6 and the minimum guaranteed interval between the pads 36 in the layout information. The size of the area in which the pads 36 can be arranged and the size of the area in which a large number of the input / output cells 35 can be arranged are obtained based on the minimum guaranteed interval G3 between the input / output cells 35 and the pads 36 in the layout information. To be The number of arranged input / output cells 35 is calculated based on the size of the area in which the input / output cells 35 can be arranged, the size of the input / output cells 35 in the pattern information, and the minimum guaranteed interval between the input / output cells 35 in the layout information. .

Next, the size of the internal cell area 32 is determined based on the size of the area in which the input / output cell 35 can be arranged and the minimum guaranteed interval G2 between the input / output cell 35 and the internal cell area 32 in the layout information. Is required. The number of arranged internal basic cells 32a is calculated based on the size of the internal cell region 32, the size of the internal basic cells 32a in the pattern information, and the minimum guaranteed interval between the internal basic cells 32a in the layout information.

Then, the chip size of the semiconductor chip 31 is determined based on the size of the area in which the input / output cell 35 can be arranged and the minimum guaranteed interval G4 between the input / output cell 35 and the outer peripheral edge of the semiconductor chip 31 in the layout information. Desired.

The pattern placement unit 10 inputs the technology information read by the technology information reading unit 6 and the pattern information of each component read by the pattern information reading unit 7. In addition, the pattern placement unit 10 inputs the layout information read by the layout information reading unit 8, the creation condition set in the creation condition setting unit 5, and the number or chip size of each component calculated by the calculation unit 9. .

Then, the pattern arranging section 10 determines the size of the gate array to be formed, and the internal basic cell 32
Various components such as a, the input / output cell 35, and the pad 36 are arranged.

The power supply busbar arranging unit 11 has a wiring width of the power supply busbar 33 read by the technology information reading unit 6,
Enter technology information such as power supply wiring adjacency conditions and generated via conditions. The power supply busbar arrangement unit 11 inputs layout information such as the minimum guaranteed interval between the power supply busbar 33 and the internal cell region 32 read by the layout information reading unit 8. Further, the power supply busbar arrangement unit 11 inputs the arrangement result of various parts by the pattern arrangement unit 10.

Then, the power supply busbar arrangement unit 11 arranges the power supply busbars based on the input technology information, layout information, and the arrangement result of various parts. Power supply line calculation unit 1
2 is technology information such as the power consumption per internal basic cell read by the technology information reading unit 6 and the power supply per unit width of the power supply wiring, the number of power supply lines set in the creation condition setting unit 5, or Enter the wiring width condition. Further, the power supply line calculation unit 12 inputs the number of internal basic cells as the creation condition set in the creation condition setting unit 5 or the number of internal basic cells calculated by the calculation unit 9.

Then, when the number of power supply lines is set in the creation condition setting unit 5, the power supply line calculation unit 12 sets the wiring width of the power supply lines that can supply power to meet the demand as follows. It is calculated according to equations (1) to (3).

That is, the power consumption per internal basic cell is K1, the number of internal basic cells is Cn, and the total power consumption of the internal basic cells is Cp. The power supply per unit width of the power supply wiring is K2, the power supply of each power supply line is P, the number of power supply lines is N, and the width of each power supply line is W. Then,

[0051]

[Equation 1]

It becomes Here, since the number N of power supply lines is known, the supply power P of each power supply line is

[0053]

[Equation 2]

It becomes Therefore, the width W of each power supply line is

[0055]

[Equation 3]

It is calculated by Also, the power supply line calculation unit 12
When the wiring width of the power supply line is set in the creation condition setting unit 5, calculates the number of power supply lines that can supply the power according to the demand according to the following equations (4) to (6). .

That is, the power consumption per internal basic cell is K1, the number of internal basic cells is Cn, and the total power consumption of the internal basic cells is Cp. The power supply per unit width of the power supply wiring is K2, the power supply of each power supply line is P, the number of power supply lines is N, and the width of each power supply line is W. Then,

[0058]

[Equation 4]

It becomes Here, since the width W of each power supply line is known, the supply power P of each power supply line is

[0060]

[Equation 5]

It becomes Therefore, the number N of power supply lines is

[0062]

[Equation 6]

It is calculated by The power supply line arranging unit 13 inputs the technology information such as the adjacency condition of the power supply wiring read by the technology information reading unit 6 and the generated via condition, and the position information capable of generating the power supply line read by the layout information reading unit 8. To do. Further, the power supply line placement unit 13 inputs the placement result of various parts by the pattern placement unit 10 and the number or wiring width of the power supply lines calculated by the power supply line calculation unit 12.

Then, the power supply line arranging unit 13 arranges the power supply lines having the wiring width calculated by the power supply line calculating unit 12 or the calculated number of power supply lines based on the above information.

FIG. 2 shows a gate array forming process of the gate array manufacturing apparatus 1 configured as described above. Prior to the gate array creation processing, the technology conditions and layout conditions of the gate array created externally are input to the creation condition setting unit 5. Further, any one of the chip size, the number of internal basic cells, the number of input / output cells, or the number of pads is set in the creation condition setting unit 5, and the number of power supply lines or the wiring width is set.

First, in step 21, from the technology library 2, the grid pitch corresponding to the technology, the wiring width of the power supply bus 33, the power supply wiring adjacency condition, the generated via condition, the power consumption per internal basic cell 32a, and the power supply. Technology information such as power supply per unit width of wiring is read.

In step 22, from the pattern library 3, the internal basic cell 32a corresponding to the technology,
The pattern information of each component such as the input / output cell 35 and the pad 36 and the corner portions 37a to 37d is read.

In the next step 23, the minimum guaranteed interval between the same parts corresponding to the series of the technology, the minimum guaranteed interval between different parts, the minimum guaranteed interval between the power bus and the internal cell area, and Layout information such as a position where a power supply line for supplying power to the power bus can be generated is read.

In step 24, any one of the creating conditions such as the chip size, the number of internal basic cells, the number of input / output cells or the number of pads, and the above steps 21 to 2
The number of other components or chip size of the gate array to be created is calculated based on the technology information, pattern information, and layout information read in 3.

In the following step 25, as shown in FIG. 3, each input / output cell 35 is arranged on the semiconductor chip 31 with the minimum guaranteed interval G4 between the outer peripheral edge of the chip 31 and each pad 36. And a minimum guarantee interval G3. Further, the internal cell region 32 is formed with the minimum guaranteed interval G2 between the internal cell region 32 and each input / output cell 35, and each internal basic cell 32a is arranged in the internal cell region 32. Further, the corner portions 37a to 37d are formed on the semiconductor chip 3
1 is placed on top.

Then, in the next step 26, the power supply bus 3
3 is arranged so as to surround the internal cell region 32 with the minimum guaranteed distance G1 from the internal cell region 32. Next, at step 27, technology information such as the power consumption per one of the internal basic cells 32a and the power supply per unit width of the power supply wiring, the number or wiring width of the power supply lines as the preparation condition, and the internal basic as the preparation condition. Based on the number of cells or the number of internal basic cells calculated in step 24, etc., the wiring width or the number of power supply lines 34 capable of supplying a power supply matching the demand is calculated.

Then, in step 28, the technology information such as the adjacency condition of the power supply wiring, the generated via condition, etc., the power supply line 34.
Based on the position information, the placement result of each component, the number of power supply lines or the width of the power supply lines as a creation condition, etc., the power supply lines 34 of the wiring width or the number calculated in step 27.
Are arranged to be connected to the power bus 33.

As described above, according to this embodiment, the technology condition and the layout condition, and any one of the chip size, the number of internal basic cells, the number of input / output cells, and the number of pads are set as the conditions for forming the gate array. I decided to do it. Then, the number of other components or the chip size of the gate array to be created is calculated by these, and each component such as the internal basic cell, the input / output cell and the pad is arranged.

Therefore, it is possible to prevent mistakes in the formation of the bulk pattern of the gate array, and
The time required for creation can be greatly reduced and the development period can be shortened.

Further, according to this embodiment, the number of power supply lines or the wiring width is additionally set as the condition for forming the gate array. Then, the wiring width or the number of power supply lines is calculated based on the number or wiring width of the power supply lines. Therefore, the wiring width or the number of power supply lines can be set to supply the power that meets the demand.

In this embodiment, the internal basic cell 32 is used.
a, the input / output cell 35 and the pad 36, and the formation of the gate array 30 including the power supply bus 33 and the power supply line 34 have been described, but when the gate array is formed, the internal basic cell 32a and the input / output cell 35 are formed. The pads and the pads 36 may be arranged, and the power bus 33 and the power supply line 34 may be created as needed.

[0077]

As described in detail above, according to the first and third aspects of the invention, it is possible to eliminate the occurrence of mistakes in the formation of the bulk pattern of the gate array and to greatly reduce the labor required for the development. The period can be shortened.

Further, according to the second and fourth inventions, the wiring width or the number of the power supply lines can be set so that the power supply which meets the demand can be supplied.

[Brief description of drawings]

FIG. 1 is a block diagram showing a gate array manufacturing apparatus according to an embodiment.

FIG. 2 is a flowchart showing a gate array creation process of one embodiment.

FIG. 3 is a layout diagram showing a bulk configuration of a gate array.

[Explanation of symbols]

1 Gate Array Manufacturing Equipment 2 Technology Library as Technology Information Storage Section 3 Pattern Library as Pattern Information Storage Section 4 Layout Library as Layout Information Storage Section 5 Creation Condition Setting Section 6 Technology Information Reading Section 7 Pattern Information Reading Section 8 Layout Information Reading unit 9 Calculation unit 10 Pattern placement unit 11 Power supply busbar placement unit 12 Power supply line calculation unit 13 Power supply line placement unit

Claims (4)

[Claims] 1. A gate array manufacturing method in which a bulk of a gate array is formed by arranging various parts of a plurality of basic cells, a plurality of input / output cells, and a plurality of pads for input / output signals on a semiconductor chip. The device is a technology information storage unit (2) that stores technology information of grid pitch for each technology, and a pattern information storage unit (2) that stores pattern information of each part of the basic cell, the input / output cell, and the pad for each technology. 3), a layout information storage unit (4) that stores layout information of the minimum guaranteed interval between parts of each series in each technology, and a technology information storage unit (2) based on technology conditions for creating a gate array. The technology information reading unit (6) that reads the technology information corresponding to the technology from the A pattern information reading section (7) for reading pattern information of each part of the basic cell, the input / output cell and the pad corresponding to the technology from the pattern information storage section (3) based on the technology condition for creating the array, and the gate array A layout information reading unit (8) that reads layout information corresponding to the series of the technology from the layout information storage unit (4) based on the technology conditions and layout conditions for creation, chip size, number of basic cells, and input / output cells Number, or the number of pads, which is one of the gate array creation conditions, is input, and the technology information is read from the technology information reading unit (6), the pattern information of each component is read from the pattern information reading unit (7), and the layout information is read. Based on the layout information from section (8) Calculation unit (9) for calculating the number of other components or the chip size of the formed gate array
Technology information from the technology information reading unit (6), pattern information of each part from the pattern information reading unit (7), layout information from the layout information reading unit (8), chip size, number of basic cells, and While inputting one of the conditions for creating the gate array for the number of output cells or the number of pads, the calculating unit (9)
And a pattern arranging section (10) for arranging various components such as a basic cell, an input / output cell and a pad by inputting the calculation result of the above. 2. The technology information storage unit (2) has a power supply bus line width for each technology, a power supply line adjacency condition, a generated via condition, power consumption per basic cell, and power supply line per unit width. The layout information storage unit (4) stores electric power technology information, and the layout information storage unit (4) has a minimum guaranteed interval between a power bus and a basic cell for each technology and a minimum guaranteed interval between a power bus and an input / output cell. , And the layout information of the position where a power supply line for supplying power to the power supply bus can be generated. Based on the technology condition, the technology information storage unit (2)
The minimum width between the power bus and the basic cell read from the layout information storage unit (4) based on the technology information of the power supply bus wiring width read from the power supply wiring adjacency condition and the generated via condition. A power supply busbar arranging unit (11) for arranging the power supply busbar based on the layout information of the guarantee space and the minimum guarantee space between the power supply busbar and the input / output cell and the layout result of various parts by the pattern layout unit (10). ) And the technology information storage unit (2) based on the technology condition.
Power consumption per basic cell read from the power supply and power supply per unit width of power supply wiring, number of power supply lines or wiring width condition as creation condition, number of basic cells as creation condition, or the calculation unit A power supply line calculation unit (12) for calculating the wiring width or the number of power supply lines based on the number of basic cells calculated in (9); and a placement result of various components by the pattern placement unit (10), Calculated by the power supply line calculation unit (12) based on the placement result of the power supply busses by the power supply busbar placement unit (11) and the adjacency condition of the power supply lines read from the technology information storage unit (2) according to the technology condition. The gate array manufacturing apparatus according to claim 1, further comprising a power supply line arranging unit (13) for arranging the arranged power supply lines. 3. A gate array manufacturing method in which a bulk of a gate array is formed by arranging various components of a plurality of basic cells, a plurality of input / output cells, and a plurality of pads for input / output signals on a semiconductor chip. The method includes a technology information storage unit (2) in which technology information of a grid pitch for each technology is stored in advance, and a pattern information storage unit in which pattern information of basic cells, input / output cells, and pads of each technology is stored. (3) and a layout information storage unit (4) that stores layout information of the minimum guaranteed interval between parts of each series in each technology are prepared, and the technology condition, layout condition of the gate array input from the outside, And chip size, number of basic cells,
Depending on either one of the number of input / output cells or the number of pads, the technology information of the grid pitch of the input technology condition is read from the technology information storage unit (2), and the input chip size, basic cell, input / output cell Alternatively, the pattern information of the circuit is read from the pattern information storage unit (3) according to one of the pads, and the layout information of the minimum guaranteed interval between the components is read out according to the input layout condition. 4) a step of reading from the technology information storage unit (2), the technology information read from the technology information storage unit (2), the pattern information read from the pattern information storage unit (3), and the layout information read from the layout information storage unit (4); Chip size based on size, number of basic cells, number of input / output cells or number of pads. Gate array manufacturing method, which includes a step of calculating a size or the number of components, and a step of arranging a basic cell, an input / output cell or a pad on a chip with a minimum guaranteed interval read from the layout information storage section (4). . 4. The technology information storage unit (2) has a power supply bus line width for each technology, a power supply line adjacency condition, a generated via condition, a power consumption per basic cell, and a power supply line per unit width. The layout information storage unit (4) stores electric power technology information, and the layout information storage unit (4) has a minimum guaranteed interval between a power bus and a basic cell for each technology and a minimum guaranteed interval between a power bus and an input / output cell. , And the layout information of the position where the power supply line for supplying power to the power bus can be generated. Based on the technology conditions, the wiring width of the power bus, the adjacency condition of the power lines, and the generated via condition are stored. The technology information is read from the technology information storage unit (2), and the minimum guaranteed interval between the power bus and the basic cell and the power are read based on the technology conditions. The layout information of the minimum guaranteed interval between the bus bar and the input / output cell is read from the layout information storage unit (4), the power supply bus bar is arranged so as to surround the basic cell region, and the technology information storage unit ( 2)
Wiring of power supply lines based on the power consumption per basic cell and the power supply per unit width of power supply wiring read from the device, the number of power supply lines or wiring width conditions as creation conditions, and the number of basic cells 4. The method of manufacturing a gate array according to claim 3, further comprising the step of calculating a width or the number of lines and arranging a power supply line so as to be connected to the power bus.