JPH06308531A - Liquid crystal display - Google Patents
Liquid crystal displayInfo
- Publication number
- JPH06308531A JPH06308531A JP9806993A JP9806993A JPH06308531A JP H06308531 A JPH06308531 A JP H06308531A JP 9806993 A JP9806993 A JP 9806993A JP 9806993 A JP9806993 A JP 9806993A JP H06308531 A JPH06308531 A JP H06308531A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- liquid crystal
- capacitance
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 28
- 239000010408 film Substances 0.000 claims description 108
- 239000000758 substrate Substances 0.000 claims description 16
- 239000011159 matrix material Substances 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 abstract description 19
- 239000000463 material Substances 0.000 abstract description 6
- 206010047571 Visual impairment Diseases 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、アクティブマトリック
ス基板を有する液晶表示装置の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a liquid crystal display device having an active matrix substrate.
【０００２】[0002]
【従来の技術】図２は従来のアクティブマトリックス液
晶パネルの平面図（ａ）とそのＡ−Ａ′断面図（ｂ）で
ある。図２内の記号の説明をすると、２０１は絶縁性ガ
ラス基板、２０２はソース線、２０３はゲート線、２０
４はゲート電極、２０５はソース領域、２０６はドレイ
ン領域、２０７はチャンネル領域、２０８は画素電極、
２０９は層間絶縁膜、２１０は絶縁膜、２１１，２１６
は配向膜、２１２は液晶、２１３は対向基板、２１４は
ブラックマトリックス遮光膜、２１５は対向電極となる
透明導電膜である。2. Description of the Related Art FIG. 2 is a plan view (a) of a conventional active matrix liquid crystal panel and a sectional view (b) taken along the line AA '. Referring to the symbols in FIG. 2, 201 is an insulating glass substrate, 202 is a source line, 203 is a gate line, 20
4 is a gate electrode, 205 is a source region, 206 is a drain region, 207 is a channel region, 208 is a pixel electrode,
209 is an interlayer insulating film, 210 is an insulating film, and 211, 216.
Is an alignment film, 212 is a liquid crystal, 213 is a counter substrate, 214 is a black matrix light-shielding film, and 215 is a transparent conductive film serving as a counter electrode.
【０００３】概略のプロセスを説明すると、以下の如く
である。透明絶縁基板（例えば石英ガラス板）、多結晶
シリコン薄膜を堆積しパターニング後ゲート絶縁膜と、
高濃度リンドープした多結晶シリコン薄膜を堆積しパタ
ーニングして、ゲート線及びゲート電極を形成するＮ型
薄膜トランジスタにするには、次に、リン原子のイオン
注入をしてソース、ドレイン領域を形成後層間絶縁膜を
堆積し、コンタクトホールを開口して、ソース線とソー
ス領域を接続し、画素電極とドレイン領域を接続する。
通常ソース線は低抵抗のＡｌ、画素電極は透明なＩＴＯ
を用いる。次に、絶縁膜を堆積し、画素領域のみの絶縁
膜を除去する。対向基板はＣｒ膜に窓開けパターンを形
成した遮光マトリックス上に、カラーフィルター及び透
明ＩＴＯ電極を形成する。以上の２枚の基板に、配向膜
を塗布し、ラビングを行なってから液晶封入を行なえ
ば、パネルが完成する。絶縁膜２１０は、色づきがなけ
れば、画素電極上にあっても光学的には問題ないが、エ
ージング中に絶縁膜中や絶縁膜と配向膜の界面等に電荷
が蓄積されて、残像が起こりやすくなるため、画素電極
上は除去するのが普通である。The outline of the process is as follows. A transparent insulating substrate (eg, quartz glass plate), a polycrystalline silicon thin film is deposited and patterned, and then a gate insulating film is formed.
In order to form an N-type thin film transistor for forming a gate line and a gate electrode by depositing and patterning a heavily phosphorus-doped polycrystalline silicon thin film, next, ion implantation of phosphorus atoms is performed to form a source / drain region, and then an interlayer is formed. An insulating film is deposited, a contact hole is opened, a source line and a source region are connected, and a pixel electrode and a drain region are connected.
Normally, the source line has low resistance Al, and the pixel electrode has transparent ITO.
To use. Next, an insulating film is deposited and the insulating film only in the pixel region is removed. For the counter substrate, a color filter and a transparent ITO electrode are formed on a light-shielding matrix in which a window opening pattern is formed in a Cr film. A panel is completed by applying an alignment film to the above two substrates, rubbing them, and then enclosing the liquid crystal. As long as the insulating film 210 is not colored, there is no optical problem even if it is on the pixel electrode, but after aging, electric charge is accumulated in the insulating film or at the interface between the insulating film and the alignment film, and an afterimage occurs. Since it becomes easier, it is common to remove it on the pixel electrode.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
構造においては、画素電極上以外、特にソース線上の絶
縁膜と配向膜の界面等には電荷が蓄積される。したがっ
て蓄積された電荷により液晶に直流成分が発生し、液晶
の寿命を低下させ、表示品質の劣化を招く。一方ソース
線と液晶の反応を防止する上である程度の被ふく膜をソ
ース線上には形成する必要性もある。However, in the conventional structure, charges are accumulated other than on the pixel electrodes, particularly on the interface between the insulating film and the alignment film on the source line. Therefore, a direct current component is generated in the liquid crystal due to the accumulated charge, which shortens the life of the liquid crystal and causes deterioration of display quality. On the other hand, in order to prevent the reaction between the source line and the liquid crystal, it is necessary to form a film to be covered to some extent on the source line.
【０００５】以上の問題点を鑑みて、本発明の課題は、
ソース配線上または近傍の絶縁膜の最適化を行って、ソ
ース線の被ふく効果と、電荷蓄積防止効果を両立させ
て、表示品質の寿命を長めることを目的とする。In view of the above problems, the object of the present invention is to
It is an object of the present invention to optimize the insulating film on or near the source wiring to achieve both the effect of covering the source line and the effect of preventing charge accumulation and prolonging the life of display quality.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、本発明の液晶表示装置において講じた手段は、絶縁
性基板上で複数本のデータ線と走査線によって格子状に
区画形成された画素領域に、前記データ線に導電接続す
るソース及び前記走査線に導電接続するゲートを備える
薄膜トランジスタとこの薄膜トランジスタのドレインに
導電接続された画素電極を配置したアクティブマトリッ
クス基板と対向電極を有する対向基板と両基板に液晶を
挟持してなる液晶表示装置において、少なくとも前記ソ
ース線上に形成される絶縁膜による容量を配向膜容量と
同等又はそれ以上にすることである。Means for Solving the Problems In order to solve the above-mentioned problems, the measures taken in the liquid crystal display device of the present invention are formed in a grid pattern on an insulating substrate by a plurality of data lines and scanning lines. A thin film transistor having a source conductively connected to the data line and a gate conductively connected to the scan line in a pixel region; an active matrix substrate in which a pixel electrode conductively connected to a drain of the thin film transistor is arranged; In a liquid crystal display device in which liquid crystal is sandwiched between both substrates, at least the capacitance of the insulating film formed on the source line is equal to or more than the alignment film capacitance.
【０００７】[0007]
【作用】ソース線近傍の様子を図３を用いて説明する。
図３（ａ）は、図２（ｂ）のＣ部を拡大したものであ
り、図３（ｂ）は、その等価回路を示すものである。記
号は図２と図３で下２桁が同じものが同一材料である
（例えば、２０２と３０２は同じソース線である）ソー
ス線上において、ソース線から対向電極までは構造上絶
縁材料として絶縁膜３１０、配向膜３１１、液晶３１
２、配向膜３１６が存在する。したがって直列容量とし
て、Ｃ1 （絶縁膜）、Ｃ2 （配向膜１）、Ｃ3 （液
晶）、Ｃ4 （配向膜２）となり、絶縁膜としてＳｉＯ2
とし各層の膜厚をそれぞれ０．２μｍ、０．０５μｍ、
４μｍ、０．０５μｍ、誘電率をそれぞれ、４，３，６
−１０，３と仮定すると、Ｃ1 ：Ｃ2 ：Ｃ3 ：Ｃ4 ≒１
０：３０：１：３０となる。配向膜１，２を合わせて考
えると、Ｃ1 ：Ｃ2 ＋：Ｃ4 ＝Ｃ3 ≒１０：１５：１
となり、各層の電位差分布は、Ｖ1 ：Ｖ2 ＋Ｖ4 ：Ｖ3
≒１．５：１：１５となる。したがって外部印加電圧の
大半は液晶に印加されるが、配向膜より、絶縁膜の方が
多く印加されることになる。仮に絶縁膜、配向膜にトラ
ップ準位が多く存在した場合、電界誘起により絶縁膜、
配向膜界面に電荷が蓄積されるため、液晶に直流成分が
残存することになる。これを防止するには、絶縁膜、配
向膜のトラップ準位を低減するか、絶縁膜自身の容量を
増加して電圧分担を低減して電界を緩和すればよい。後
者の場合配向膜は構造上最低限必要なものであるから、
絶縁膜の電位分担を配向膜の電位分担以下にすること肝
要である。これは絶縁膜の膜厚を薄くするか誘電率の高
い材料を用いることで実現できる。絶縁膜を薄くする場
合電圧分担を低減する上、絶縁膜中の全トラップ量も減
少できるので相剰的な効果がある。また高誘電材料は、
絶縁性がやや劣るため、蓄積電荷の放電が行なわれやす
く、蓄積効果が軽減する。The operation in the vicinity of the source line will be described with reference to FIG.
FIG. 3A is an enlarged view of the C portion of FIG. 2B, and FIG. 3B shows an equivalent circuit thereof. Symbols in FIG. 2 and FIG. 3 have the same last two digits of the same material (for example, 202 and 302 are the same source line). On the source line, from the source line to the counter electrode, the insulating film is a structural insulating material. 310, alignment film 311, liquid crystal 31
2. There is an alignment film 316. Therefore, C 1 (insulating film), C 2 (alignment film 1), C 3 (liquid crystal), and C 4 (alignment film 2) are formed as series capacitors, and SiO 2 is formed as an insulating film.
And the film thickness of each layer is 0.2 μm, 0.05 μm,
4μm, 0.05μm, dielectric constant 4,3,6
Assuming −10,3, C 1 : C 2 : C 3 : C 4 ≈1
It becomes 0: 30: 1: 30. Considering the alignment films 1 and 2 together, C 1 : C 2 +: C 4 = C 3 ≈10: 15: 1
And the potential difference distribution of each layer is V 1 : V 2 + V 4 : V 3
≈1.5: 1: 15. Therefore, most of the externally applied voltage is applied to the liquid crystal, but more is applied to the insulating film than to the alignment film. If there are many trap levels in the insulating film and the alignment film, the insulating film,
Since a charge is accumulated at the interface of the alignment film, a direct current component remains in the liquid crystal. In order to prevent this, the trap level of the insulating film or the alignment film may be reduced, or the capacity of the insulating film itself may be increased to reduce the voltage sharing and relax the electric field. In the latter case, the alignment film is the minimum required structurally,
It is important that the potential sharing of the insulating film is equal to or less than the potential sharing of the alignment film. This can be realized by reducing the thickness of the insulating film or using a material having a high dielectric constant. When the insulating film is thinned, the voltage sharing is reduced and the total amount of traps in the insulating film can also be reduced, which has an additive effect. In addition, high dielectric materials are
Since the insulating property is slightly inferior, the accumulated charge is easily discharged and the accumulation effect is reduced.
【０００８】[0008]
（実施例１）図２において、ソース線上の絶縁膜とし
て、ＳｉＯ2 からＳｉＮx 、Ｔａ2 Ｏ5 といった高誘電
率材料にする場合である。誘電率は、ＳｉＯ2 が４、Ｓ
ｉＮxが７、Ｔａ2 Ｏ5 が２５であるため、作用の項で
述べた電位分布は膜厚を同じとすれば、ＳｉＮx でＶ
1 ：Ｖ2 ＋Ｖ4 ：Ｖ3 ≒０．９：１：１５、Ｔａ2 Ｏ5
でＶ1 ：Ｖ2 ＋Ｖ4 ：Ｖ3 ≒０．２４：１：１５とな
り、配向膜よりソース線被ふくの絶縁膜の電位分担を軽
減できる。容量でいえば、絶縁膜による容量が配向膜容
量と同等又はそれ以上となる。また絶縁膜をＳｉＯ2 、
Ｓｉ3 Ｎ4 、Ｔａ2 Ｏ5 、Ａｌ2 Ｏ3 の多層膜で構成し
てもよい。例えば、全膜厚を０．２μｍとした場合、Ｓ
ｉＯ2 、０．０５μｍ、Ｓｉ3 Ｎ4 、０．１５μｍとす
れば、Ｖ1 ：Ｖ2 ＋Ｖ4 ：Ｖ3 ≒１：１：１５となり、
絶縁膜容量が配向膜容量とほぼ同等になる。配向膜の膜
厚を厚くすると絶縁膜の膜厚も厚くしても電位分担は軽
減されるが、液晶にかかる電圧も低下し、ロスが多くな
り好ましくない。以上から配向膜の膜厚は０．０５μｍ
程度又はそれ以下とするのが良く、より高誘電材料を用
いれば膜厚はより厚く設定できるが０．３μｍ程度また
はそれ以下とするのが好ましい。(Embodiment 1) In FIG. 2, a high dielectric constant material such as SiO 2 to SiN x , Ta 2 O 5 is used as the insulating film on the source line. Dielectric constant is SiO 2 is 4, S
Since iN x is 7 and Ta 2 O 5 is 25, if the film thickness is the same, the potential distribution described in the section of action is V in SiN x .
1 : V 2 + V 4 : V 3 ≈0.9: 1: 15, Ta 2 O 5
Then, V 1 : V 2 + V 4 : V 3 ≈0.24: 1: 15, and the potential sharing of the insulating film of the source line covering can be reduced from that of the alignment film. In terms of capacity, the capacity of the insulating film is equal to or higher than the capacity of the alignment film. The insulating film is SiO 2 ,
Si 3 N 4, Ta 2 O 5, may be constructed as a multilayer film of Al 2 O 3. For example, if the total film thickness is 0.2 μm, S
If iO 2 , 0.05 μm, Si 3 N 4 , and 0.15 μm, V 1 : V 2 + V 4 : V 3 ≈1: 1: 15,
The insulating film capacity is almost the same as the orientation film capacity. If the film thickness of the alignment film is increased, the potential sharing is reduced even if the film thickness of the insulating film is increased, but the voltage applied to the liquid crystal is also reduced, and the loss is increased, which is not preferable. From the above, the thickness of the alignment film is 0.05 μm
The film thickness can be set to about or less, and the film thickness can be set thicker by using a higher dielectric material, but about 0.3 μm or less is preferable.
【０００９】（実施例２）図１は第２の実施例を示すも
のであり、アクティブマトリックス液晶パネルの平面図
（ａ）とそのＢ−Ｂ′断面図（ｂ）からなる。記号は図
１と図２で下２桁が同じものが同一材料である。しかし
図１と図２は若干構造が異なる。すなわち、第１の層間
絶縁膜１０９ａにコンタクトホールを開口して、ソース
線とソース領域を接続するまでは同じであるがドレイン
領域と接続する積み上げ電極１０８ｂを形成する。次に
第２の層間絶縁膜１０９ｂを堆積し、積み上げ電極上に
コンタクトホールを開口し、積み上げ電極１０８ｂと画
素電極１０８ａを導電接続する。この場合、ソース線上
は第２層間絶縁膜１０９ｂで被ふくされているため、図
２のような絶縁膜２１０の代用となる。この構造は、基
板全体を平坦化することが可能で、かつソース線１０２
と画素電極１０８ａが絶縁分離されているので、ソース
線、画素電極間隔を著しく狭くすることができ、パネル
開口率の向上が期待できるため、理想的な構造である。
しかしソース線１０２上に限って考えれば、第２層間絶
縁膜の膜厚は、図２ような薄い場合もあるが、最密構造
パネルにあっては、ソース線と画素電極間の容量を減ら
す目的で十分厚くする必要がある。この場合、ソース線
上の絶縁膜の容量が減少し、電圧分担が大きくなり、蓄
積電荷が増大し、残像が発生することがある。したがっ
て、図１（ｂ）に示すように、ソース線上の層間絶縁膜
を選択的に薄くして絶縁膜の容量を配向膜容量と同等又
はそれ以上にすることを提案する。膜厚は、実施例１に
示されたように設定する。具体的に、選択的に層間絶縁
膜を薄くするには、画素電極１０８ａのパターンを用い
るか、ソース線上のみを除去するような専用パターンを
用いて層間絶縁膜を適量エッチングすればよい。適量の
エッチングで、エッチングのエンドがわかりずらいよう
な場合には、層間絶縁膜を２種の積層膜として行えばよ
い。図４は、図１（ｂ）のソース線上Ｄの拡大図であ
る。記号は図１と図４で下２桁が同じものが対応する。
第２層間絶縁膜４０９ｂは下層ＳｉＮx 膜４０９ｂ−１
上層ＳｉＯ2 膜４０９−２から成り、下層膜をエッチス
トッパーとして上層膜のみを除去し、層間絶縁膜４０９
ｂを薄くすることで、ソース線上の絶縁膜の容量を配向
膜の容量よりも増せしている。下層絶縁膜４０９ｂ−１
は、高誘電材料の多層膜としてもよいしソース線の酸化
膜（例えばＡｌのソース線であればＡｌ2 Ｏ3 ）でもよ
い。(Embodiment 2) FIG. 1 shows a second embodiment, which is composed of a plan view (a) of an active matrix liquid crystal panel and a BB 'sectional view (b) thereof. Symbols in FIG. 1 and FIG. 2 having the same last two digits are the same material. However, the structures in FIGS. 1 and 2 are slightly different. That is, a contact hole is opened in the first interlayer insulating film 109a, and the stacked electrode 108b which is the same until the source line and the source region are connected but is connected to the drain region is formed. Next, a second interlayer insulating film 109b is deposited, a contact hole is opened on the stacked electrode, and the stacked electrode 108b and the pixel electrode 108a are conductively connected. In this case, since the source line is covered with the second interlayer insulating film 109b, it serves as a substitute for the insulating film 210 as shown in FIG. This structure makes it possible to planarize the entire substrate and the source line 102.
Since the pixel electrode 108a and the pixel electrode 108a are insulated and separated from each other, the distance between the source line and the pixel electrode can be significantly narrowed, and the panel aperture ratio can be expected to be improved, which is an ideal structure.
However, considering only on the source line 102, the thickness of the second interlayer insulating film may be thin as shown in FIG. 2, but in the close-packed structure panel, the capacitance between the source line and the pixel electrode is reduced. It should be thick enough for the purpose. In this case, the capacitance of the insulating film on the source line decreases, the voltage sharing increases, the accumulated charge increases, and an afterimage may occur. Therefore, as shown in FIG. 1B, it is proposed that the interlayer insulating film on the source line be selectively thinned so that the capacity of the insulating film is equal to or more than the orientation film capacity. The film thickness is set as shown in Example 1. Specifically, in order to selectively thin the interlayer insulating film, a suitable amount of the interlayer insulating film may be etched using a pattern of the pixel electrode 108a or a dedicated pattern for removing only the source line. When it is difficult to understand the end of etching with an appropriate amount of etching, the interlayer insulating film may be formed as a laminated film of two types. FIG. 4 is an enlarged view of D on the source line in FIG. Symbols corresponding to those having the same last two digits in FIG. 1 and FIG. 4 correspond.
The second interlayer insulating film 409b is a lower SiN x film 409b-1.
The upper layer film is composed of the upper layer SiO 2 film 409-2, and only the upper layer film is removed by using the lower layer film as an etch stopper.
By making b thin, the capacitance of the insulating film on the source line is made larger than that of the alignment film. Lower insulating film 409b-1
May be a multilayer film of a high dielectric material or an oxide film of a source line (for example, Al 2 O 3 for an Al source line).
【００１０】また図４の構造は、図２（ｂ）のＣ部に適
用することが第２層間絶縁膜４０９ｂを絶縁膜２１０と
おきかえることで構造的にもプロセス的にも可能であ
る。The structure of FIG. 4 can be applied to the portion C of FIG. 2 (b) by replacing the second interlayer insulating film 409b with the insulating film 210, both structurally and processally.
【００１１】[0011]
【発明の効果】以上述べたように、本発明によれば、ソ
ース線上又は近傍の絶縁膜に高誘電率の材料を用いる
が、薄膜化することによって絶縁膜の容量を配向膜の容
量と同等又はそれ以上とすることで、絶縁膜の電位分担
を軽減できる。その結果絶縁膜と配向膜界面の誘起電荷
の蓄積を抑制することで、残像を軽減し、液晶の品質劣
化を防止することが可能になる。As described above, according to the present invention, a material having a high dielectric constant is used for the insulating film on or near the source line. However, by making it thinner, the capacitance of the insulating film becomes equal to that of the alignment film. By setting it to be more, it is possible to reduce the potential sharing of the insulating film. As a result, by suppressing the accumulation of induced charges at the interface between the insulating film and the alignment film, it is possible to reduce the afterimage and prevent deterioration of the quality of the liquid crystal.
【図１】本発明の実施例を示すアクティブマトリックス
液晶パネルの平面図（ａ）とそのＢ−Ｂ′断面図
（ｂ）。FIG. 1 is a plan view (a) of an active matrix liquid crystal panel showing an embodiment of the present invention and a BB ′ sectional view thereof (b).
【図２】従来のアクティブマトリックス液晶パネルの平
面図（ａ）とそのＡ−Ａ′断面図（ｂ）。FIG. 2A is a plan view of a conventional active matrix liquid crystal panel and FIG. 2B is a sectional view taken along the line AA ′ of FIG.
【図３】図２（ｂ）のＣ部拡大図（ａ）とその等価回路
図（ｂ）。FIG. 3 is an enlarged view (a) of a C portion of FIG. 2 (b) and its equivalent circuit diagram (b).
【図４】図１（ｂ）のＤ部拡大図。FIG. 4 is an enlarged view of a D portion of FIG.
１０１ 絶縁性基板 １０２ ソース線 １０３ ゲート線 １０４ ゲート電極 １０５ ソース領域 １０６ ドレイン領域 １０７ チャンネル領域 １０８ａ 画素電極 １０８ｂ 積み上げ電極 １０９ａ 第１層間絶縁膜 １０９ｂ 第２層間絶縁膜 １１１ 配向膜 １１２ 液晶 １１３ 対向基板 １１４ ブラックマトリックス遮光膜 １１５ 対向電極 １１６ 配向膜 101 insulating substrate 102 source line 103 gate line 104 gate electrode 105 source region 106 drain region 107 channel region 108a pixel electrode 108b stacked electrode 109a first interlayer insulating film 109b second interlayer insulating film 111 alignment film 112 liquid crystal 113 counter substrate 114 black Matrix light-shielding film 115 counter electrode 116 alignment film
Claims (4)
によって格子状に区画形成された画素領域に、前記デー
タ線に導電接続するソース及び前記走査線に導電接続す
るゲートを備える薄膜トランジスタとこの薄膜トランジ
スタのドレインに導電接続された画素電極を配置したア
クティブマトリックス基板と対向電極を有する対向基板
と両基板に液晶を挟持してなる液晶表示装置において、
少なくとも前記ソース線上に形成される絶縁膜による容
量を配向膜容量と同等又はそれ以上にすることを特徴と
する液晶表示装置。1. A thin film transistor having a source area conductively connected to the data line and a gate area conductively connected to the scanning line in a pixel region partitioned and formed in a grid pattern by a plurality of data lines and scanning lines on an insulating substrate. And a liquid crystal display device comprising a liquid crystal sandwiched between an active matrix substrate in which a pixel electrode conductively connected to the drain of the thin film transistor is arranged, an opposite substrate having an opposite electrode, and both substrates,
A liquid crystal display device, wherein the capacitance of at least the insulating film formed on the source line is equal to or more than the capacitance of the alignment film.
とする請求項１記載の液晶表示装置。2. The liquid crystal display device according to claim 1, wherein the insulating film is a high dielectric film.
することを特徴とする請求項１記載の液晶表示装置。3. The liquid crystal display device according to claim 1, wherein the insulating film on the source line is selectively thinned.
とする請求項１記載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the insulating film has a multilayer film structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9806993A JPH06308531A (en) | 1993-04-23 | 1993-04-23 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9806993A JPH06308531A (en) | 1993-04-23 | 1993-04-23 | Liquid crystal display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06308531A true JPH06308531A (en) | 1994-11-04 |
Family
ID=14210057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9806993A Pending JPH06308531A (en) | 1993-04-23 | 1993-04-23 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06308531A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100356832B1 (en) * | 1999-04-23 | 2002-10-18 | 주식회사 현대 디스플레이 테크놀로지 | Method for manufacturing high aperture ratio and high transmittance LCD |
| US7517738B2 (en) | 1995-01-17 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor |
| US8835271B2 (en) | 2002-04-09 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US8946717B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9366930B2 (en) | 2002-05-17 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device with capacitor elements |
-
1993
- 1993-04-23 JP JP9806993A patent/JPH06308531A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7517738B2 (en) | 1995-01-17 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor |
| KR100356832B1 (en) * | 1999-04-23 | 2002-10-18 | 주식회사 현대 디스플레이 테크놀로지 | Method for manufacturing high aperture ratio and high transmittance LCD |
| US9666614B2 (en) | 2002-04-09 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US10700106B2 (en) | 2002-04-09 | 2020-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US8946718B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9105727B2 (en) | 2002-04-09 | 2015-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US8946717B2 (en) | 2002-04-09 | 2015-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9406806B2 (en) | 2002-04-09 | 2016-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US8835271B2 (en) | 2002-04-09 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US10050065B2 (en) | 2002-04-09 | 2018-08-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US10083995B2 (en) | 2002-04-09 | 2018-09-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US11101299B2 (en) | 2002-04-09 | 2021-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
| US10854642B2 (en) | 2002-04-09 | 2020-12-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
| US9366930B2 (en) | 2002-05-17 | 2016-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device with capacitor elements |
| US10527903B2 (en) | 2002-05-17 | 2020-01-07 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US10133139B2 (en) | 2002-05-17 | 2018-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US11422423B2 (en) | 2002-05-17 | 2022-08-23 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3708637B2 (en) | Liquid crystal display device | |
| US6028653A (en) | Active matrix liquid crystal display panel having an improved numerical aperture and display reliability and wiring designing method therefor | |
| EP0668528B1 (en) | Thin film field effect transistor array for use in active matrix liquid crystal display | |
| US5737049A (en) | Liquid crystal display device having storage capacitors of increased capacitance and fabrication method therefor | |
| US6373546B1 (en) | Structure of a liquid crystal display and the method of manufacturing the same | |
| JP3226836B2 (en) | Liquid crystal display device and manufacturing method thereof | |
| US7170571B2 (en) | Liquid crystal display device with double metal layer source and drain electrodes and fabricating method thereof | |
| KR100218293B1 (en) | Thin film transistor liquid crystal display device and manufacturing method thereof | |
| EP0329887B1 (en) | Liquid crystal display device | |
| JP2001196595A (en) | Active matrix substrate and manufacturing method thereof | |
| US7602452B2 (en) | Liquid crystal display device and method for manufacturing the same | |
| JPH03280018A (en) | Liquid crystal display device | |
| JPH06281956A (en) | Active matrix wiring board | |
| JP2940689B2 (en) | Thin film transistor array of active matrix display device and method of manufacturing the same | |
| US6876404B2 (en) | Liquid crystal display device and fabricating method thereof | |
| KR100308853B1 (en) | A storage capacitor of a liquid crystal display and a fabricating method thereof | |
| US7619695B2 (en) | Liquid crystal display and manufacturing method therefor | |
| US20070273803A1 (en) | Active component array substrate and fabricating method thereof | |
| JPH06308531A (en) | Liquid crystal display | |
| JPH09127556A (en) | Display device and driving method thereof | |
| KR100488936B1 (en) | LCD | |
| JP3427664B2 (en) | Horizontal electric field type active matrix liquid crystal display | |
| JPH112828A (en) | Liquid crystal image display device and method of manufacturing the same | |
| JPH0862629A (en) | Liquid crystal display | |
| JP3119233B2 (en) | Liquid crystal display device and method of manufacturing the same |