JPH06310735A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which the quantum confinement effect is enhanced in the planar direction and thereby a fine quantum line or quantum dot structure having high confinement potential and narrow confinement width is provided. CONSTITUTION:A quantum well structure having a single quantum well layer 14 of GaInAs is formed on a semiinsulating GaAs (1,1,0) substrate 11. A GaAs layer 16 and a multiple quantum well layer 18, which function as a strain application layer when a mesa type stripe groove 17 is formed, are then formed thereon. Quantum confinement is achieved in [-1, 1, 1] direction by the sum of the variation in the deformation potential and the variation in the piezoelectric potential of the quantum well layer 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a quantum wire or quantum dot structure formed on a semiconductor substrate, for example, a quantum effect which can be used for a field effect transistor, an arithmetic element, a memory element and the like. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in a device having a quantum well structure formed on a semiconductor substrate, a method of forming a quantum wire by giving a strain change to the quantum well layer in the in-plane direction is known. (Phys. Rev. Lette
r, 67, 1326 (1991)).

When a quantum well structure is formed on a semiconductor substrate and strain is changed in the in-plane direction in the quantum well layer in the quantum well structure, the deformation potential in the in-plane direction changes. This deformation potential causes a quantum confinement effect in the in-plane direction of the quantum well layer, thereby forming a quantum wire structure. For example, in the above-mentioned prior literature, a plurality of layers including a GaAs quantum well layer are formed on a (001) GaAs substrate by a molecular beam epitaxy method (MBE method).
And then removing the amorphous carbon film by vapor deposition on the formed quantum well structure, and removing the amorphous carbon film by the residual stress after the formation and removal of the amorphous carbon film. Describes a method of forming a quantum wire structure by applying a strain change in the [010] direction.

[0004]

However, in the method of forming the quantum confinement structure in the in-plane direction of the quantum well layer and forming the quantum wires or quantum dots as described above, the confinement potential in the in-plane direction is small. There was a problem. Further, when a confinement structure is formed in the in-plane direction by giving a strain change in the in-plane direction as described above, the confinement potential can be increased by narrowing the confinement width. Then, it was difficult to narrow the confinement width in the in-plane direction.

The object of the present invention is to solve the above-mentioned drawbacks of the conventional quantum wire or quantum dot structure, to have a large confinement potential in the in-plane direction of the quantum well layer, and to narrow the confinement width in the in-plane direction. It is to provide a semiconductor device having a thin wire or quantum dot structure.

[0006]

The present invention comprises a semiconductor substrate and a quantum well layer having a zinc blende type crystal structure formed on the semiconductor substrate to form a quantum well structure. In a semiconductor device in which a quantum wire or quantum dot structure is formed by applying strain change to the well layer in the in-plane direction, a semiconductor substrate has a piezoelectric potential in the quantum well layer in the in-plane direction of the quantum well layer. Direction, and is laminated directly or indirectly on the quantum well layer to give a strain change in the in-plane direction, and in-plane in the direction in which the piezoelectric potential of the quantum well layer is generated. A semiconductor device comprising a strain applying layer that gives a strain change.

That is, according to the present invention, the quantum confinement in the in-plane direction of the quantum well layer is determined not by the confining width in the in-plane direction but by the quantum well layer made of a semiconductor having a zinc blende type crystal structure in the in-plane direction. In view of the fact that a piezoelectric potential is generated when a force is applied in a certain direction, the strain applying layer is formed so as to also utilize the change in the piezoelectric potential, thereby enhancing the in-plane confinement effect. Have.

According to the present invention, the strain applying layer comprises:
As described in (3) above, it is composed of at least one semiconductor layer whose lattice constant is changed in the direction in which the piezoelectric potential is generated. Note that, as a mode in which the lattice constant changes, not only the thickness of the semiconductor layer is changed, but the semiconductor layer is partially removed by etching or the like, and the semiconductor layer is partially cut off in the in-plane direction. It also includes the case where the part that is formed is formed.

[0009]

In the present invention, the strain applying layer laminated directly or indirectly with respect to the quantum well layer gives an in-plane strain change in the direction in which the piezoelectric potential is generated in the in-plane direction of the quantum well layer. Therefore, in the direction in which the piezoelectric potential of the quantum well layer is generated, the potential of the conduction band is the sum of the deformation potential and the piezoelectric potential. Therefore, in the middle of the direction in which the piezoelectric potential is generated, the deformation potential due to in-plane strain is generated. And the piezoelectric potential will form a potential well. Therefore, the quantum confinement effect in the in-plane direction can be further increased, and the quantum confinement width can be narrowed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be clarified by describing embodiments of the present invention with reference to the drawings.

A field effect transistor as a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2, as shown in FIG. 1 (a), the horizontal direction of the drawing is the [-1,1,1] direction.
FIG. 4 is a cross-sectional view in which the lateral direction of the drawing is the [1, −1,2] direction.

First, the semi-insulating GaAs substrate 11 (CrO
The undoped GaAs buffer layer 12 is formed on the doped GaAs and the crystal orientation is (110) by, for example, the MBE method.
(Film thickness = 1 μm), GaAs barrier layer 13 (Si-doped, 2 × 10 ¹⁸ cm ⁻³ , film thickness = 5 nm), undoped Ga _0.75 In _0.25 As quantum well layer 14 (single quantum well,
Film thickness = 5 nm), undoped AlAs barrier layer 15
(Film thickness = 2 nm) and undoped GaAs layer 16 (film thickness = 50 nm) were grown.

Next, as shown in FIG. 1B, the GaAs layer 16 is etched to form a mesa stripe groove 17 having a depth of 30 nm extending in the [1, -1,2] direction and a width of 150 nm on the opening side. Was formed. Although this etching is performed by wet etching using a sulfuric acid-based etchant, it may be performed by dry etching such as reactive ion beam etching using chlorine gas.

Next, in the MBE apparatus, the substrate temperature is set to 700 to 750 ° C., the molecular beam of As is irradiated in the As atmosphere, and the bottom Al of the stripe groove 17 is irradiated.
The GaAs layer 16 was evaporated until the As barrier layer 15 was exposed (see FIG. 1C).

Thereafter, as shown in FIG. 2, the multiple quantum well layer 18 was grown by the MBE method. The multiple quantum well layer 18 is made of undoped Ga _0.9 In _0.1 As (film thickness = 5).
nm) and GaAs (film thickness = 5 nm), and these laminated structures were formed by repeating three layers.

Next, referring to FIG. 3A, the stripe groove 17 is formed.
As shown in a cross section in which the [1, -1,2] direction is the lateral direction, the portion where the
By implanting i ions, an n-type region 19 having a thickness of 500 nm shown by hatching is formed. Further, as shown in FIG. 3B, electrodes 20 and 21 which make ohmic contact with the upper surface were formed by a method such as vapor deposition. The electrode 21 functions as the gate electrode of the FET, and the electrodes 20, 2
0 functions as a source electrode and a drain electrode.

In the FET obtained as described above,
A quantum confinement effect is obtained in the [-1,1,1] direction, and quantum wires are formed. This will be described with reference to FIG.

As shown in the cross-sectional view below FIG. 4, in the FET of this embodiment, above the quantum well layer 14, [-
The direction perpendicular to the [1,1,1] direction, that is, [1,-
The stripe groove 17 is formed so as to extend in the 1, 2] direction. Therefore, Ga forming the quantum well layer
_The GaAs layer 16 having a smaller lattice constant than _0.75 In _0.25 As is removed in the portion where the stripe groove 17 is formed. Therefore, by providing the stripe groove 17, the in-plane strain change in the [-1,1,1] direction is given by the GaAs layer 16 and the multiple quantum well layer 18.

Therefore, the change in the deformation potential applied to the quantum well layer 14 by forming the stripe groove 17 is as shown by the broken line A in the upper part of FIG. On the other hand, the quantum well layer 14 generates a piezoelectric potential in the [-1,1,1] direction. Therefore, the above GaA
given by the s-layer 16 and the multiple quantum well layer 18 [-
Due to the in-plane strain change in the [1,1,1] direction, a piezoelectric potential indicated by a chain line B in the upper part of FIG. 4 is generated. That is, in the FET of this embodiment, the sum of the change in deformation potential and the change in piezoelectric potential gives
As shown by the solid line C, the conduction band potential changes. Therefore, in the portion where the stripe groove 17 is formed, a quantum wire structure extending in the [1, -1,2] direction is realized.

In the FET of this embodiment, in the quantum wire structure formed as described above, the GaAs functioning as the strain applying layer in the [-1,1,1] direction.
The layer 16 and the multiple quantum well layer 18 generate not only the deformation potential but also the in-plane strain in the [-1,1,1] direction to generate the piezoelectric potential.
The quantum confinement effect in the 1] direction becomes large, and the confinement width can be narrowed.

In this embodiment, Ga is used as the strain applying layer for achieving the quantum confinement in the [-1,1,1] direction.
Although the As layer 16 and the multiple quantum well layer 18 have been used, even when the multiple quantum well layer 18 is not formed and only the GaAs layer 16 in which the stripe groove 17 is formed as described above is formed, The quantum confinement in the -1,1,1] direction can be effectively performed.

FIG. 5 and FIG. 6 show the second semiconductor device of the invention.
FIG. 6 is a plan view showing a resonant tunnel diode array as an example of FIG. 5 and a sectional view of a portion taken along the line AA of FIG. 5.
Referring to FIGS. 5 and 6, in the diode array according to the present embodiment, first, Si-doped n-type semi-insulating GaAs is used.
On the substrate 31 (Si-doped, crystal orientation (110)), M
By the BE method, the n-type GaAs buffer layer 32 (Si-doped, amount of dopant 2 × 10 ¹⁸ cm ⁻³ , thickness = 1 μm)
m), an undoped GaAs layer 33 (thickness = 0.1 μm
m), undoped Al _0.35 Ga _0.65 As barrier layer 34
(Thickness = 5 nm), undoped GaAs single quantum well layer 35 (thickness = 5 nm), undoped Al _0.35 Ga
_{A 0.65} As barrier layer 36 (film thickness = 5 nm) and 25 sets of multiple quantum well layers 37 made of undoped Ga _0.9 In _0.1 As (film thickness = 1 nm) / GaAs (film thickness = 1 nm) were grown. Next, similar to Example 1, wet etching or dry etching was performed to form a mesa-shaped convex portion 37a having a plane shape of 40 nm in height and a bottom shape of a square having a side of 170 nm.

Next, an undoped GaAs layer 38 (film thickness = 0.1 μm) and an n-type GaAs buffer layer 39 (Si
Dope, amount of dopant 2 × 10 ¹⁸ cm ⁻³ , film thickness = 1 μ
m) was grown by the MBE method. Then, ohmic electrodes 40 and 41 were formed on the entire upper surface and lower surface.

In the resonant tunnel diode array of the present embodiment obtained as described above, in order to give an in-plane strain to the quantum well layer 35 above the quantum well structure having the single quantum well layer 35, The convex portion 37a is formed. That is, although the crystal orientation is shown on the right side of FIG. 5, the quantum well layer 35 generates a piezoelectric potential in the [0,0, -1] direction, but the quantum well layer 35 has a different lattice constant from that of the multiple quantum well layer 35. The thickness of the layer 37 is thick at the portion where the convex portion 37a is provided.

Therefore, by forming the convex portion 37a, the in-plane strain change is given to the quantum well layer 35 in the entire in-plane direction. Moreover, the quantum well layer 35 has [0,
A piezoelectric potential is generated in the 0, −1] direction. Therefore, in this embodiment, in the quantum well layer 35,
A quantum dot structure is formed at a corner portion (portion indicated by arrow X in FIG. 5) in the [0,0, −1] direction of the convex portion 37a having a square planar shape.

Moreover, in each diode element in the diode array of this embodiment, the in-plane strain change is applied in the [0, 0, -1] direction, which is the direction in which the piezoelectric potential is generated, as in the case of the first embodiment. Therefore, the quantum confinement effect is effectively enhanced by the sum of the change in the deformation potential and the change in the piezoelectric potential.

Therefore, when a current is passed between the upper and lower electrodes 40, 41, the diode element has the above-mentioned quantum dot structure, so that each diode element has a multiple quantum well layer in the energy range in which the negative resistance remarkably increases. A current flows due to a tunnel phenomenon due to resonance of energy levels between 37 and the quantum well layer 35.

In each of the first and second embodiments, the strain applying layer is arranged above the quantum well layer, but the strain applying layer in the present invention is arranged below the quantum well layer. May be.

Further, in the first embodiment, (110) Ga
In the quantum well layer formed on the As substrate [-1, 1, 1]
Quantum confinement in the direction to form a quantum wire,
In addition, in the second embodiment, the quantum dot structure is formed by performing quantum confinement in the [0, 0, -1] direction in the quantum well layer formed on the (110) GaAs substrate. The direction of in-plane quantum confinement is not limited to this. In short, the crystal orientation of the substrate is
Both of the in-plane directions of the quantum well layer may be selected so as to include the direction in which the piezoelectric potential is generated.

[0030]

According to the present invention, the strain is applied by the strain applying layer in the direction in which the piezoelectric potential is generated in the quantum well layer in the in-plane direction of the quantum well layer. Therefore, quantum confinement in the in-plane direction is performed by both the change in the deformation potential and the change in the piezoelectric potential provided by the strain applying layer. Therefore, the quantum confinement effect can be enhanced and the confinement width can be narrowed as compared with the conventional quantum wire structure or quantum dot structure.

Therefore, in the semiconductor device of the present invention, the confinement potential in the in-plane direction can be increased and the confinement width in the in-plane direction can be narrowed. Therefore, when applied to an FET, for example, the ground state and the first excitation By increasing the energy level difference between states, elastic scattering can be suppressed and carrier mobility can be increased. Therefore, it becomes possible to provide a higher speed FET.

[Brief description of drawings]

1A to 1C are FEs as a first embodiment.
6A to 6C are cross-sectional views for explaining a process of manufacturing T.

FIG. 2 is a cross-sectional view for explaining the manufacturing process of the FET of the first embodiment.

3A and 3B are cross-sectional views for explaining the manufacturing process of the FET of the first embodiment.

FIG. 4 is a schematic diagram for explaining the principle of in-plane confinement in the FET of the first embodiment.

FIG. 5 is a plan view of a resonant tunnel diode as a second embodiment.

6 is a sectional view taken along the line AA of FIG.

[Explanation of symbols]

11 ... Semi-insulating GaAs (110) substrate 13 ... GaAs barrier layer 14 ... Single quantum well layer 15 ... AlAs barrier layer 16 ... GaAs layer functioning as a strain applying layer 17 ... Mesa-type stripe groove 18 ... Multiple quantum well layer 20 , 21 ... Electrode 31 ... Semi-insulating GaAs (110) substrate 34 ... Al _0.35 Ga _0.65 As barrier layer 35 ... Single quantum well layer 36 ... Al _0.35 Ga _0.65 As barrier layer 37 ... Multiple quantum well layer 37a ... Convex portion 40 , 41 ... Electrodes

Claims (2)

[Claims] 1. A semiconductor substrate, and a quantum well layer having a zinc blende type crystal structure formed to form a quantum well structure on the semiconductor substrate, wherein the quantum well layer is strained in an in-plane direction. In a semiconductor device having a quantum wire or quantum dot structure formed by applying a change, the semiconductor substrate is oriented in a crystal orientation including a direction in which a piezoelectric potential is generated in the quantum well layer in an in-plane direction of the quantum well layer. A strain applied to the quantum well layer directly or indirectly to give a strain change in the in-plane direction, and a strain applied to give a strain change in the direction in which the piezoelectric potential of the quantum well layer is generated. A semiconductor device comprising a layer. 2. The semiconductor according to claim 1, wherein the strain applying layer is composed of at least one semiconductor layer whose lattice constant is changed in a direction in which the piezoelectric potential is generated. apparatus.