JPH06310859A - Manufacture of multilayer thin-film wiring substrate - Google Patents

Manufacture of multilayer thin-film wiring substrate

Info

Publication number
JPH06310859A
JPH06310859A JP9772793A JP9772793A JPH06310859A JP H06310859 A JPH06310859 A JP H06310859A JP 9772793 A JP9772793 A JP 9772793A JP 9772793 A JP9772793 A JP 9772793A JP H06310859 A JPH06310859 A JP H06310859A
Authority
JP
Japan
Prior art keywords
inner layer
layer circuit
outer peripheral
multilayer wiring
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9772793A
Other languages
Japanese (ja)
Inventor
Yoshihiro Tamura
義広 田村
Kanji Murakami
敢次 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP9772793A priority Critical patent/JPH06310859A/en
Publication of JPH06310859A publication Critical patent/JPH06310859A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To manufacture a multilayer wiring board in less positional error by a method wherein a conductor in triangular shape as an outer peripheral is simultaneously arranged on the outer periphery of an inner layer circuit when the circuit of the inner layer circuit board is formed. CONSTITUTION:An etching resist is stuck on both surface of a 0.2mm thick glass epoxy resin Cu plating laminated board. Next, specific pattern and triangular outer peripheral conductor frame are formed on both surfaces of an inner layer board by patterning the etching resist to be etched using a negative film arranging a triangular outer peripheral frame pattern on a circuit pattern and the outer periphery. Next, 0.1mm thick glass fiber epoxy resin prepreg is inserted into the inner layer circuit plate. Furthermore, successive inner layer circuit plate is aligned to be arranged. Next, a bonding sheet and a 18 micron copper foiled mirror plate are arranged on both sides of the inner layer circuit. Next, the whole body is thermal pressure fixed for 90min at molding temperature of 170 deg.C and forming pressure of 4 MPa to obtain a 0.8mm thick six layer multilayer wiring board. Through these procedures, the multilayer wiring board in less positional error to be manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子計算機、無線機器、
電送機器等に用いられる多層配線板の製造方法に関する
ものである。
BACKGROUND OF THE INVENTION The present invention relates to an electronic computer, a wireless device,
The present invention relates to a method for manufacturing a multilayer wiring board used for electric transmission equipment and the like.

【0002】[0002]

【従来の技術】一般に多層配線板は、予め所望の導体回
路を形成した内層回路板を複数枚作成し、その間に接着
シートを介し、必要に応じてさらに内層板の外側に接着
シートや銅箔を配し、これらを加熱、加圧し積層接着し
て形成されている。多層配線板の寸法精度や板厚精度を
維持するためには各種工程中での内層回路の変形を防止
し、寸法精度を高めることが必要で、層間の位置ずれを
防止することが多層配線板の品質上特に重要である。こ
のずれを防止するため、一般的に内層回路板の外周部に
帯状の導体部を設ける方法が用いられている。
2. Description of the Related Art Generally, in a multilayer wiring board, a plurality of inner layer circuit boards on which desired conductor circuits are formed are prepared in advance, and an adhesive sheet is interposed therebetween, and if necessary, an adhesive sheet or a copper foil is further provided outside the inner layer board. Are arranged, and they are heated and pressed to be laminated and adhered to each other. In order to maintain the dimensional accuracy and the board thickness accuracy of the multilayer wiring board, it is necessary to prevent deformation of the inner layer circuit during various processes and to improve the dimensional accuracy. Is especially important for quality. In order to prevent this shift, a method of providing a strip-shaped conductor portion on the outer peripheral portion of the inner layer circuit board is generally used.

【0003】[0003]

【発明が解決しようとする課題】一般的に用いられてい
る帯状の導体部を設ける方法では、積層接着する際、内
層回路板が変形し寸法精度を低下させ、さらに、内層回
路板間のパターン位置精度を低下させるという重大な課
題を有している。
In the generally used method of providing a strip-shaped conductor portion, the inner-layer circuit board is deformed to reduce the dimensional accuracy when laminated and bonded, and the pattern between the inner-layer circuit boards is further reduced. It has a serious problem of reducing the position accuracy.

【0004】本発明は、複数枚の内層回路板のパターン
位置精度が高い多層配線板の製造方法を提供するもので
ある。
The present invention provides a method for manufacturing a multilayer wiring board in which the pattern position accuracy of a plurality of inner layer circuit boards is high.

【0005】[0005]

【課題を解決するための手段】本発明の多層配線板の製
造方法は、複数枚の内層回路板を接着シートを介して熱
圧着形成する多層配線板の製造方法において、前記内層
回路板の回路形成する際、同時に内層回路外周部に三角
形状の導体部分を外周枠とし、配置することを特徴とす
る。
A method for manufacturing a multilayer wiring board according to the present invention is a method for manufacturing a multilayer wiring board in which a plurality of inner layer circuit boards are thermocompression-bonded via an adhesive sheet. At the time of formation, a triangular conductor portion is simultaneously formed as an outer peripheral frame on the outer peripheral portion of the inner layer circuit, and is arranged.

【0006】本発明を図1を用い説明する。図1−Aに
示すように内層板を準備する。この時内層板は両面銅張
り積層板でもよいが、片面銅張り積層板等を使用しても
よい。次に図1−Bに示すように内層板にエッチングレ
ジストをラミネートした後、焼き付け及び現像を行う。
この時内層板表面上にエッチングレジストを直接印刷
し、回路描写してもよい。この回路描写と同時に内層板
外周部に1三角形状外周部を形成することが望ましい。
次に図1−Cに示すようにエッチングし、所望の回路パ
ターンと三角形状導体外周枠を形成する。次に、図1−
Dに示すように内層回路板に接着シートを介す。さらに
内層回路板を配し、両側に接着シート及び銅箔又は片面
銅張り積層板、多層配線板、耐熱シート等を配し、鏡板
で挟み込む。この後、図1−Eに示すように加熱、加圧
することで積層接着する。加熱、加圧する手段、条件は
従来と同じものが使用できる。これにより図1−Fに示
す多層配線板を製造することができる。
The present invention will be described with reference to FIG. An inner layer plate is prepared as shown in FIG. 1-A. At this time, the inner layer plate may be a double-sided copper-clad laminated plate, or may be a single-sided copper-clad laminated plate. Next, as shown in FIG. 1-B, after laminating an etching resist on the inner layer plate, baking and development are performed.
At this time, an etching resist may be directly printed on the surface of the inner layer plate to draw a circuit. At the same time as this circuit drawing, it is desirable to form one triangular outer peripheral portion on the outer peripheral portion of the inner layer plate.
Next, as shown in FIG. 1-C, etching is performed to form a desired circuit pattern and a triangular conductor outer peripheral frame. Next, Fig. 1-
As shown in D, an adhesive sheet is placed on the inner layer circuit board. Further, an inner layer circuit board is arranged, and an adhesive sheet and a copper foil or a copper clad laminate on one side, a multilayer wiring board, a heat resistant sheet, etc. are arranged on both sides, and sandwiched between mirror plates. Thereafter, as shown in FIG. 1-E, heating and pressurization are performed to laminate and adhere. The heating and pressurizing means and conditions may be the same as conventional ones. As a result, the multilayer wiring board shown in FIG. 1-F can be manufactured.

【0007】[0007]

【作用】従来の、帯状の導体部を設ける方法による内層
回路板の寸法精度の低下や内層回路板の変形を、本発明
の内層回路板に設けた三角形状外周枠によって抑制し、
寸法精度を向上させパターン位置精度を向上させること
ができる。
With the triangular outer peripheral frame provided on the inner layer circuit board of the present invention, the dimensional accuracy of the inner layer circuit board and the deformation of the inner layer circuit board due to the conventional method of providing the strip-shaped conductor portion are suppressed.
It is possible to improve dimensional accuracy and pattern position accuracy.

【0008】[0008]

【実施例】実施例1 厚さ0.2mmのガラス布エポキシ樹脂銅張り積層板M
CL−E−67(日立化成工業株式会社製、商品名)両
表面にエッチングレジストを張り合わせる。回路パター
ンと外周部に三角形状外周枠パターンを配したネガフィ
ルムを用いてエッチングレジストにパターンニングを行
い、エッチングし、所望のパターンと三角形状外周導体
枠を内層板両表面に作成した。次に、内層回路板に0.
1mmのガラス布エポキシ樹脂プリプレグGE−67N
(日立化成工業株式会社製、商品名)を介した。さらに
次なる内層回路板を位置合わせし配した。この両側に接
着シート、さらに18ミクロン銅箔、鏡板を順次配し
た。これを成形温度170℃、形成圧力4MPaで90
分熱圧着し、板厚0.8mmの6層多層配線板を得た。
Example 1 Glass cloth epoxy resin copper-clad laminate M having a thickness of 0.2 mm
CL-E-67 (manufactured by Hitachi Chemical Co., Ltd., trade name) is laminated with etching resist on both surfaces. An etching resist was patterned using a negative film having a circuit pattern and a triangular outer peripheral frame pattern arranged on the outer peripheral portion, and etching was performed to form a desired pattern and a triangular outer peripheral conductor frame on both surfaces of the inner layer plate. Next, 0.
1mm glass cloth epoxy resin prepreg GE-67N
(Manufactured by Hitachi Chemical Co., Ltd., trade name). Furthermore, the next inner layer circuit board was aligned and arranged. An adhesive sheet, an 18-micron copper foil, and a mirror plate were sequentially arranged on both sides of this. 90 at a molding temperature of 170 ° C. and a forming pressure of 4 MPa
After thermocompression bonding, a 6-layer multilayer wiring board having a board thickness of 0.8 mm was obtained.

【0009】実施例2 実施例1の厚さ0.2mmのガラス布エポキシ樹脂銅張
り積層板に代え、厚さ0.1mmのガラス布エポキシ樹
脂銅張り積層板MCL−E−67(日立化成工業株式会
社製、商品名)を用い、他の方法は実施例1と同じ方法
で板厚0.6mmの6層多層配線板を得た。本発明方法
による実施例1、2での位置ずれ量を従来の方法と比較
して表1に示す。
Example 2 Instead of the 0.2 mm thick glass cloth epoxy resin copper clad laminate of Example 1, a 0.1 mm thick glass cloth epoxy resin copper clad laminate MCL-E-67 (Hitachi Chemical Co., Ltd.) was used. A 6-layer multilayer wiring board having a board thickness of 0.6 mm was obtained in the same manner as in Example 1 except that the product name was manufactured by Co., Ltd. Table 1 shows the positional deviation amounts in the first and second embodiments according to the method of the present invention in comparison with the conventional method.

【0010】[0010]

【表1】 [Table 1]

【0011】[0011]

【発明の効果】以上に説明したように、本発明の方法に
よって、位置ずれ量の少ない多層配線板の製造法を提供
することができる。
As described above, according to the method of the present invention, it is possible to provide a method for manufacturing a multilayer wiring board with a small amount of displacement.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す各製造過程の斜視図で
ある。
FIG. 1 is a perspective view of each manufacturing process showing an embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数枚の内層回路板を接着シートを介して
熱圧着形成する多層配線板の製造方法において、前記内
層回路板の回路形成する際、同時に内層回路外周部に三
角形状の導体部分を外周枠とし、配置することを特徴と
する多層配線板の製造方法。
1. A method for manufacturing a multilayer wiring board, which comprises thermocompression-bonding a plurality of inner-layer circuit boards through an adhesive sheet, and at the same time when forming a circuit of the inner-layer circuit boards, at the same time, a triangular conductor portion is provided on an outer peripheral portion of the inner-layer circuit. Is used as an outer peripheral frame, and is arranged.
JP9772793A 1993-04-23 1993-04-23 Manufacture of multilayer thin-film wiring substrate Pending JPH06310859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9772793A JPH06310859A (en) 1993-04-23 1993-04-23 Manufacture of multilayer thin-film wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9772793A JPH06310859A (en) 1993-04-23 1993-04-23 Manufacture of multilayer thin-film wiring substrate

Publications (1)

Publication Number Publication Date
JPH06310859A true JPH06310859A (en) 1994-11-04

Family

ID=14199926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9772793A Pending JPH06310859A (en) 1993-04-23 1993-04-23 Manufacture of multilayer thin-film wiring substrate

Country Status (1)

Country Link
JP (1) JPH06310859A (en)

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