JPH06310959A - Automatic gain control circuit - Google Patents

Abstract

PURPOSE:To obtain an automatic gain control circuit whose operation is made stable by controlling the operation of an AGC control counter with a run/stop instruction given to the AGC control counter. CONSTITUTION:A peak value 14 held by a sample-and-hold circuit 3 is inputted to comparators 5, 6, in which the peak value is compared respectively with reference values a15, b16. The result of comparison is inputted to a counter 7, which receives a step-up signal 17 from the comparator 5 and a step-down signal 18 from the comparator 6 to act as an up-counter. Furthermore, the counter 7 executes a reset operation when the counter 7 receives other combinations of the outputs of the comparators 5, 6. A run/stop control circuit 8 outputs a run instruction when the count of the counter 7 is 4 or over and outputs a stop instruction when the count is less than 4. The AGC control counter 9 makes amplification factor step revision to the amplifier 1 in the case of the run instruction with a run/stop instruction 19 of the circuit 8 and stops the step revision in the case of the stop instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit for waveform transmission for transmitting signals and the like.

[0002]

2. Description of the Related Art Conventionally, a communication signal is attenuated on a communication path in a data communication device, and the attenuation rate of this communication signal varies depending on the distance between communication devices and the signal cable. When amplifying the attenuated signal to a level at which data can be discriminated, the error occurrence rate at the time of data discrimination can be reduced by selecting the optimum amplification rate at the time of data reproduction. Therefore, in order to automatically control the optimum amplification factor, some data communication devices have an automatic gain control circuit.

The above-mentioned automatic gain control circuit detects the peak voltage of a signal to be reproduced within a certain period, changes the amplification factor of the amplifier by comparing the peak value and a reference value, and always amplifies to a level at which data can be identified. It is a circuit that controls the amplifier. The amplification factor of this automatic gain control circuit changes depending on the peak voltage of the signal, but the change of the amplification factor is digital. When the peak voltage exceeds a certain value, the amplification factor is lowered, and when it becomes lower than a certain value, the amplification factor is increased. In addition, the amplification factor exists in a step-like manner at certain intervals (see FIG. 5).

However, when the noise on the signal is detected as the peak voltage, the step of the amplification factor is determined by the peak voltage determined by the noise level. For example, when the true peak value of the signal shown in FIG. 5 is at the A level, it is appropriate that the amplification factor is B. However, if the peak value is A'due to the influence of noise, the amplification factor falls to B'and the automatic gain control circuit takes an unsuitable amplification factor for the signal.

Referring to FIG. 3, the conventional automatic gain control circuit includes an amplifier 31 for amplifying an input signal 41 and a peak value detection circuit 32 for detecting a peak value of an output signal 42.
A sample / hold circuit (S / H) 33 for holding a peak value 42, a frame generation circuit 34 for generating a frame signal 43, a comparator (CMP) 40 for comparing a peak value with a reference value 45, and an amplifier 31. And an AGC control counter 39 for instructing the amplification factor.

Here, the frame generation circuit 34 outputs the frame signal 43 at regular time intervals, and the peak value detection circuit 32.
The sample and hold circuit (S / H) 33 and the AGC control counter 39 are synchronized. Moreover, one frame is defined between the frame signals.

Next, a reproduced signal for explaining the operation of the conventional automatic gain control circuit is input to the amplifier 31. The signal 41 is amplified by the amplifier 31 at the amplification factor given to the amplifier 31 at that time, and output to a data identification circuit (not shown). The amplified signal 42 is also input to the peak value detection circuit 32. Peak value detection circuit 3
At 2, the peak value of the signal 42 is detected, and the sample / hold circuit 33 holds the peak value of the signal for one frame. At this time, the peak value detection circuit 32 is reset by the frame signal 43 and searches for the peak value of the next frame. The held peak voltage 44 is compared with the reference voltage value 45 by the comparator 40. Reference value 45 and peak value PP
An example of the relation of is shown in FIG.

The comparison result with the reference voltage value 45 depends on the relationship between the peak voltage and the reference voltage: peak voltage> reference voltage → reduce amplification factor (step down) peak voltage <reference voltage → increase amplification factor (step up) Is inputted to the AGC control counter 39 as an up / down signal 46 for controlling the above, and the counter value is increased / decreased in synchronization with the frame signal 43. The amplification factor of the step determined by the counter value of the AGC control counter 39 is instructed to the amplifier 31, and the amplifier 31 amplifies the signal with the amplification factor.

[0009]

However, referring to FIG. 6 which shows a timing chart of the frame signal and the step change control system signal, the automatic gain control circuit of this conventional example has a large difference in the amplitude level of the signal as a whole. However, since the peak value is always detected, noise on the signal is also detected as the peak value, and the step is changed. As a result, since the AGC control counter 9 does not perform the optimum amplification factor control for the signal, there is a high possibility that the data identification level does not match the signal and a data error occurs. That is, in the conventional peak value detection type automatic gain control circuit, when noise enters the signal and the peak value becomes larger than the actual signal, the inappropriate step is changed to match the actual signal at the time of data identification. However, there is a problem that an error occurs.

[0010]

SUMMARY OF THE INVENTION An automatic gain control circuit according to the present invention comprises an amplifier that variably amplifies an input signal according to a control signal, and a peak value detection that detects a peak voltage of an output signal of the amplifier at regular intervals. Circuit and a sample and hold circuit that holds the peak value of this peak value detection circuit for a certain period of time, and compares the peak voltage and the reference voltage within the certain period of this sample and hold circuit and outputs a step-up signal or step-down signal A comparator, an AGC control counter that outputs the control signal that controls a step according to the step-up signal and the step-down signal, a synchronization of the peak value detection circuit, the sample-hold circuit, and the AGC control counter. In an automatic gain control circuit having a frame generation circuit for generating a frame signal to be taken, The comparator has a first comparator that compares the peak voltage with a first reference voltage, and a second comparator that compares the peak voltage with a second reference voltage that is less than the first reference voltage value. A counter that counts a step-up signal output from the first comparator or a step-down signal output from the second comparator;
And a counter control circuit for instructing the operation and stop of the step change of the GC control counter.

Further, the automatic gain control circuit of the present invention may be arranged such that the counter is initialized by the number of steps of the AGC control counter at the time of reset.

[0012]

1 is a block diagram of an automatic gain control circuit according to a first embodiment of the present invention. The automatic gain control circuit according to this embodiment has an amplifier 1 for amplifying an input signal 11.
A peak value detection circuit 2 for detecting the peak value of the output signal 12, a sample and hold circuit (S / H) 3 for holding the peak value 12, a frame generation circuit 4 for generating a frame signal 13, and a peak value. First to compare the reference value a15
Comparator (CMP) 5 and peak value and reference value b1
A second comparator 6 for comparing 6 and a first and a second
The counter 7 that counts according to the outputs of the comparators 5 and 6, the run / stop control circuit 8 that outputs the run instruction 19 when the counter value 20 exceeds a predetermined value, and the run instruction 19 are issued. It is composed of an AGC control counter 9 which sometimes increases / decreases a count value according to the output of the first comparator 5. Further, the counter 7 holds the maximum value when it overflows.

Next, the operation of the automatic gain control circuit of this embodiment will be described.

The peak value 14 held by the sample and hold circuit 3 is input to the first comparator 5 and the second comparator 6. In the first comparator 5,
The peak value 14 is compared with the reference value a15. At the same time, the peak value 14 is also compared with the reference value b16 by the second comparator 6. The reference values a and b (15 to 16) are within the data discriminable range and are within ± of the desired peak voltage according to the input signal.
It is several percent (see FIG. 4B).

The comparison result of the peak voltage of the signal and the reference voltage is input to the counter 7 as data for each frame.
Further, when the counter 7 receives the step-up signal 17 from the first comparator 5 or the step-down signal 18 from the second comparator 6, it acts as an up-counter and outputs the force signals of the first and second comparators 5 and 6. When receiving any other combination, the operation is reset (counter value = 0).

FIG. 9 shows the truth values of the outputs (17, 18) of the first and second comparators 5, 6 and the counter input.

Referring to FIG. 9, the run / stop control circuit 8 outputs the following instruction to the AGC control counter 9 according to the value of the counter 7.

When the counter 7 is 4 or more, a run instruction is output. …
(1) When the counter 7 is less than 4, → stop command is output. …
(2) The run instruction / sto of this run / stop control circuit 8
The p command 19 causes the AGC control counter 9 to perform a step change operation of the amplification factor with respect to the amplifier 1 when it is a run command and stops the step change operation when it is a stop command.
An example of the operation of the counter 7 and the run / stop control circuit is shown in FIG.
Shown in.

Referring to FIG. 7 showing the operation of this embodiment for the same signal as in the conventional example, the automatic gain control circuit of the conventional example constantly changes the steps, but the automatic gain control circuit of the present embodiment causes noise. Since the step change is not performed due to the influence, the amplification rate step that does not match the actual signal data is not taken.

In the automatic gain control circuit of the first embodiment, the run / stop judgment value of the counter is set to 4,
Other values depending on the input signal are possible.

Next, an automatic gain control circuit according to the second embodiment of the present invention will be described.

Referring to FIG. 2, the automatic gain control circuit of the second embodiment of the present invention is the same as the automatic gain control circuit 9 of the first embodiment of the present invention when a run instruction 19 is issued. In addition to the configuration of the first embodiment, the AGC control counter 29 for increasing / decreasing the count value according to the output of the first comparator 5 and designating the initial value 21 of the counter 7 according to the amplification step number is used. The gain control circuit has the same structure as that of the gain control circuit, and the same components are designated by the same reference numerals. That is, in this embodiment, the amplifier 1 for amplifying the input signal 11, the peak value detection circuit 2 for detecting the peak value of the output signal 12, and the sample and hold circuit (S / H) 3 for holding the peak value 12 are provided. A frame generation circuit 4 for generating a frame signal 13, a first comparator (CMP) 5 for comparing a peak value with a reference value a15, a second comparator 6 for comparing a peak value with a reference value b16, a first comparator A counter 7 that counts in response to the outputs of the second comparators 5 and 6, and a run / s that outputs a run instruction 19 when the counter value 20 exceeds a predetermined value.
top control circuit 8.

Next, the operation of the automatic gain control circuit according to the second embodiment of the present invention will be described.

The difference between the operation of this embodiment and the operation of the first embodiment is that the initial value of the counter 7 is initialized as follows at the time of resetting by the amplification factor step number of the AGC control counter 29. .

Large amplification step → Large initial value → Small determination count number (3) During amplification step → Small initial value → Large determination count number (4) Small amplification step → Initial value Large → decision count number (5) That is, it is necessary to greatly change the amplification factor step of the amplifier 1 immediately after the start of communication by the initialization operations of (3), (4) and (5). In that case, the convergence of the amplification factor step can be accelerated.

[0026]

As described above, the automatic gain control circuit according to the present invention is provided with the run / value provided to the AGC control counter.
By controlling the operation of the AGC control counter with the stop instruction, the amplification factor change due to noise can be eliminated.

Therefore, there is an effect that the signal is stabilized at an appropriate amplification factor step and a data error can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an automatic gain control circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an automatic gain control circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional automatic gain control circuit.

FIG. 4 is a diagram for explaining a relationship between a reference value and a peak value. FIG. 4A is a diagram for explaining a case of a conventional example. FIG. 4B is a diagram for explaining a case of the first and second embodiments of the present invention. It is a figure.

FIG. 5 is a diagram illustrating an amplification factor step.

FIG. 6 is a timing diagram of step control system signals of a conventional automatic gain control circuit.

FIG. 7 is a timing chart of step control system signals of the automatic control circuit according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating operations of a counter 7 and a run / stop control circuit.

9 is a diagram showing a truth value of an input signal of the counter 7. FIG.

[Explanation of symbols]

 1, 31 Amplifier 2, 32 Peak value detection circuit 3, 33 Sample and hold circuit (S / H) 4, 34 Frame generation circuit 5, 6, 40 Comparator (CMP) 7 Counter 8 run / stop control circuit 9, 29, 39 AGC control counter 11,41 Input signal 12,42 Amplifier output 13,43 Frame signal 14,44 Input peak value signal 15,16 Reference voltage value 17 Step-up signal 18 Step-down signal 19 run / stop command 20 Counter value 21 Initial value of counter

Claims (2)

[Claims] 1. An amplifier that variably amplifies an input signal according to a control signal, a peak value detection circuit that detects a peak voltage of an output signal of the amplifier for each constant period, and a peak value of the peak value detection circuit that is constant. A sample-and-hold circuit that holds the period, a comparator that compares the peak voltage and the reference voltage within a fixed period of this sample-and-hold circuit and outputs a step-up signal or step-down signal, and the step-up signal and the step-down signal An AGC control counter for outputting the control signal for controlling the step, and a frame generation circuit for generating a frame signal for synchronizing the peak value detection circuit, the sample and hold circuit, and the AGC control counter. In the gain control circuit, the comparator controls the peak voltage and the first reference voltage. A first comparator that compares the voltage and a second comparator that compares the peak voltage with a second reference voltage that is less than the first reference voltage value. Step up of the output of the first comparator An automatic counter having a counter for counting a signal or a step-down signal output from a second comparator, and a counter control circuit for instructing the operation and stop of the step change of the AGC control counter according to the counter value of the counter. Gain control circuit. 2. The counter resets the AG when reset.
The automatic gain control circuit according to claim 1, wherein the automatic gain control circuit is initialized by the number of steps of a C control counter.