JPH06310992A - Display device for receiver - Google Patents

Abstract

PURPOSE:To simultaneously observe the signal intensity of plural frequencies, and to easily discover an empty channel by displaying the signal intensity of the plural frequencies, and shifting and changing the display position of the signal intensity corresponding to the change of a received frequency. CONSTITUTION:A received high frequency signal is inputted through both a changeover switch 10 and an RF amplifier 2 to a mixer 3, mixed with the signal of a local oscillator 4, and converted into an IF signal. The IF signal outputted from an IF amplifier 6 is detected by a detection circuit 19, A/D converted. and stored in an MPU 30 as signal level data SLD. Then, at the time of a receiving state on a search mode, while the frequency of the oscillator 4 is changed, level display data corresponding to the signal level data are written in a VRAM 40, and the low frequency signal of a wave to be modulated of the high frequency signal is displayed on an LCD 60 in order of the signal level. Also, the display position of the signal level can be shifted and changed corresponding to the change of the received frequency. Thus, the signal intensity can be simultaneously observed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device of a receiver for high frequency communication which displays signal strengths of a plurality of frequencies.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional radio receiver having a spectrum display function. In FIG. 2, a high frequency signal received by an antenna 100 is input to a mixer 102 via a high frequency amplifier (hereinafter referred to as an RF amplifier) 101, and then mixed with a local oscillation signal generated by a local oscillator 103. The frequency is converted into a predetermined intermediate frequency signal (hereinafter referred to as an IF signal). This IF signal is passed through an intermediate frequency amplifier (hereinafter referred to as IF amplifier) 104 to F
After being input to the M demodulator 105 and being FM demodulated, the demodulated low frequency signal is output to the speaker 107 via the low frequency amplifier (hereinafter referred to as AF amplifier) 106. The IF signal output from the IF amplifier 104 is envelope-detected by the detection circuit 108 and then output to the signal level meter 109, whereby the signal level of the received high-frequency signal is displayed on the signal level meter 109. To be done.

On the other hand, the IF signal is input to the mixer 110 and then mixed with the swept local oscillation signal generated by the swept local oscillator 111 with a predetermined sweep frequency width to form a swept IF signal having the above swept frequency width. Frequency converted.
This sweep IF signal is envelope-detected by the detection circuit 113 via the slope IF amplifier 112, and the detected signal is C
It is input to the vertical axis input terminal of the RT display 114. Further, the swept local oscillation signal output from the swept local oscillator 111 is input to a horizontal sweep signal generator 115 including a PLL circuit, and the generator 115 is a CRT display 114 synchronized with the input swept local oscillation signal. Generates a horizontal sweep signal for the CRT display 11
4 is input to the horizontal axis input terminal. This gives C
On the RT display 114, a frequency spectrum regarding the signal received by the antenna 100 is displayed in the above-mentioned predetermined sweep frequency width with the center frequency of the received high frequency signal as the center.

Therefore, the circuits and devices denoted by reference numerals 110 to 115 constitute a so-called spectrum analyzer for displaying the frequency spectrum, and the speaker 1 outputs the low frequency signal of the modulated wave contained in the received high frequency signal.
While listening at 07, it is possible to observe the frequency spectrum of the frequency of the high frequency signal and the signals of the frequencies in the vicinity thereof.

[0005]

However, in the conventional radio receiver with the spectrum display function, R
An original signal receiving circuit for receiving a high frequency signal of the first reception frequency from the F amplifier 101 to the IF amplifier 104;
The first and second reception frequencies are displayed with a reception circuit for displaying a spectrum of a high frequency signal of the swept second reception frequency including another local oscillator 111 from the RF amplifier 101 to the scope IF amplifier 112. Since the system has two receiving circuits for receiving, there is a problem that the circuit is complicated and the manufacturing cost is high. In the conventional radio receiver with spectrum display function,
Since the local oscillator 111 and the local oscillator 115 operate in cooperation with each other, it is possible to observe the signal strength of the frequency continuously adjacent to the output signal of the mixer 102, but it is possible to measure the signal strength of a plurality of frequencies set discretely. It was impossible to observe.

Further, in the receiver with the spectrum display function of the conventional example, when the reception frequency is changed, the reception position corresponding to the display position must be changed although the display position of the spectrum after the frequency change must be changed. Until the signal strength of the frequency is observed, there is a disadvantage that the signal strength of the frequency before the frequency change is displayed.

The object of the present invention is to solve the above problems, to display the signal strength of a plurality of frequencies, and to shift the display position of the signal strength of a plurality of frequencies in response to the change of the reception frequency. It is to provide a display device of a receiver that can be changed.

[0008]

According to a first aspect of the present invention, there is provided a display device for a receiver which receives a high frequency signal at a predetermined reception frequency, wherein the reception frequency is arbitrarily set. A detection storage unit that selectively switches in the switching order to detect and store the signal strengths of the plurality of received frequencies received, and a plurality of display units, and stores the signal strengths of the stored plurality of reception frequencies. Display means for displaying on the plurality of display units respectively corresponding to the switching order, and by shifting the signal strength of the plurality of reception frequencies stored in the detection storage means in response to the change of the reception frequency, And a control means for shifting the display position of the signal strength of the plurality of reception frequencies displayed on the display means.

According to a second aspect of the present invention, there is provided a receiver display device according to the first aspect, wherein the receiver storage device has a signal strength display function of a plurality of frequencies. It is characterized in that the reception frequency is switched in ascending order or descending order in terms of frequency.

[0010]

With the above construction, in the display device of the receiver according to claim 1, the detection storage means selectively switches the reception frequency in an arbitrarily set switching order to receive the signal. The plurality of received signal strengths of the received frequencies are detected and stored, and the display means displays the stored signal strengths of the plurality of received frequencies on the plurality of display units corresponding to the switching order. Further, the control means shifts the signal strengths of the plurality of reception frequencies stored in the detection storage means in response to the change of the reception frequency, whereby the signals of the plurality of reception frequencies displayed on the display means. Shift the display position of intensity. As a result, on the plurality of display portions of the display means, the signal intensities of the plurality of reception frequencies are respectively displayed in correspondence with the switching order, and the signal intensities of the plurality of frequencies are displayed in correspondence with the change of the reception frequency. The display position can be changed by shifting.

Further, in the display device of the receiver according to claim 2, the detection storage means switches the reception frequency in ascending or descending order at a predetermined step frequency. Thereby, in the plurality of display portions of the display means, the signal strengths of the plurality of reception frequencies correspond to the switching order,
That is, they are displayed side by side, for example, at the intervals of the above step frequencies. Further, the display positions of the signal intensities of the plurality of frequencies can be changed by shifting the step frequency by the step frequency in response to the change of the reception frequency.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an embodiment of the present invention "a radio transceiver with a signal level display function of a plurality of frequencies"
It is a block diagram of. The wireless transceiver of this embodiment has the following operation modes.

(A) VFO mode / memory channel mode "VFO mode" is an operation mode in which the transmission / reception frequency is set as follows. Rotary encoder 31
When setting the reception frequency fset = f _R by turning the dial, VFO (Variable Frequency Oscillator:. In this embodiment, specifically, to refer to the local oscillator 4) with said set reception frequency f A local oscillation signal having a local oscillation frequency f _L corresponding to _R is generated, and when the dial of the rotary encoder 31 is rotated clockwise, the local oscillation frequency f _L increases at each preset step frequency Δf. Direction, which changes the transmission / reception frequency f _R. In addition, the rotary encoder 31
When the dial of is rotated counterclockwise, the local oscillation frequency f _L changes in the descending direction for each preset step frequency Δf, which changes the transmission / reception frequency f _R. Alternatively, instead of using the dial of the rotary encoder 31, when a transmission / reception frequency is directly input using the ten-key pad 32, a local oscillation signal having a local oscillation frequency f _L corresponding to the input transmission / reception frequency f _R is input. was generated by a local oscillator 4, transmission and reception frequencies fset = f _R is set.

On the other hand, "memory channel mode"
Stores a plurality of transmission / reception frequencies in advance in the memory of the MPU 30 in association with each memory channel number, and designates one channel number by using the rotary encoder 31 or the numeric keypad 32, so that the transmission / reception frequency fset = f corresponding thereto is set. _This is the operation mode for setting _R.

(B) Normal Mode / Search Mode The "normal mode" is an operation mode for transmitting / receiving using the speaker 13 and the microphone 21 without displaying the level of signal strength of a plurality of frequencies. On the other hand, the “search mode” is an operation mode for displaying the signal levels of the reception signals of a plurality of frequencies on the matrix display portion 61 of the liquid crystal display device (hereinafter, referred to as LCD) 60. The level of signal strength is simply called the signal level.

(C) Receivable mode / Unreceivable mode An operation mode which is effective only when the search mode is set, and the "receivable mode" is an operation in which the speaker 13 can receive a reception signal. On the other hand, the “unreceivable mode” is an operation mode set so that the speaker 13 cannot receive a reception signal.

(D) Normal mode / scan search mode The "normal mode" is the same as the normal mode described in (c) above, and does not display the level of the signal strength of a plurality of frequencies.
This is an operation mode for transmitting and receiving using the speaker 13 and the microphone 21. On the other hand, the "scan search mode" is the operation mode for displaying the signal levels of the reception signals of a plurality of frequencies on the matrix display section 61 of the LCD 60. For each step frequency set using 33, the direction in which the frequency increases automatically (hereinafter,
Upward. ) Or changing to a lower direction (hereinafter referred to as a downward direction) in the “scan search mode”.
Is repeated until it is canceled, thereby shifting the signal level data of the received signals of a plurality of frequencies stored in the VRAM 40 in response to the change of the transmission / reception frequency, and thereby the plurality of frequencies of the matrix display unit 61 of the LCD 60 are changed. The display position of the signal level of the received signal is sequentially shifted in the upward or downward direction of the frequency and displayed. When setting the scan search mode in the upward direction,
Normal mode / scan search mode selector switch SW5
After turning on, the rotary encoder (hereinafter abbreviated as RE in the drawing) 31 is turned clockwise (when the frequency is upward) or counterclockwise (when the frequency is downward) when viewed from above. Hereinafter, the rotation direction of the rotary encoder 31 is indicated by the rotation direction viewed from above.

The radio transceiver with a signal level display function for a plurality of frequencies according to the present embodiment has an I output from the IF amplifier 6.
After the F signal is detected by the detection circuit 19, analog /
A digital converter (hereinafter referred to as A / D converter) 20 converts the converted data into digital data, and the converted data is taken into a microprocessing unit (hereinafter referred to as MPU) 30 as signal level data SLD.
In the search mode and in the receiving state, the signal level data SLD is fetched while sequentially changing the local oscillation frequency f _L of the local oscillator 4, and the level display data corresponding to the signal level data SLD is written into the VRAM 40, whereby the transmission / reception frequency f _R While listening to and receiving the low frequency signal of the modulated wave of the high frequency signal through the speaker 13, the matrix display unit 61 of the LCD 60 displays the signal levels of a plurality of frequencies centered on the signal level of the transmission / reception frequency f _R. And

Here, in the VFO mode and the search mode, the LCD 6 when displaying the signal levels of a plurality of frequencies
The horizontal step frequency of 0 is the step frequency Δf of the VFO mode preset in the wireless transceiver.
In the present embodiment, the frequency (f _R −3Δ
f), frequency (f _R -2Δf), frequency (f _R -Δf),
Transmission / reception frequency f _R , frequency (f _R + Δf), frequency (f _R
It is characterized in that each signal level of + 2Δf) and frequency (f _R + 3Δf) is displayed. On the other hand, in the memory channel mode and the search mode, when the currently set channel is the channel number m, in the present embodiment, the channel number (m-3) from the left toward the matrix display portion 61 of the LCD 60. Frequency of
Channel number (m-2) frequency, channel number (m-1) frequency, channel number m frequency, channel number (m + 1) frequency, channel number (m +
Each of the signal levels of the frequency 2) and the channel number (m + 3) is displayed.

Further, in the reception state, in the search mode, as described above, the matrix display section 61 of the LCD 60 displays the signal levels of a plurality of frequencies indicating the signal levels of the high frequency signals of seven frequencies which change in the vertical direction. In the normal mode, the pixel level of the high-frequency signal being received, which changes in the horizontal direction, is displayed using the lowermost 2 rows and 7 columns of the matrix display portion 61.

Further, the transceiver of this embodiment sets the transmission / reception frequency by setting the scan search mode.
Automatically changing the frequency upward or downward for each step frequency set by using the step frequency selection key 33 is repeated until the scan search mode is released, whereby the plurality of frequencies in the VRAM 40 are changed. By shifting the data of the signal level of the received signal, the display position of the signal level of the received signal of a plurality of frequencies can be sequentially shifted in the upward or downward direction of the frequency in response to the change in the transmission / reception frequency. It has a feature. In this scan search mode, when the transmission / reception frequency is changed upward, the signal level of the transmission / reception frequency is displayed in FIG.
After being shifted to the right end of the matrix liquid crystal display unit 61 indicated by 3b, the transmission / reception frequency is sequentially scanned in the upward direction, so that the display position of the corresponding signal level is left as shown in FIG. Are sequentially shifted in the direction. On the other hand, when changing to the downward direction, the display of the signal level of the transmission / reception frequency is shifted so as to be located at the left end of the matrix liquid crystal display unit 61 indicated by the center indicating liquid crystal display unit 63c in FIG. Since the frequency is sequentially scanned downward, the display position of the signal level corresponding to the frequency is sequentially shifted to the right as shown in FIG.

Further, in the transceiver of the present embodiment, when the rotary encoder 31 is rotated clockwise or counterclockwise in the VFO mode and the search mode, its rotation frequency (the rotary encoder 31 is about A clip point exists every 30 °, and the rotation frequency increases each time the clip point is passed.) The transmission / reception frequency is changed by shifting the transmission frequency upward or downward, and stored in the VRAM 40 accordingly. By shifting the data of the signal levels of the received signals of a plurality of frequencies in the above-described search mode, the matrix display unit 61 of the LCD 60 is
The display positions of the signal levels of the received signals of a plurality of frequencies are shifted and displayed. This behavior
The above-mentioned "scan search mode" that is automatically performed is called a manual scan search.

First, the configuration of the wireless transceiver having the signal level display function for a plurality of frequencies shown in FIG. 1 will be described.

In FIG. 1, in the receiving state, the high frequency signal received by the antenna 100 is input to the mixer 3 via the common terminal c of the transmission / reception changeover switch 10 and its contact point a, and further via the RF amplifier 2 to be locally supplied. An _IF signal mixed with a local oscillation signal having a local oscillation frequency f _L generated by the oscillator 4 and having a predetermined intermediate frequency f _IF (in this embodiment, f _IF = f _R −f _L is set). After being frequency-converted to, the signal is input to a limiter amplifier 7 and a detection circuit 19 via a bandpass filter (BPF) 5 that passes only the IF signal and an IF amplifier 6. here,
The local oscillator 4 includes a PLL circuit, and generates a local oscillation signal having a local oscillation frequency f _L based on the local oscillation frequency data Df _L output from the MPU 30 and outputs it to the mixer 3 and the mixer 24. Further, the transmission / reception changeover switch 10 is selectively changed over to a contact a side or a contact b side based on a transmission / reception changeover signal (hereinafter referred to as a TRSW signal) output from the MPU 30. Where TRS
When the W signal is at the L level (in the flowchart, it is indicated by the control data "0" in the MPU 30), the changeover switch 10 is changed over to the contact a side, and the wireless transceiver becomes the receiving state. When it is at the H level (in the flowchart, it is indicated by the control data "1" in the MPU 30), the changeover switch 10 is changed over to the contact b side, and the wireless transceiver becomes the transmitting state.

The IF signal input to the detection circuit 19 is envelope-detected and then converted into digital data by the A / D converter 20, and the signal level data SLD proportional to the signal level of the received high frequency signal is MPU 30. Is input and captured. On the other hand, the limiter amplifier 7 limits the amplitude of the input IF signal to a predetermined amplitude level and then
Output to the demodulator 8. The FM demodulator 8 FM demodulates the input IF signal to take out the low frequency signal of the modulated wave,
Low pass filter (LPF) 9 and squelch switch 11
And to the speaker 13 via the AF amplifier 12.
A signal output from the FM demodulator 8 and having a frequency higher than the low frequency signal including triangular noise is detected by a detection circuit 17 via a high pass filter (HPF) 14, a squelch adjusting attenuator 15 and a noise amplifier 16. Entered in. The detection circuit 17 detects the noise component output from the FM demodulator 8 and outputs it to the waveform shaping circuit 18.

The waveform shaping circuit 18 detects the signal of the modulated wave to be received when the noise component is equal to or higher than the threshold level by comparing the input noise component with a predetermined threshold level. When it is determined that the squelch switch 11 is not possible, an SD (signal detection) signal of H level is output to the control terminal of the squelch switch 11 as a squelch signal (hereinafter referred to as an SQ signal) via the first input terminal of the OR gate OR1. The squelch switch 11 is turned off to prevent the low frequency signal after FM demodulation from being output from the speaker 13. The SD signal output from the waveform shaping circuit 18 is also input to the MPU 30. on the other hand,
When the noise component is below the threshold level, the waveform shaping circuit 18 determines that the noise component is sufficiently low and controls the SD signal of L level to control the squelch switch 11 via the first input terminal of the OR gate OR1. The low frequency signal after FM demodulation is output from the speaker 13 by outputting to the terminal and turning on the squelch switch 11. further,
The MPU 30 controls the squelch switch 11 via a second input terminal of the OR gate OR1 with an H level forced squelch signal (hereinafter referred to as an ESQ signal) for forcibly turning off the squelch switch 11, as described later. Output to the terminal.

In the flow chart, the H-level ESQ signal is indicated by the control data "1" in the MPU 30, and the L-level ESQ signal is indicated by the control data "0" in the MPU 30. The same applies to the H-level SD signal.

On the other hand, in the transmitting state, the microphone 21
The audio signal input to is input to the FM modulator 23 via the AF amplifier 22, and then the FM modulator 23 converts the carrier signal of the IF signal having the predetermined intermediate frequency f _IF into the input audio signal. FM-modulates, outputs the FM-modulated IF signal to the mixer 24, and the mixer 24 outputs the input IF signal.
The signal and the local oscillation signal are mixed to generate a high-frequency transmission signal equal to the frequency f _R and output to the antenna 1 via the power amplifier 25, the contact b of the transmission / reception changeover switch 10 and the common terminal c. , Emits the transmission signal.

The MPU 30 is a control circuit for controlling the overall operation of the radio transceiver and the display operation of the LCD 60, and includes a CPU for performing control and calculation, a control program, and data necessary for executing the control program. R that stores
An OM and a RAM, which is used as a work area when the control program is executed and stores current data of various signals and flags, are provided. Also, the MPU3
0 is a rotary encoder 31 for setting the transmission / reception frequency and the memory channel number by rotating the knob.
And a transmission / reception frequency and a memory channel number are directly input, and a standby process described later (step S246)
The ten key 32 for setting various controls such as the waiting time Tw seconds in FIG. Here, the transmission / reception frequency set by the rotary encoder 31 or the numeric keypad 32 is set as set frequency data fset and stored in the RAM in the MPU 30. Further, the waiting time Tw seconds is also set by the ten keys 32 and then stored in the RAM in the MPU 30 in the same manner.

Further, in the MPU 30, the step frequency Δf, which is the frequency of the change step of the transmission / reception frequency in the VFO mode, is set to, for example, 1 kHz, 5 kHz, 10 k.
The step frequency setting key 33 for selectively setting one of Hz, 20 kHz and 25 kHz is connected, and the data of the step frequency Δf set by the key 33 is MP.
Input to U30. The other end of the frequency change unit changeover switch 34, one end of which is connected to the ground, is connected to the MPU 30, and each time the switch 34 is turned on, the rotary encoder 31 is used to change the unit for changing the transmission / reception frequency. The step frequency Δf selected by the selection key 33 and 1 MHz are selectively changed and set.

Furthermore, the MPU 30 is connected to the ground via the following four switches. (A) PTT (Push To Talk) switch SW1: A switch for setting the wireless transceiver to a transmission state and transmitting an audio signal, which is in a transmission state when turned on. (B) VFO mode / memory channel mode switch SW2: This switch selectively switches between the VFO mode and the memory channel mode, and the VFO mode and the memory channel mode are alternately switched every time the switch is turned on. (C) Normal mode / search mode switch SW
3: A switch for selectively switching between the normal mode and the search mode, and the normal mode and the search mode are alternately switched every time the switch is turned on. (D) Receivable mode / unreceivable mode changeover switch SW4: a switch that is effective only in the search mode, and is a switch that selectively switches between the receivable mode and the unreceivable mode. The enable mode and the unreceivable mode are switched alternately. (E) Normal mode / scan search mode switch SW5: This switch selectively switches between the normal mode and the scan search mode, and the normal mode and the scan search mode are switched alternately each time the switch is turned on.

FIG. 3 is a front view when all the liquid crystal pixels are displayed on the LCD 60. As shown in FIG. 3, a matrix display unit in which liquid crystal pixels LM00 to LM63 (see FIG. 4), which are rectangular liquid crystal pixels and have a matrix shape of 4 rows and 7 columns, are arranged in the upper central portion of the LCD 60. 61 are provided, and display positions and reference levels at the time of displaying signal levels of a plurality of frequencies each having a horizontal line shape in the vicinity of immediately below each liquid crystal pixel LM00-LM60 in the lowermost row of the matrix display section 61. Is provided for the reference indicating liquid crystal pixel. On the other hand, near the upper side of the liquid crystal pixel LM33 in the upper center of the matrix display section 61, a center indicating liquid crystal display section 63a for constant display having a downward arrow shape is provided. Also, on the left side of the matrix display section 61, it is indicated that the level indicated by the matrix display section 61 in the normal mode is the reception signal level (in the reception state) or the transmission signal level (in the transmission state) "S / The “RF” liquid crystal display portion 64 is formed,
Also, an "M" liquid crystal display portion 65 indicating the memory channel mode is formed immediately below it, and a three-digit 7-segment liquid crystal display portion 66 indicating the memory channel in the memory channel mode is formed immediately below it. further,
A 5-digit 7-segment liquid crystal display portion 67 indicating the transmission / reception frequency f _R is formed in the lower right portion of the LCD 60, and the liquid crystal display portion 67 has a decimal point between the second digit and the third digit.

The VRAM 40 is connected to the MPU 30,
A video RAM that stores 28 pixel data to be displayed on the matrix display unit 61, and an output terminal of the VRAM 40 is connected to the matrix display unit 61 of the LCD 60 via the LCD driver 50. Therefore, the VRAM 40
When the pixel data is stored in, the LCD driver 50 displays the liquid crystal in real time on the matrix display unit 61 in accordance with the stored pixel data. FIG. 4 shows a liquid crystal pixel of the matrix display unit 60 of the LCD of FIG. 3 and a V for storing pixel data.
It is a front view showing the relationship with the address of RAM40. As shown in FIG. 4, 28 liquid crystal pixels LM00-LM63
Addresses "00"-"63" are given to each of the four-digit two-digit display.

The register 41 is connected to the MPU 41,
A 2-bit register for storing 2-bit pixel data Dsm for displaying the liquid crystal display units 64 and 65,
The output terminal of the register 41 is connected to the liquid crystal display units 64 and 65 of the LCD 60 via the LCD driver 51. Therefore, when the pixel data Dsm is stored in the register 41, the LCD driver 51 accordingly displays the liquid crystal on the liquid crystal display units 64 and 65. Here, the pixel data D
The first bit of sm is data indicating whether to display the liquid crystal display unit 64, and the second bit of pixel data Dsm is data indicating whether to display the liquid crystal display unit 65.

The register 42 is connected to the MPU 41,
A register 42 for storing the memory channel number data Dm for displaying the liquid crystal display 66.
The output terminal of is connected to the liquid crystal display unit 66 of the LCD 60 via the LCD driver 52. Therefore, when the pixel data Dm is stored in the register 42, the LCD
A liquid crystal display is displayed on the liquid crystal display unit 66 by the driver 52. Further, the register 43 is connected to the MPU 41 and is used for transmitting / receiving frequency data Df for displaying the liquid crystal display 67.
A register for storing _CL, and an output terminal of the register 43 is connected to the liquid crystal display unit 67 of the LCD 60 via the LCD driver 52. Therefore, when the pixel data Df _CL is stored in the register 43, the LCD driver 53 accordingly displays the liquid crystal on the liquid crystal display unit 67.

The register 44 is connected to the MPU 41,
This is a 2-bit register for storing 2-bit pixel data Dcm for displaying the center indicating liquid crystal display portions 63a, 63b, 63c, and the output terminal of the register 44 is L.
The liquid crystal display 63 of the LCD 60 via the CD driver 54
a, 63b, 63c. Therefore, register 4
4 when the pixel data Dcm is stored, the liquid crystal display portions 63a, 63
A liquid crystal display is displayed at b and 63c. Here, the pixel data Dc
When m is "00", only the liquid crystal display section 63a that indicates the center of the matrix liquid crystal display section 61 is displayed, and when the pixel data Dcm is "01", the matrix liquid crystal display section 61 is displayed.
Only the liquid crystal display portion 63b indicating the right end of the matrix liquid crystal display portion 63c is displayed, and when the pixel data Dcm is "10", only the liquid crystal display portion 63c indicating the left end of the matrix liquid crystal display portion 61 is displayed.

The various flags stored in the RAM in the MPU 30 are as follows. (A) FS2: FS2 = 0 in the VFO mode,
In the memory channel mode, FS2 = 1. (B) FS3: FS3 = 0 in the normal mode, and FS3 = 1 in the search mode. (C) FS4: FS4 = 0 in the receivable mode, and FS3 = 1 in the unreceivable mode. (D) FS5: FS5 = 0 in the normal mode, and FS5 = 1 in the scan search mode. (E) FS5S: a flag indicating the start of scan search, which is set to 1 when the scan search mode is disclosed and after the matrix liquid crystal display section 61 is all turned off in step S406, step S40
It is reset to 0 at 7 (f) FUP: Set to 1 when the rotary encoder 31 is rotated clockwise to automatically or manually scan the transmission / reception frequency upward, while the transmission / reception frequency is lowered. 0 when the rotary encoder 31 is rotated counterclockwise to automatically or manually scan the direction
Is reset to.

FIG. 9 is a flowchart of the main routine executed by the CPU of the wireless transceiver of FIG.

As shown in FIG. 9, in step S1, initialization processing is first performed. That is, the TRSW signal of L level is output to enter the reception state, and (433M
The frequency of (Hz-f _IF ) is set as the local oscillation frequency data Df _L. In addition, each flag FS2, FS3, FS
4, FS5, FS5S are reset to 0 and flag F
When UP is set to 1, the L-level ESQ signal is output, and "10" is set and stored in the pixel data Dsm. Next, after the key input processing (see FIGS. 10 and 11) is executed in step S2, it is determined in step S3 whether the flag FS2 is 1 or not. If FS2 = 1, the memory channel mode process is executed in step S4, and then the process returns to step S2. On the other hand, when FS2 = 0, step S5
After the VFO mode processing (see FIG. 12) is executed in step S2, the process returns to step S2.

FIG. 10 and FIG. 11 are flowcharts of the key input process (step S2) subroutine of FIG. b)
Flag FS3 from step S31 to step S34
Setting process of (c) step S61 to step S6
Setting process of the flag FS5 up to 5 and (d) step S
Setting process of the flag FS4 from 40 to step S46 (excluding step S45), and (e) step S
45 frequency data setting process, and (f) step S5
Rotary encoder 31 from 1 to step S54
And the other key input processing in step S55 (g).

As shown in FIG. 10, in step S21, it is determined whether or not the switch SW2 is turned on. If not, the process proceeds to step S31. If it is turned on, the flag FS2 is 1 in step S22. It is determined whether or not. Here, when the flag FS2 = 1, the flag FS2 is reset to 0 in step S23 and then the process proceeds to step S31, while the flag FS2 =
When it is 0, the flag FS2 is set to 1 in step S24, and then the process proceeds to step S31.

Next, in step S31, it is determined whether or not the switch SW3 is turned on. When it is not turned on, the process proceeds to step S40. When it is turned on, it is determined in step S32 whether the flag FS3 is 1 or not. To be done. When the flag FS3 = 1, the flag FS3 is reset to 0 in step S33 and then the process proceeds to step S40. When the flag FS3 = 0, the flag FS3 is set to 1 in step S34 and the process proceeds to step S40.

Next, in step S61, it is determined whether or not the switch SW5 is turned on. When it is not turned on, the process proceeds to step S40 in FIG. 11. On the other hand, when it is turned on, the flag FS5 is 1 in step S62. Is determined. Here, when the flag FS5 = 1, the flag FS5 is reset to 0 in step S63, and then the process proceeds to step S40 in FIG. On the other hand, when the flag FS5 = 0 in step S62, step S6
After the flags FS5 and FS5S are both set to 1 in S4 and S65, the process proceeds to step S40 in FIG.

Next, in step S40, the flag F
It is determined whether or not S3 is 1, and it is determined at step S46 whether or not the flag FS5 is 1. That is, these judgments are made in order to validate the processing of steps S41 to S44 only in the search mode or the scan search mode. Therefore, FS3 = 1 or FS5 = 1
If so, the process proceeds to step S41, while FS3 = 0 and FS
When 5 = 1, the process proceeds to step S51. Further, in step S41, it is determined whether or not the switch SW4 is turned on. If not, the process proceeds to step S51, while if turned on, the flag F is set in step S42.
It is determined whether or not S4 is 1. Here, flag F
When S4 = 1, the flag FS4 is reset to 0 in step S43 and then the process proceeds to step S51, while when flag FS4 = 0, the flag FS is calculated in step S44.
After 4 is set to 1, the process proceeds to step S51.

Next, in step S45, the set frequency data fset set by using the rotary encoder 31 or the numeric keypad 32 is transmitted / received frequency data Df _CL.
It is set as, set frequency data (Df _CL -f _IF) as the local oscillation frequency data Df _L, the local oscillation frequency data Df _L center local oscillation frequency data Df _LO
Is set as.

Next, in step S51, it is determined whether or not the rotary encoder 31 has been rotated clockwise, and if it has been rotated clockwise, both flags FUP and FS5S are set to 1 in step S52, and the flow proceeds to step S53. . On the other hand, if NO in step S51, the process directly proceeds to step S53. Next, in step S53, it is determined whether or not the rotary encoder 31 is rotated counterclockwise. If it is rotated counterclockwise, the flag FUP is reset to 0 in step S54, and the flag FS5S is set to 1 in step S5.
Go to 5. On the other hand, if NO in step S53, the process directly proceeds to step S55. Furthermore, step S55
In, input processing is executed for other keys such as setting the waiting time Tw seconds using the ten-key pad 32, setting using the step frequency selection key 33, and setting using the frequency change unit changeover switch 34.

FIG. 12 is a flow chart of a subroutine of the VFO mode process (step S5) of FIG.

As shown in FIG. 12, it is determined in step S11 whether the flag FS3 is 1, and in step S90 it is determined whether the flag FS5 is 1. When FS3 = 0 and FS5 = 0, neither the search mode nor the scan search mode, so the process proceeds to step S96. When FS3 = 1, the search mode occurs, so the process proceeds to step S91. When FS5 = 1 Since it is the scan search mode, step S9
Go to 4. In step S96, the pixel data Dsm
Data “10” is stored in the LCD and “S / RF” is displayed on the LCD 60.
The liquid crystal pixels of the liquid crystal display unit 64 are displayed and the pixel data Dc is displayed.
"00" is stored in m, the liquid crystal pixel of the center instruction liquid crystal display portion 63a is displayed on the LCD 60, and then step S
After executing the normal process (see FIG. 13) in 13, the process returns.

In step S91, the pixel data D
Data “00” is stored in sm and liquid crystal display units 64, 65
The liquid crystal is not displayed on the LCD, and "00" is stored in the pixel data Dcm to display the liquid crystal pixel of the center instruction liquid crystal display unit 63a on the LCD 60, and the process proceeds to step S92. Next, in step S92, it is determined whether or not the flag FS4 is 1, and when FS4 = 0, search receivable processing (see FIGS. 14 to 16) is executed, and then step S93.
Proceed to. On the other hand, when FS4 = 1, step S14
After executing the search unreceivability process in step S9, the process proceeds to step S93. In step S93, the display changing process (see FIG. 17) which is the process of the manual scan search is executed, and the process returns.

In step S94, the pixel data D
Data “00” is stored in sm and liquid crystal display units 64, 65
No liquid crystal is displayed on the screen, and the process proceeds to step S95. Next, in step S95, it is determined whether or not the flag FS4 is 1, and when FS4 = 0, the scan search receivable process (see FIGS. 14 to 16) is executed, and then the process returns. On the other hand, when FS4 = 1, step S1
After executing the search unreceivability processing in 4, return

FIG. 13 is a flow chart of a subroutine of the normal process (step S13) of FIG. Figure 1
As shown in FIG. 3, first, in step S101, PT
It is determined whether the T switch SW1 is turned on,
When it is turned on, the process proceeds to step S102, the TRSW signal of H level is output, and the transmission / reception changeover switch 10
Is switched to the contact b side to set the transmission state, and then the process returns. On the other hand, when the PTT switch SW1 is not turned on (NO in step S101), step S1
At 03, an L level TRSW signal is output to switch the transmission / reception changeover switch 10 to the contact a side to bring it into a receiving state, and then at step S104, the A / D converter 20
The received signal level data SLD output from is detected and fetched, and the data SLD is set to 7 in step S105.
After converting to level data, the converted data is converted into address 0 of VRAM 40 in step S106.
0, 01, 10, 11, ..., 60, 61 and updated to store 14 liquid crystal pixels LM00, LM01, L for the two lowermost rows of the matrix display section 61 of the LCD 60.
M10, LM11, LM20, LM21, LM30, L
M31, LM40, LM41, LM50, LM51, L
Using M60 and LM61, the left end is set to 0/7 level, two lines are simultaneously displayed, the signal level is displayed in the horizontal direction, and the process returns.

For example, when the signal level is 4/7, as shown in FIG. 6, liquid crystal pixels LM00, LM01, LM1.
0, LM11, LM20, LM21, LM30, LM3
When 1 is displayed and the signal level is 7/7, liquid crystal pixels LM00, LM01, LM10, L for all two rows are displayed.
M11, LM20, LM21, LM30, LM31, L
M40, LM41, LM50, LM51, LM60, L
When M61 is displayed and the signal level is 1/7, the liquid crystal pixels LM00 and LM01 are displayed.

Although a detailed description is omitted, in the normal process and other processes, the output level of the power amplifier 25 is detected in the transmission state and the same as in the reception state.
14 liquid crystal pixels LM00, LM01, LM10 for the two rows at the bottom of the matrix display section 61 of the LCD 60.
LM11, LM20, LM21, LM30, LM31,
LM40, LM41, LM50, LM51, LM60,
The LM 61 is used to display the transmission signal level in the horizontal direction by setting the left end to level 0 and simultaneously displaying two lines.

14 to 16 are flowcharts of the subroutine of the search receivable processing of FIG.

As shown in FIG. 14, first, step S2
In 01, it is determined whether or not the PTT switch SW1 is turned on, and when it is turned on, step S202
Then, the H-level TRSW signal is output to switch the transmission / reception changeover switch 10 to the contact b side to put it in the transmission state, and then the process returns. On the other hand, when the PTT switch SW1 is not turned on (N in step S201)
O), in step S203, the L level TRSW signal is output to switch the transmission / reception changeover switch 10 to the contact a side to bring it into the receiving state, and in step S204, the H level ESQ signal is output to output the squelch switch 1
1 is turned off, and the output of the low frequency signal to the speaker 13 is stopped.

Next, in step S211, the frequency data (Df _LO -3Δf) is converted into the local oscillation frequency data Df.
_The received signal level data SLD output from the A / D converter 20 is detected and fetched in step S212, and the data SL is set in step S213.
After converting D into 4-level data, step S214
In the above, the converted data is stored and updated in the address 00-03 of the VRAM 40, and four liquid crystal pixels LM00 for one column of the matrix display section 61 of the LCD 60 are stored.
-Using LM03, the signal level is displayed in the vertical direction with the lower end at the 0/4 level, as shown in FIG. 5, for example. Here, for example, when the signal level is 4/4, all four liquid crystal pixels LM00-LM03 are displayed in liquid crystal, and when the signal level is 2/4, the two liquid crystal pixels LM00-LM0 are displayed.
1 is displayed on the liquid crystal display.

Next, in step S221, the frequency data (Df _LO -2Δf) is converted into the local oscillation frequency data Df.
_The received signal level data SLD output from the A / D converter 20 is detected and fetched in step S222, and the data SL is set in step S223.
After converting D into 4-level data, step S224
The converted data is stored and updated in the addresses 10-13 of the VRAM 40 at 4 and the four liquid crystal pixels LM10 for one column of the matrix display section 61 of the LCD 60.
-Using LM13, display the signal level in the vertical direction with the lower end at 0/4 level.

Then, in step S231, the frequency data (Df _LO -Δf) is converted into the local oscillation frequency data Df _L.
, The received signal level data SLD output from the A / D converter 20 is detected and taken in in step S232, and the data SLD is received in step S233.
Is converted into four-level data, the converted data is stored and updated in addresses 20-23 of the VRAM 40 in step S234, and four liquid crystal pixels LM20 for one column of the matrix display section 61 of the LCD 60 are stored. −
The LM 23 is used to display the signal level in the vertical direction with the lower end at the 0/4 level, and the process proceeds to step S240 in FIG.

As shown in FIG. 15, in step S240, the L-level ESQ signal is output, the squelch switch 11 is turned off, and the low-frequency signal of the modulated wave of the received signal can be received using the speaker 13. In addition, the clocking time Twp of the clocking timer (not shown) in the MPU 30 for standby processing is reset to 0 seconds to start clocking. Next, after the central local oscillation frequency data Df _LO is set to the local oscillation frequency data Df _L in step S241, the process proceeds to step S242. In step S242, the received signal level data SLD output from the A / D converter 20 is detected and fetched, and step S24
After converting the data SLD into 4-level data in 3, the converted data is stored and updated in the addresses 30-33 of the VRAM 40 in step S244, and the 1 of the central portion of the matrix display portion 61 of the LCD 60 is updated.
The four liquid crystal pixels LM30 to LM33 for columns are used to display the signal level in the vertical direction with the lower end at the 0/4 level, and it is determined in step S245 whether the SD signal is at the H level. When the SD signal is at the H level, that is, when there is no signal at the reception frequency, the process proceeds to step S250 of FIG. 16 without executing the waiting time determination process of step S246. On the other hand, when the SD signal is at the L level in step S245, that is, when there is a signal at the reception frequency, step S2
At 46, the waiting time for the waiting process is determined.
That is, it is determined whether the time count Twp of the time count timer has passed the preset standby time Tw. When the time has not passed, the process returns to step S246 and the level detection display process of the reception frequency is executed while executing the standby process. On the other hand, if it has elapsed, the process proceeds to step S250 in FIG. The signal level displayed in step S244 indicates the signal level of the signal currently being received. In the loop processing of returning from step S246 to step S246 through step S242, while detecting and displaying the signal level of the received signal in real time at a predetermined cycle,
Moreover, since the squelch switch 11 is on, it is possible to receive the received signal of the set transmission / reception frequency f _R = fset = Df _CL and to hear the low frequency signal of the modulated wave through the speaker 13. The present invention is not limited to this, and the step S
In 246, the judgment of the waiting time may not be executed, and the waiting time may be Tw seconds, for example. in this case,
The signal level currently received does not change in real time.

As shown in FIG. 16, in step S250, the H level ESQ signal is output to turn off the squelch switch 11, and the output of the low frequency signal to the speaker 13 is stopped. Next, in step S251, the frequency data (Df _LO + Δf) is set to the local oscillation frequency data Df _L.
, The received signal level data SLD output from the A / D converter 20 is detected and captured in step S252, and the data SLD is detected in step S253.
Is converted into 4-level data, and the converted data is stored and updated in addresses 40-43 of the VRAM 40 in step S254, and four liquid crystal pixels LM40 for one column of the matrix display section 61 of the LCD 60 are stored. −
The LM 43 is used to display the signal level in the vertical direction with the lower end at the 0/4 level.

Next, in step S261, the frequency data (Df _LO + 2Δf) is converted into the local oscillation frequency data Df.
_The received signal level data SLD output from the A / D converter 20 is detected and fetched in step S262, and data SL is set in step S263.
After converting D into 4-level data, step S264
The converted data is stored and updated in the addresses 50-53 of the VRAM 40 at 4 and the four liquid crystal pixels LM50 for one column of the matrix display section 61 of the LCD 60.
-Using LM53, display the signal level in the vertical direction with the lower end at 0/4 level.

Next, in step S271, the frequency data (Df _LO + 3Δf) is converted into the local oscillation frequency data Df.
_It is set as _L , the reception signal level data SLD output from the A / D converter 20 is detected and taken in at step S272, and the data SL is sent at step S273.
After converting D into 4-level data, step S274
At step 60, the converted data is stored and updated in addresses 60-63 of the VRAM 40, and four liquid crystal pixels LM60 for one column of the matrix display section 61 of the LCD 60 are stored.
-Using LM63, display the signal level in the vertical direction with the lower end at 0/4 level.

The search unreceivability process (step S15) of FIG. 12 is shown in FIGS. 14 to 16 except that the ESQ signal of H level instead of L level is output in step S240 of FIG. This is similar to the search receivable process (step S14). As a result, in the search mode and the unreceivable mode, the signal levels of a plurality of frequencies are displayed as in the search receivable processing, but the low frequency signal of the received signal cannot be heard using the speaker 13. Is composed of.

FIG. 17 is a flow chart of a subroutine of the display changing process (step S93) of FIG. 12 for executing the manual scan search.

In step S97, the changing direction of the rotation of the rotary encoder 31 is determined, and when it is clockwise, the upward display changing process is executed in step S98 (see FIG. 18).
And then returns. When it is counterclockwise in step S93, the downward display change processing (see FIG. 19) is executed in step S99, and then the process returns. Further, when there is no change in rotation in step S97, the process directly returns.

FIG. 18 is a flow chart of a subroutine (step S98) of the upward display change processing of FIG.

[0067] First, after the rotational frequency of the rotary encoder 31 is set to the data CNT in step S601, the data obtained by adding the step frequency Δf centered local oscillation frequency data Df _LO as the center local oscillation frequency data Df _LO at step S602 The data obtained by updating and adding the step frequency Δf to the transmission / reception frequency data Df _CL in step S603 is set as the transmission / reception frequency data D.
Update as f _CL . Then, in step S604, the updated transmission / reception frequency data Df _CL is displayed on the LCD 6
After displaying on the 7-segment liquid crystal display unit 67 of 0, the upward display data replacement process (see FIG. 20) is executed in step S605. In the upward display data replacement process, the matrix display unit 6 of the LCD 60
In order to shift the display position of the signal level of the reception signal of a plurality of frequencies in 1 to the left by one step, V
The pixel data in the RAM 40 is replaced.

Next, in step S606, data (Df _LO + 3Δ) is added to the central local oscillation frequency data Df _LO.
Store and update f) and set. Further, step S60
7, the received signal level data SLD output from the A / D converter 20 is detected and fetched, and step S
After converting the data SLD into 4-level data in 608, the converted data is stored and updated in addresses 60-63 of the VRAM 40 in step S609, and the rightmost one column of the matrix display unit 61 of the LCD 60 is converted. Using four liquid crystal pixels LM60-LM63,
The signal level is displayed in the vertical direction with the lower end at the 0/4 level, and the signal level at the right end where the frequency does not correspond due to the data replacement in step S605 is detected and displayed. Then, step S6
After updating the data CNT by decrementing it by 1 in step 10, it is determined in step S611 whether the data CNT is 0. If CNT = 0, the rotary encoder 31 is rotated to perform the designated shift. It returns assuming that the display position of the matrix liquid crystal display unit 61 has been shifted by several minutes. On the other hand, if CNT ≠ 0 in step S611, the process returns to step S602 and is repeated.

Through the above-described processing, the rotary encoder 3 displays the display position of the signal level of the reception signals of a plurality of frequencies displayed on the matrix liquid crystal display section 61 of the LCD 60.
1 can be used to shift the frequency upwards by a manually set number of steps. For example, as shown in FIG. 26, when the transmission / reception frequency is f11 (time t1), when the rotary encoder 31 is rotated clockwise by three steps, it is sequentially changed from t1 to t2 and t3. It becomes a state. In addition, in FIG.
The frequency of each signal level in the matrix liquid crystal display unit 61 that changes according to the rotation operation of the rotary encoder 31 and the transmission / reception frequency data Df _CL displayed on the liquid crystal display unit 67 are shown, and f11 is the transmission / reception frequency at the start of the scan search. The higher the number assigned to “f”, the higher the frequency.

FIG. 19 is a flow chart of a subroutine (step S99) of the downward display change processing of FIG.

[0071] First, after the rotational frequency of the rotary encoder 31 is set to the data CNT in step S621, the data obtained by adding the step frequency Δf centered local oscillation frequency data Df _LO as the center local oscillation frequency data Df _LO at step S622 The data is updated, and the transmission / reception frequency data Df _CL is obtained by subtracting the step frequency Δf from the transmission / reception frequency data Df _CL in step S623.
Update as f _CL . Then, in step S624, the updated transmission / reception frequency data Df _CL is displayed on the LCD 6
After displaying on the 7-segment liquid crystal display 67 of 0, the downward display data replacement process (see FIG. 21) is executed in step S625. In the downward display data replacement process, the matrix display unit 6 of the LCD 60
In order to shift the signal level display positions of the received signals of a plurality of frequencies in 1 by 1 step to the right,
The pixel data in the RAM 40 is replaced.

Then, in step S626, data (Df _LO -3Δf) is added to the central local oscillation frequency data Df _LO.
Store, update, and set. Furthermore, in step S627, the received signal level data SLD output from the A / D converter 20 is detected and captured, and in step S62.
After converting the data SLD into 4-level data in step S8, the converted data is stored in the address 00-03 of the VRAM 40 and updated in step S629, and the rightmost one column of the matrix display unit 61 of the LCD 60 is converted. Using four liquid crystal pixels LM00-LM03, the signal level is displayed in the vertical direction with the lower end at 0/4 level,
As a result, the signal level at the left end where the frequencies do not correspond due to the data replacement in step S625 is detected and displayed. Then, step S630
After updating the data CNT by decreasing it by 1,
In step S631, it is determined whether or not the data CNT is 0. When CNT = 0, the rotary encoder 31 is rotated to shift the display position of the matrix liquid crystal display unit 61 by the designated number of steps to be shifted. To return. On the other hand, if CNT ≠ 0 in step S631, the process returns to step S622 and repeats.

Through the above-described processing, the rotary encoder 3 displays the display position of the signal level of the received signals of a plurality of frequencies displayed on the matrix liquid crystal display section 61 of the LCD 60.
1 can be used to shift the frequency downward by the number of steps set manually. For example, as shown in FIG. 26, when the transmission / reception frequency is f14 (time t4), when the rotary encoder 31 is rotated counterclockwise by three steps, it is sequentially changed from t4 through t3 and t2 to t1. It becomes a state.

FIG. 20 is a flowchart of the subroutine of the upward display data replacement processing (steps S605 and S501) shown in FIGS.

First, in step S321, the VRAM
The pixel data stored in the address 10-13 of 40 is stored and updated in the address 00-03, and the corresponding signal level is displayed in the vertical direction on the liquid crystal pixel LM00-03 of the matrix liquid crystal display unit 61 of the LCD 60. . Next, in step S322, the pixel data stored in the address 20-23 of the VRAM 40 is stored and updated in the address 10-13, and the signal level corresponding to the pixel data is vertically extended in the matrix liquid crystal display unit 61 of the LCD 60.
The liquid crystal pixels LM10-13 are displayed. Further, in steps S323 to S326, the same processing is repeated, and the addresses 30-33 and 40-4 of the VRAM 40 are repeated.
Pixel data stored in 3, 50-53, and 60-63 have their addresses 20-23, 30-33, respectively.
40-43, 50-53 are stored and updated, and the signal levels corresponding to them are respectively updated in the vertical direction in the liquid crystal pixels LM20-23, LM3 of the matrix liquid crystal display unit 61 of the LCD 60.
Display on 0-33, LM40-43, LM50-53 and return. Through the above processing, the display position of the signal levels of the reception signals of a plurality of frequencies displayed on the matrix liquid crystal display section 61 of the LCD 60 is shifted leftward by one step.

FIG. 21 is a flow chart of a subroutine of the downward display data replacement process (steps S625 and S511) of FIGS.

First, in step S331, the VRAM
The pixel data stored in the addresses 50-53 of 40 are stored and updated in the addresses 60-63, and the corresponding signal level is displayed in the vertical direction on the liquid crystal pixels LM60-63 of the matrix liquid crystal display unit 61 of the LCD 60. . Next, in step S332, the pixel data stored in the addresses 40-43 of the VRAM 40 is stored and updated in the addresses 50-53, and the signal level corresponding to the pixel data is vertically changed to the matrix liquid crystal display unit 61 of the LCD 60.
Liquid crystal pixels LM50-53. Further, in steps S333 to S336, the same processing is repeated, and addresses 30-33 and 20-2 of the VRAM 40 are repeated.
Pixel data stored in Nos. 3,10-13,00-03 are assigned addresses 40-43,30-33, respectively.
20-23, 10-13 are stored and updated, and the signal levels corresponding thereto are updated in the vertical direction in the liquid crystal pixels LM40-43, LM3 of the matrix liquid crystal display unit 61 of the LCD 60.
Display on 0-33, LM20-23, LM10-13 and return. Through the above processing, the display position of the signal levels of the reception signals of a plurality of frequencies displayed on the matrix liquid crystal display section 61 of the LCD 60 is shifted rightward by one step.

FIG. 22 is a flow chart of a subroutine of the scan search receivable processing of FIG.

As shown in FIG. 22, first, step S4
In 01, it is determined whether or not the PTT switch SW1 is turned on, and when it is turned on, step S402
Then, the H-level TRSW signal is output to switch the transmission / reception changeover switch 10 to the contact b side to put it in the transmission state, and then the process returns. On the other hand, when the PTT switch SW1 is not turned on (N in step S401
O), in step S403, the L level TRSW signal is output to switch the transmission / reception changeover switch 10 to the contact a side to bring it into the receiving state, and in step S404, the H level ESQ signal is output to output the squelch switch 1.
1 is turned off, and the output of the low frequency signal to the speaker 13 is stopped. Next, in step S405, the flag FS
It is determined whether or not 5S = 1. When FS5S = 1, in step S406, the addresses 00-63 of the VRAM 40 are cleared to turn off all the liquid crystal pixels of the matrix liquid crystal display unit 61, and in step S407, the flag FS5S is set. Is reset to 0 and then step S408
Proceed to. On the other hand, if FS5S = 0 in step S405, the process directly proceeds to step S408.

Next, in step S408, it is determined whether or not the flag FUP = 1, and when FUP = 1, the pixel data Dcm is set to "0" in step S409.
1 ”is stored and the LCD 60 for indicating the center is displayed on the LCD 60.
The liquid crystal pixel of 3b is displayed on the liquid crystal, the scan search upward processing (see FIG. 23) is executed in step S410, and the process returns. On the other hand, in step S408, FUP = 0
, The pixel data Dcm in step S411
"10" is stored in, and the liquid crystal display of the liquid crystal pixel of the center instruction liquid crystal display portion 63c is displayed on the LCD 60 by the step S410.
In the scan search downward processing (see FIG. 24), the process returns.

The scan search unreceivable process (step S16) in FIG. 22 is performed in step S404 in FIG.
22 is the same as the search reception process (step S16) shown in FIG. 22, except that the ESQ signal of H level is output instead of L level. As a result, in the scan search mode and the unreceivable mode, the signal levels of a plurality of frequencies are displayed as in the scan search receivable process, but the low frequency signal of the received signal can be heard using the speaker 13. It is configured so that it cannot be done.

FIG. 23 is a flowchart of the scan search upward process (step S410) of FIG.

First, after the upward display data replacement process (see FIG. 20) is executed in step S501,
In step S502, the L-level ESQ signal is output, the squelch switch 11 is turned off, the low-frequency signal of the modulated wave of the received signal can be received using the speaker 13, and the MPU 30 for standby processing The clock time Twp of the clock timer is reset to 0 seconds and the clock starts. Next, in step S503, the transmission / reception frequency data Df _CL is set in the register 43 to be displayed on the liquid crystal display unit 67, in step S504 the central local oscillation frequency data Df _LO is set to the local oscillation frequency data Df _L , and then in step S505. move on.

In step S505, the received signal level data SLD output from the A / D converter 20 is detected and fetched, and in step S506, the data SL
After converting D into 4-level data, step S507
The converted data is stored and updated in the addresses 60-63 of the VRAM 40 at 4 and the four liquid crystal pixels L for one column at the right end of the matrix display portion 61 of the LCD 60.
The M60-LM63 is used to display the signal level in the vertical direction with the lower end at the 0/4 level, and it is determined in step S508 whether the SD signal is at the H level. S
When the D signal is at the H level, that is, when there is no signal at the reception frequency, the process proceeds to step S510 without executing the waiting time determination process of step S509.
On the other hand, when the SD signal is at the L level in step S508, that is, when there is a signal at the reception frequency, the standby time for the standby process is determined in step S509. That is, the count time T of the count timer
It is determined whether wp has passed a preset waiting time Tw. If it has not elapsed, step S505
Returning to step 1, while executing the standby process, the level detection display process of the reception frequency is executed. On the other hand, when it has elapsed, the process proceeds to step S510. Then, step S51
At 0, the frequency data (Df _LO + Δf) is set as the central local oscillation frequency data Df _LO , the frequency data (Df _CL + Δf) is set as the transmission / reception frequency data Df _CL , and then the process returns.

The signal level displayed in step S507 in FIG. 23 indicates the signal level of the signal currently being received. In the loop processing that returns from step S505 to step S505 through step S509, the squelch switch 11 is ON while detecting and displaying the signal level of the received signal in real time at a predetermined cycle. Therefore, it is possible to receive the reception signal of the set transmission / reception frequency f _R = fset = Df _CL and listen to the low frequency signal of the modulated wave through the speaker 13. It should be noted that the present invention is not limited to this, and the standby time may not be determined in step S509, and the standby time may be, for example, the standby time Tw seconds. In this case, the currently received signal level does not change in real time.

FIG. 24 is a flow chart of the scan search downward process (step S412) subroutine of FIG.

First, after the downward display data replacement process (see FIG. 21) is executed in step S511,
In step S512, the L-level ESQ signal is output, the squelch switch 11 is turned off, the low frequency signal of the modulated wave of the received signal can be received using the speaker 13, and the MPU 30 for standby processing The clock time Twp of the clock timer is reset to 0 seconds and the clock starts. Next, in step S513, the transmission / reception frequency data Df _CL is set in the register 43 to be displayed on the liquid crystal display unit 67, and in step S514, the central local oscillation frequency data Df _LO is set to the local oscillation frequency data Df _L , and then in step S505. move on.

In step S515, the received signal level data SLD output from the A / D converter 20 is detected and fetched, and in step S516, the data SL
After converting D into 4-level data, step S517
The converted data is stored in the address 00-03 of the VRAM 40 and updated at 4 and the four liquid crystal pixels L for one column at the left end of the matrix display portion 61 of the LCD 60.
Using M00-LM03, the signal level is displayed in the vertical direction with the lower end at the 0/4 level, and it is determined in step S518 whether the SD signal is at the H level. S
When the D signal is at the H level, that is, when there is no signal at the reception frequency, the process proceeds to step S520 without executing the waiting time determination process of step S519.
On the other hand, when the SD signal is at the L level in step S518, that is, when there is a signal at the reception frequency, the standby time for the standby process is determined in step S519. That is, the count time T of the count timer
It is determined whether wp has passed a preset waiting time Tw. If not, step S515
Returning to step 1, while executing the standby process, the level detection display process of the reception frequency is executed. On the other hand, if it has elapsed, the process proceeds to step S520. Then, step S52
At 0, the frequency data (Df _LO −Δf) is set as the central local oscillation frequency data Df _LO , and the frequency data (Df _CL −Δf) is set as the transmission / reception frequency data Df _CL , and then the process returns.

The signal level displayed in step S517 in FIG. 24 indicates the signal level of the signal currently being received. In the loop processing of returning from step S515 to step S515 through step S519, the squelch switch 11 is ON while detecting and displaying the signal level of the received signal in real time at a predetermined cycle. Therefore, the reception signal of the set transmission / reception frequency f _R = fset = Df _CL can be received and the low frequency signal of the modulated wave can be heard through the speaker 13. Note that the present invention is not limited to this, and the standby time may not be determined in step S519, and the standby time may be, for example, the standby time Tw seconds. In this case, the currently received signal level does not change in real time.

In the scan search receivable processing described with reference to FIG. 22, the transmission / reception frequency is automatically changed to the upward or downward frequency for each step frequency set using the step frequency selection key 33. Repeat until the scan search mode is canceled,
Accordingly, by shifting the data of the signal levels of the reception signals of a plurality of frequencies in the VRAM 40, the display position of the signal levels of the reception signals of a plurality of frequencies is displayed in the upward or downward direction of the frequency in response to the change of the transmission / reception frequency. Are sequentially shifted and displayed. Here, in the scan search mode, when the transmission / reception frequency is changed upward, the signal level of the transmission / reception frequency is displayed in the matrix liquid crystal display unit 61 as indicated by the center instruction liquid crystal display unit 63b in FIG. After being shifted so as to be located at the right end, the display position of the signal level corresponding thereto is sequentially shifted to the left as shown in FIG. 27 because the transmission / reception frequency is sequentially scanned in the upward direction. On the other hand, when changing to the downward direction, the display of the signal level of the transmission / reception frequency is shifted so as to be located at the left end of the matrix liquid crystal display portion 61 as instructed by the center instruction liquid crystal display portion 63c in FIG. Since the transmission / reception frequency is sequentially scanned downward, the display position of the corresponding signal level is shown in FIG.
As shown in FIG. 8, the shift is sequentially performed to the right. Note that FIG.
7 and 28, similar to FIG. 26, the frequency of each signal level in the matrix liquid crystal display unit 61 that changes with the passage of time t and the transmission / reception frequency data Df _CL displayed on the liquid crystal display unit 67 are shown. , F11 are transmission / reception frequencies at the start of the scan search, and the higher the number assigned to “f”, the higher the frequency.

In step S406 in the scan search receivable processing of FIG. 22, all the liquid crystal displays of the matrix liquid crystal display portion 61 in the LCD 60 are turned off, but the present invention is not limited to this, and the processing of step S406 should be executed. Instead, it may be configured not to be turned off. in this case,
29 and 30 corresponding to FIGS. 27 and 28, respectively.
As shown in (3), in the upward scan search, the lower three frequencies f8 = f11-3Δf, f9 = f11-2Δf from the transmission / reception frequency f11 at the start of the scan search.
The data of the signal level of f10 = f11-Δf is VRAM.
Since the remaining number is stored in 40, it is additionally displayed as compared with the above-described embodiment, and in the downward scan search, the three frequencies f12 = f11 + Δf and f13 = f11 + 2Δ above the transmission / reception frequency f11 at the start of the scan search.
The data of the signal level of f, f14 = f11 + 3Δf is V
Since it remains stored in the RAM 40, it is additionally displayed as compared with the above embodiment.

FIG. 25 shows a signal level display process for a plurality of frequencies when the VFO mode, the search mode and the search receivable mode are set in the wireless transceiver of FIG. 1 and the SD signal is at the L level and the reception state is repeated. 5 is a timing chart at the time of a search reception process (hereinafter, referred to as a search reception process) centered on the. As shown in FIG. 25, the search reception processing is composed of the following processing groups, and the processing is repeated periodically unless the mode is switched using the switches SW1 to SW4.

(A) Steps S2 and S of the main routine
Processing 500 of T0 seconds including processing of 3. (B) 3 below the set transmission / reception frequency f _R = fset = Df _CL including the processing of steps S211 to S234
A process 501 of T1 seconds including a detection display process of signal levels of three frequencies (hereinafter, referred to as lower three frequencies). here,
The lower three frequencies are the frequency f _R −3Δf and the frequency f _R −2Δ which are different from each other by a preset step frequency Δf.
f and frequency f _R −Δf. (C) Process 502 for T2 seconds including the detection / display process of the signal level of the transmission / reception frequency f _R = fset = Df _CL including the processes of steps S240 to S245. (D) Step 246 for determining the waiting time of Tw seconds, and steps S246 to S242 until the waiting time Tw seconds elapses although not shown in FIG.
A process 503 including a loop process of returning to step S246 via. In the process 503, as described above,
The signal level of the received signal of the transmission / reception frequency f _R = fset = Df _CL that is currently being received is periodically detected and displayed in real time at a predetermined cycle, and the operator modulates while watching the display of the signal level. The low frequency signal of the wave can be heard through the speaker 13. (E) 3 above the set transmission / reception frequency f _R = fset = Df _CL including the processing of steps S250 to S274
Processing 504 for T3 seconds including detection display processing of signal levels of one frequency (hereinafter, referred to as upper three frequencies). here,
The upper three frequencies are frequency f _R + Δf, frequency f _R + 2Δf, which are different from each other by a preset step frequency Δf.
The frequency is f _R + 3Δf.

In the search reception processing, the processing 5
00 to 504 are cyclically repeated, and when the level detection display process of one frequency is being performed, the signal levels of the other six frequencies are stored in the VRAM 40 and displayed in the previous level detection display process. Therefore, the matrix display section 61 of the LCD 60 displays the signal levels for all seven frequencies including the upper 3 frequencies, the transmission / reception frequency f _R, and the lower 3 frequencies, and thereby the step frequency Δf Then, the signal levels of a plurality of frequencies including the frequency band from the lowest frequency f _R −3Δf to the highest frequency f _R + 3Δf and having a reception bandwidth of 6Δf are displayed. Also, for example, process 500
Through 502 and processing 504 time (T0 + T1 + T2 + T
3) By making the seconds as small as possible and making the waiting time Tw seconds sufficiently long, the time (T0 + T1 + T2 + T3) seconds of the processing 500 to 502 and the processing 504 (the squelch switch 11 is turned off in the processing 500 to 502 and the processing 504). The low frequency signal of the modulated signal of the received signal of the transmission / reception frequency f _R is used in the steps S244 to S246 in most of the time except for the case where the low frequency signal of the received signal is not output from the speaker 13 by using the speaker 13. I can listen.

Here, since the signal levels of the seven frequencies are always stored in the VRAM 40, the low frequency signal of the modulated wave of the reception signal of the desired transmission / reception frequency f _R is substantially used by the speaker 13. It is possible to observe the signal levels of a plurality of frequencies displayed on the matrix display section 61 while listening to. Therefore, the signal level of the transmission / reception frequency f _R which is currently set and is being received, and 6
Each signal level at one frequency can be easily observed.

Here, the waiting time Tw may be variably set by the operator using the ten keys 32 according to the communication status, and Tw is preferably set to 10 to 30 seconds. In addition, according to a trial experiment of the present inventor, it was confirmed that the level detection display processing for one frequency can be suppressed to 0.01 milliseconds or less.

The memory channel mode process (step S4) is the VFO process (step S4) except for the following processes.
It is executed in the same manner as 5). Here, it is assumed that the channel number preset using the rotary encoder 31 or the numeric keypad 32 is a natural number m, and the transmission / reception frequency at that time is fm. At this time, the set frequency fset is set to fm. (A) The “M” liquid crystal display portion 65 is displayed on the LCD 60. (B) In step S211, the frequency data {Df _LO
-F (m-3)} is set as the local oscillation frequency data Df _L. (C) In step S221, frequency data {Df _LO
-F (m-2)} is set as the local oscillation frequency data Df _L. (D) In step S231, frequency data {Df _LO
-F (m-1)} is set as the local oscillation frequency data Df _L. (E) In step S251, frequency data {Df _LO
-F (m + 1)} is set as the local oscillation frequency data Df _L. (F) In step S261, frequency data {Df _LO
-F (m + 2)} is set as the local oscillation frequency data Df _L. (G) In step S271, frequency data {Df _LO
-F (m + 3)} is set as the local oscillation frequency data Df _L.

When the memory channel mode, the search mode, and the search receivable mode are set in the radio transceiver and the reception state is repeated, when the level detection display process of one frequency is being performed, the other six frequencies are displayed. Since the signal level for is stored and displayed in the VRAM 40 in the immediately preceding level detection display processing, the LCD
The channel number (m
The signal levels for the frequencies of the seven memory channels from -3) to (m + 3) are displayed, thereby displaying these seven signal levels. Therefore, the signal levels of the currently set and received memory channel and the six memory channels near the memory channel number can be easily observed even if the frequencies are far apart from each other. In the above operation mode, each signal level is displayed when seven channel numbers are arranged in ascending order. The displayed channel number is the signal of the received signal corresponding to the seven channel numbers selected by the operator in advance. The level may be displayed.

As described above, in the VFO mode and the memory channel mode, by selecting the receivable mode which is the search mode, one system of receiving circuit for receiving only the high frequency signal of one receiving frequency is used. Thus, the processing of detecting and storing the signal levels of a plurality of frequencies and the processing of outputting the output of the FM demodulator 8 to the speaker 13 are performed in a time-division manner, and in effect, reception of the desired transmission / reception frequency f _R is performed. Speaker 1 for low frequency signal of modulated wave of signal
It is possible to easily and substantially simultaneously observe the signal levels of the seven frequencies displayed on the matrix display section 61 while listening to the sound by using the signal No. 3. For example, in the VFO mode, a pseudo spectrum can be displayed by reducing the step frequency. The time-division processing may be performed at the same time. In this case, when the reception signal of six frequencies other than the reception signal of the desired transmission / reception frequency f _R is received and the signal level is equal to or higher than the squelch level. Is possible with a jarring sound.

In this embodiment, unlike the conventional example shown in FIG. 2, the two-system receiving circuit of the original signal receiving circuit and the receiving circuit for spectrum display is not provided, and only the former one-system receiving circuit is provided. Since it is provided, a radio transceiver with a signal level display function of a plurality of frequencies, which has an extremely simple circuit configuration and a low manufacturing cost, is realized as compared with the conventional example of FIG. 2 and a case where a spectrum analyzer is separately provided. be able to.

Further, in the conventional example of FIG. 2, the bandwidth when measuring the received signal during spectrum display is
Substantially determined by the pass band width of the band pass filter in the scope IF amplifier 112, and if it is desired to set the same as the received signal level displayed by the signal level meter 109, the bandwidth of the band pass filter in the IF amplifier 104. Must be changed to be the same as that of the scope IF amplifier 112. On the other hand, in the present embodiment, since the processing is performed by the same receiving circuit, it is not necessary to change the setting, and a plurality of frequencies (VFO) located near the frequency of the currently received signal are received. The signal level (in the mode) can be easily grasped by looking at the matrix display section 61 of the LCD 60 under the same reception condition as the received signal being received. This makes it possible to easily find a vacant channel or a used channel in a nearby frequency. The former is useful for understanding free channels, especially when most of the channels are busy, such as in urban areas.On the other hand, knowing which channels are in use is especially important for channels used in areas other than urban areas. It is effective when there are few.

Further, in the receiving state, the number of pixels in the horizontal direction is set to be larger than the number of pixels in the vertical direction in the search mode as described above, so that the matrix display portion 61 of the LCD 60 changes in the vertical direction. While displaying the respective signal levels relating to the high frequency signals of seven frequencies, the signal level of the high frequency signal being received which changes in the horizontal direction by using the lowermost 2 rows and 7 columns pixels of the matrix display section 61 in the normal mode. Can be displayed with a larger number of steps than the signal level display of a plurality of frequencies, that is, with a higher number of signal levels.

Although the wireless transmitter / receiver has been described in the above embodiments, the present invention is not limited to this, and can be applied to a wireless receiver, a wired receiver or a wired transmitter / receiver which receives a high frequency signal. Further, although an example of the FM transceiver is described in the above embodiments, the present invention is not limited to this, and can be applied to a transceiver or receiver of any modulation scheme such as AM, SSB, FSK. . In the above-described embodiments, the receiver including the receiving circuit of one system is described, but the present invention is not limited to this, and may be applied to the receiver including the receiving circuits of a plurality of systems.

In the above embodiment, the VRAM 40, which is a memory for storing display data on the LCD 60, and the registers 41, 42, 43 are provided separately from the MPU 30, but the present invention is not limited to this, and these memories are provided. 1
A chip microprocessor may be used.

In the above embodiment, the transmission frequency and the reception frequency are set to be the same at the set frequency fset, but they are set to be different from each other by a predetermined frequency for the repeater operation such as amateur radio. You may.

In the above embodiments, the signal level is displayed horizontally in the normal mode using the matrix display section 61 of the LCD 60, and the signal level is displayed vertically in the search mode using the matrix display section 61. But
These display directions are not limited to this, and these display directions may be reversed, for example.

In the memory channel mode processing (step S4) in the above embodiment, the signal levels of the received signals of the plurality of channels are displayed in juxtaposition in ascending order, but the invention is not limited to this and the juxtaposition is performed in descending order. You may.

In the above embodiment, the LC is set so that the signal level of the received signal is changed in the horizontal direction in the normal mode.
Although it is displayed on the matrix display portion 61 of D60, the present invention is not limited to this, and it may be displayed so as to change in the vertical direction. Also, in search mode, the LCD can be set to change the signal level of each spectrum in the vertical direction.
Although it is displayed on the matrix display unit 61 of 60, the present invention is not limited to this and may be displayed so as to change in the horizontal direction. Further, the display direction of the signal level may be changed between the display of the signal level and the display of the spectrum, or may be displayed in the same direction without changing.

In step S45 of FIG. 11, the setting process for the set frequency fset is performed.
When et is unchanged, the process of step S45 may be omitted.

In FIG. 15, in step S245, it is determined whether or not the standby process (see step S246) for the predetermined time Tw is executed according to the presence or absence of the received signal. The determination may be made accordingly, or the process of step S245 may be deleted. In this case, step S246 is performed regardless of the signal level of the SD signal, that is, regardless of the presence or absence of the received signal.
The standby process of is executed.

In FIG. 15, YE is determined in step S245.
When S, the process directly proceeds to step S250, but not limited to this, a standby process of waiting for a preset standby time Twa may be executed and the process proceeds to step S250.

By changing the waiting time Tw and / or the waiting time Twa, the processing of detecting and storing the signal levels of a plurality of frequencies by using the receiving circuit of one system and the output of the FM demodulator 8. It is possible to change the ratio of the operation time of each of the above processes when the process of outputting to the speaker 13 is performed in a time division manner.

In the above embodiments, the local oscillator 4 is constructed by using the PLL circuit. However, in order to shorten the operation time for changing and setting the local oscillation frequency, the ROM for storing the signal waveform level in advance is stored. May be used to generate a local oscillation signal having a predetermined local oscillation frequency.

In the above embodiment, when the SD signal is at the L level, the signal level for one reception frequency is detected and stored in steps S240 to S246, and the demodulated low frequency signal is output to the speaker 13. However, the present invention is not limited to this, and the signal levels of a plurality of reception frequencies may be sequentially detected and stored, and the demodulated low frequency signal may be sequentially output to the speaker 13.

Although the OR gate OR1 is provided outside the MPU 30 in the above embodiments, it may be realized by software for internal processing of the MPU 30.

[0116]

As described above in detail, according to the present invention, in a display device of a receiver which receives a high frequency signal at a predetermined reception frequency, the reception frequency is selectively switched in an arbitrarily set switching order. And a detection storage unit for detecting and storing the received signal strengths of the plurality of received frequencies, and a plurality of display units, and the stored signal strengths of the plurality of received frequencies are respectively associated with the switching order. Display means for displaying on the plurality of display units, and a plurality of display means for displaying on the display means by shifting the signal strength of the plurality of reception frequencies stored in the detection storage means in response to the change of the reception frequency. And a control means for shifting the display position of the signal strength of the reception frequency, the signal strength of the plurality of reception frequencies is switched in the plurality of display portions of the display means. It is possible to display each corresponding to ordinal, it can be changed by shifting the display position of the signal intensity of the plurality of frequencies in response to change of the received frequency. Thereby, the signal strengths of a plurality of frequencies can be easily and substantially simultaneously observed. In addition, there is an advantage that a free channel or a used channel in a nearby frequency can be easily found.

[Brief description of drawings]

FIG. 1 is a block diagram of a wireless transceiver with a signal level display function for a plurality of frequencies according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional radio receiver with a spectrum display function.

FIG. 3 is a front view of the LCD of FIG.

FIG. 4 is a front view showing a relationship between liquid crystal pixels of a matrix display section of the LCD of FIG. 3 and an address of a VRAM storing pixel data.

5 is a front view of the LCD showing an example when the signal levels of a plurality of frequencies are displayed in the VFO mode and the search mode in the wireless transceiver of FIG. 1. FIG.

FIG. 6 is a front view of an LCD showing an example when the reception signal level is displayed in the VFO mode and the normal mode in the wireless transceiver of FIG. 1.

7 is a front view of an LCD showing an example when the signal levels of a plurality of frequencies are displayed in the scan search mode when the transmission / reception frequency is scanned in the VFO mode in the wireless transceiver of FIG. is there.

8 is a front view of an LCD showing an example of displaying the signal levels of a plurality of frequencies in a scan search mode when the transmission / reception frequency is scanned in a lower direction in the wireless transceiver of FIG. is there.

9 is a flowchart of a main routine executed by a CPU of the wireless transceiver of FIG.

10 is a first subroutine of the key input process of FIG.
It is a flowchart of the part.

FIG. 11 is a second subroutine of the key input process of FIG.
It is a flowchart of the part.

12 is a flowchart of a subroutine of VFO mode processing of FIG.

13 is a flowchart of a normal processing subroutine of FIG.

FIG. 14 is the first part of the flowchart of the subroutine of the search receivable processing of FIG.

FIG. 15 is a second part of the flowchart of the subroutine of the search receivable processing of FIG.

FIG. 16 is a third part of the flowchart of the subroutine of the search receivable processing in FIG.

FIG. 17 is a flowchart of a subroutine of the display change process of FIG.

FIG. 18 is a flowchart of a subroutine of an upward display change process of FIG.

FIG. 19 is a flowchart of a subroutine of downward display change processing of FIG.

FIG. 20 is a flowchart of a subroutine of the upward display data replacement process of FIGS. 18 and 23.

FIG. 21 is a flowchart of a subroutine of the downward and upward display data replacement processing of FIGS. 19 and 24.

22 is a flowchart of a subroutine of scan search receivable processing of FIG. 12. FIG.

FIG. 23 is a flowchart of a scan search upward process subroutine in FIG. 22;

FIG. 24 is a flowchart of a scan search downward process subroutine in FIG. 22;

FIG. 25 is a timing chart mainly showing signal level display processing of a plurality of frequencies in the wireless transceiver of FIG.

FIG. 26 shows the frequencies of seven signal levels displayed on the matrix display 61 of the liquid crystal display and the transmission / reception frequencies displayed on the 7-segment liquid crystal display 67 when the transmission / reception frequencies are scanned by the manual scan search. It is a figure.

FIG. 27 shows the frequency of seven signal levels displayed on the matrix display section 61 of the liquid crystal display section and the 7-segment liquid crystal display section 67 when the transmission / reception frequency is scanned by the automatic scan search for scanning the transmission / reception frequency in the higher direction.
It is a figure which shows the transmission / reception frequency displayed on.

FIG. 28 shows seven signal level frequencies displayed on the matrix display section 61 of the liquid crystal display section when the transmission / reception frequency is scanned by the automatic scan search for scanning the transmission / reception frequency in the lower direction, and the 7-segment liquid crystal display section 67.
It is a figure which shows the transmission / reception frequency displayed on.

FIG. 29 is a 7-segment liquid crystal display with seven signal level frequencies displayed on the matrix display 61 of the liquid crystal display when the transmission / reception frequency is scanned in a modification of the automatic scan search in which the transmission / reception frequency is scanned in the higher direction. It is a figure which shows the transmission / reception frequency displayed on the part 67.

FIG. 30 shows 7 signal level frequencies displayed on the matrix display section 61 of the liquid crystal display section and a 7-segment liquid crystal display when the transmission / reception frequency is scanned in a modification of the automatic scan search for scanning the transmission / reception frequency in the lower direction. It is a figure which shows the transmission / reception frequency displayed on the part 67.

[Explanation of symbols]

1 ... Antenna, 2 ... RF amplifier, 3, 24 ... Mixer, 4 ... Local oscillator, 5 ... IF band pass filter, 6 ... IF amplifier, 8 ... FM demodulator, 9 ... Low pass filter, 10 ... Transmission / reception switching Switch, 11 ... Squelch switch, 12 ... AF amplifier, 13 ... Speaker, 14 ... High pass filter, 15 ... Squelch level adjusting attenuator, 16 ... Noise amplifier, 17 ... Detection circuit, 18 ... Waveform shaping circuit, 19 ... Detection circuit, 20 ... A / D converter, 30 ... MPU, 31 ... Rotary encoder (RE), 32 ... Numeric keypad, 33 ... Step frequency selection key, 34 ... Frequency change unit changeover switch, 40 ... VRAM, 41, 42, 43, 44 ... Registers, 50, 51, 52, 53, 54 ... LCD driver, 60 ... LCD, 61 ... Matrix display section, 3a, 63b, 63c ... Center indicating liquid crystal display section, 67 ... 7 segment liquid crystal display section, OR1 ... OR gate, SW1 ... PTT switch, SW2 ... VFO mode / memory channel mode changeover switch, SW3 ... Normal mode / search mode changeover switch , SW4 ... Receivable mode / Unreceivable mode changeover switch, SW5 ... Normal mode / scan search mode changeover switch.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 1, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction content]

Furthermore, the MPU 30 is connected to the ground via the following five switches. (A) PTT (Push To Talk) switch SW1: A switch for setting the wireless transceiver to a transmission state and transmitting an audio signal, which is in a transmission state when turned on. (B) VFO mode / memory channel mode switch SW2: This switch selectively switches between the VFO mode and the memory channel mode, and the VFO mode and the memory channel mode are alternately switched every time the switch is turned on. (C) Normal mode / search mode switch SW
3: A switch for selectively switching between the normal mode and the search mode, and the normal mode and the search mode are alternately switched every time the switch is turned on. (D) Receivable mode / unreceivable mode changeover switch SW4: a switch that is effective only in the search mode, and is a switch that selectively switches between the receivable mode and the unreceivable mode. The enable mode and the unreceivable mode are switched alternately. (E) Normal mode / scan search mode switch SW5: This switch selectively switches between the normal mode and the scan search mode, and the normal mode and the scan search mode are switched alternately each time the switch is turned on.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

FIG. 3 is a front view when all the liquid crystal pixels are displayed on the LCD 60. As shown in FIG. 3, a matrix liquid crystal display in which liquid crystal pixels LM00 to LM63 (see FIG. 4), which are rectangular liquid crystal pixels and have a matrix shape of 4 rows and 7 columns, are arranged in the central portion of the upper portion of the LCD 60, as shown in FIG. And a liquid crystal pixel LM00-L in the lowermost row of the matrix liquid crystal display unit 61.
Immediately below M60, reference indicating liquid crystal pixels 62 each having a horizontal line shape and always showing the display position and the reference level when displaying signal levels of a plurality of frequencies are provided.
On the other hand, in the vicinity of the upper side of the liquid crystal pixel LM33 in the upper center of the matrix liquid crystal display section 61, a center indicating liquid crystal display section 63a having a downward arrow shape is provided. In addition, the liquid crystal pixel LM6 at the upper right end of the matrix liquid crystal display unit 61.
3, a center indicating liquid crystal display portion 63b having a shape of a downward arrow is provided, and a downward arrow shape is provided near the upper side of the liquid crystal pixel LM63 at the upper left end of the matrix liquid crystal display portion 61. The center indicating liquid crystal display portion 63c is provided. Further, on the left side of the matrix liquid crystal display unit 61, in the normal mode, the level indicated by the matrix liquid crystal display unit 61 is the reception signal level (in the reception state) or the transmission signal level (in the transmission state).
"S / RF" liquid crystal display portion 64 indicating that the memory channel mode is formed, and immediately below that, an "M" liquid crystal display portion 65 indicating that the memory channel mode is present is formed. A 3-digit 7-segment liquid crystal display unit 66 indicating a channel is formed. Further, in the lower right part of the LCD 60, a 5-digit 7-segment liquid crystal display section 67 showing the transmission / reception frequency f _R (center transmission / reception frequency in the scan mode) is formed.
7 has a decimal point below the second and third digits.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

The VRAM 40 is connected to the MPU 30,
This is a video RAM that stores 28 pixel data to be displayed on the matrix liquid crystal display unit 61, and the output terminal of the VRAM 40 is connected to the matrix display unit 61 of the LCD 60 via the LCD driver 50. Therefore, VRAM
When the pixel data is stored in 40, LC
Liquid crystal display is performed in real time on the matrix liquid crystal display unit 61 by the D driver 50. FIG. 4 is a front view showing the relationship between the liquid crystal pixels of the matrix liquid crystal display unit 61 of the LCD of FIG. 3 and the addresses of the VRAM 40 that stores pixel data. As shown in FIG. 4, 28 liquid crystal pixels LM0
0-LM63, each with a two-digit display "00"-"6"
The address “3” is given.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

The register 41 is connected to the MPU 30,
A 2-bit register for storing 2-bit pixel data Dsm for displaying on the liquid crystal display units 64 and 65,
The output terminal of the register 41 is connected to the liquid crystal display units 64 and 65 of the LCD 60 via the LCD driver 51. Therefore, when the pixel data Dsm is stored in the register 41, the LCD driver 51 accordingly displays the liquid crystal on the liquid crystal display units 64 and 65. Here, the pixel data D
The first bit of sm is data indicating whether to display the liquid crystal display unit 64, and the second bit of pixel data Dsm is data indicating whether to display the liquid crystal display unit 65.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

The register 42 is connected to the MPU 30,
A register 42 for storing the memory channel number data Dm to be displayed on the liquid crystal display unit 66.
The output terminal of is connected to the liquid crystal display unit 66 of the LCD 60 via the LCD driver 52. Therefore, when the pixel data Dm is stored in the register 42, the LCD
A liquid crystal display is displayed on the liquid crystal display unit 66 by the driver 52. Further, the register 43 is connected to the MPU 30 and transmitted / received frequency data Df for displaying on the liquid crystal display 67.
A register for storing _CL, and an output terminal of the register 43 is connected to the liquid crystal display unit 67 of the LCD 60 via the LCD driver 52. Therefore, when the pixel data Df _CL is stored in the register 43, the LCD driver 53 accordingly displays the liquid crystal on the liquid crystal display unit 67.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

The register 44 is connected to the MPU 30,
This is a 2-bit register for storing 2-bit pixel data Dcm for displaying the center indicating liquid crystal display portions 63a, 63b, 63c, and the output terminal of the register 44 is L.
The liquid crystal display 63 of the LCD 60 via the CD driver 54
a, 63b, 63c. Therefore, register 4
4 when the pixel data Dcm is stored, the liquid crystal display portions 63a, 63
A liquid crystal display is displayed at b and 63c. Here, the pixel data Dc
When m is "00", only the liquid crystal display section 63a that indicates the center of the matrix liquid crystal display section 61 is displayed, and when the pixel data Dcm is "01", the matrix liquid crystal display section 61 is displayed.
Only the liquid crystal display portion 63b indicating the right end of the matrix liquid crystal display portion 63c is displayed, and when the pixel data Dcm is "10", only the liquid crystal display portion 63c indicating the left end of the matrix liquid crystal display portion 61 is displayed.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

The various flags stored in the RAM in the MPU 30 are as follows. (A) FS2: FS2 = 0 in the VFO mode,
In the memory channel mode, FS2 = 1. (B) FS3: FS3 = 0 in the normal mode, and FS3 = 1 in the search mode. (C) FS4: FS4 = 0 in the receivable mode, and FS4 = 1 in the unreceivable mode. (D) FS5: FS5 = 0 in the normal mode, and FS5 = 1 in the scan search mode. (E) FS5S: a flag indicating the start of scan search, which is set to 1 when the scan search mode is started, and is reset to 0 in step S407 after all the matrix liquid crystal display portions 61 are turned off in step S406 To be done. (F) FUP: Set to 1 when the rotary encoder 31 is rotated clockwise to automatically scan the transmission / reception frequency upwards or manually, while automatically or manually set the transmission / reception frequency downwards. 0 when the rotary encoder 31 is rotated counterclockwise for effective scanning
Is reset to.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

Next, in step S31, it is determined whether or not the switch SW3 is turned on. When it is not turned on, the process proceeds to step S61. When it is turned on, it is determined in step S32 whether the flag FS3 is 1 or not. To be done. Here, when the flag FS3 = 1, the flag FS3 is reset to 0 in step S33 and then the process proceeds to step S61. When the flag FS3 = 0, the flag FS3 is set to 1 in step S34 and the process proceeds to step S61.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

Next, in step S40, the flag F
It is determined whether or not S3 is 1, and it is determined at step S46 whether or not the flag FS5 is 1. That is, these judgments are made in order to validate the processing of steps S41 to S44 only in the search mode or the scan search mode. Therefore, FS3 = 1 or FS5 = 1
If so, the process proceeds to step S41, while FS3 = 0 and FS
When 5 = 0, the process proceeds to step S45. Further, in step S41, it is determined whether or not the switch SW4 is turned on. If not, the process proceeds to step S45, while if it is turned on, the flag F is set in step S42.
It is determined whether or not S4 is 1. Here, flag F
When S4 = 1, the flag FS4 is reset to 0 in step S43 and then the process proceeds to step S45, while when flag FS4 = 0, the flag FS is calculated in step S44.
After 4 is set to 1, the process proceeds to step S45.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Change

[Correction content]

In step S91, the pixel data D
Data “00” is stored in sm and liquid crystal display units 64, 65
The liquid crystal is not displayed on the LCD, and "00" is stored in the pixel data Dcm to display the liquid crystal pixel of the center instruction liquid crystal display unit 63a on the LCD 60, and the process proceeds to step S92. Next, in step S92, it is determined whether or not the flag FS4 is 1, and when FS4 = 0, the search receivable process (see FIGS. 14 to 16) is executed in step S14, and then the process proceeds to step S93. . On the other hand, when FS4 = 1, the search unreceivability process is executed in step S15, and then the process proceeds to step S93. Step S93
In, the display change process (see FIG. 17) which is the process of the manual scan search is executed, and the process returns.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0050

[Correction method] Change

[Correction content]

In step S94, the pixel data D
Data “00” is stored in sm and liquid crystal display units 64, 65
No liquid crystal is displayed on the screen, and the process proceeds to step S95. Next, in step S95, it is determined whether or not the flag FS4 is 1, and when FS4 = 0, the scan search receivable process (see FIGS. 14 to 16) is executed in step S17, and then the process returns. On the other hand, FS4 = 1
If it is, the scan search unreceivable process is executed in step S16, and then the process returns.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0059

[Correction method] Change

[Correction content]

As shown in FIG. 15, in step S240, the L-level ESQ signal is output, the squelch switch 11 is turned off, and the low-frequency signal of the modulated wave of the received signal can be received using the speaker 13. In addition, the clocking time Twp of the clocking timer (not shown) in the MPU 30 for standby processing is reset to 0 seconds to start clocking. Next, after the central local oscillation frequency data Df _LO is set to the local oscillation frequency data Df _L in step S241, the process proceeds to step S242. In step S242, the received signal level data SLD output from the A / D converter 20 is detected and fetched, and step S24
After converting the data SLD into 4-level data in 3, the converted data is stored and updated in the addresses 30-33 of the VRAM 40 in step S244, and the 1 of the central portion of the matrix display portion 61 of the LCD 60 is updated.
The four liquid crystal pixels LM30 to LM33 for columns are used to display the signal level in the vertical direction with the lower end at the 0/4 level, and it is determined in step S245 whether the SD signal is at the H level. When the SD signal is at H level, that is, when there is no reception signal at the reception frequency,
The process proceeds to step S250 of FIG. 16 without executing the waiting time determination process of step S246. On the other hand, when the SD signal is at the L level in step S245, that is, when there is a received signal at the reception frequency, the waiting time for the waiting process is determined in step S246. That is, it is determined whether the time count Twp of the time count timer has passed the preset standby time Tw. When the time has not elapsed, the process returns to the step S242 and the standby detection process is executed while the level detection display process of the reception frequency is executed. On the other hand, if it has elapsed, the process proceeds to step S250 in FIG. Step S above
The signal level displayed at 244 indicates the signal level of the signal currently being received. It should be noted that the above steps S246 to S242 are followed by step S
In the loop processing of returning to 246, the squelch switch 11 is ON while detecting and displaying the signal level of the received signal in a predetermined cycle in real time, and thus the set transmission / reception frequency f _R = fset = Df _CL
The low-frequency signal of the modulated wave can be heard through the speaker 13 by receiving the reception signal of. Note that the present invention is not limited to this, and the standby time may not be determined in step S246, and the standby time may be, for example, the standby time Tw seconds. In this case, the currently received signal level does not change in real time.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0065

[Correction method] Change

[Correction content]

In step S97, the changing direction of the rotation of the rotary encoder 31 is determined, and when it is clockwise, the upward display changing process is executed in step S98 (see FIG. 18).
And then returns. When it is counterclockwise in step S97, the downward display change process (see FIG. 19) is executed in step S99, and then the process returns. Further, when there is no change in rotation in step S97, the process directly returns.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0068

[Correction method] Change

[Correction content]

Next, in step S606, the local oscillation frequency data Df _L is stored and updated with the data (Df _LO + 3Δf) and set. Furthermore, in step S607, the received signal level data SLD output from the A / D converter 20 is detected and captured, and in step S608.
After the data SLD is converted into 4-level data in step S609, the converted data is stored and updated in addresses 60-63 of the VRAM 40 in step S609, and the data for one column at the right end of the matrix display portion 61 of the LCD 60 is divided into four. The liquid crystal pixels LM60 to LM63 are used to display the signal level in the vertical direction with the lower end at 0/4 level, thereby detecting the signal level at the right end where the frequency does not correspond due to the data replacement in step S605. it's shown. Then, after the data CNT is reduced by 1 and updated in step S610, it is determined in step S611 whether the data CNT is 0. When CNT = 0, the rotary encoder 31 is rotated to perform the designated shift. It returns assuming that the display position of the matrix liquid crystal display unit 61 has been shifted by the number of steps to be performed. On the other hand, if CNT ≠ 0 in step S611, the process returns to step S602 and is repeated.

[Procedure Amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0071

[Correction method] Change

[Correction content]

First, after the rotational frequency of the rotary encoder 31 is set to the data CNT in step S621, the data obtained by subtracting the step frequency Δf from the central local oscillation frequency data Df _LO in step S622 is set as the central local oscillation frequency data Df _LO. updated, and updates the data obtained by subtracting the step frequency Δf from the transmission and reception frequency data Df _CL as reception frequency data Df _CL at step S623. Then, in step S624, the updated transmission / reception frequency data Df _{CL is set} to LC.
After displaying on the 7-segment liquid crystal display 67 of D60, in step S625, downward display data replacement processing (see FIG. 21) is executed. In the downward display data replacement process, the pixel data in the VRAM 40 is replaced so that the signal level display positions of the reception signals of a plurality of frequencies on the matrix display unit 61 of the LCD 60 are shifted rightward by one step.

[Procedure Amendment 16]

[Document name to be amended] Statement

[Name of item to be corrected] 0072

[Correction method] Change

[Correction content]

Then, in step S626, the data (Df _LO -3Δf) is stored and updated in the local oscillation frequency data Df _L and set. Further, in step S627, the received signal level data SLD output from the A / D converter 20 is detected and fetched, and in step S628 the data SLD is converted into 4-level data.
In step S629, the converted data is VR
Store and update at address 00-03 of AM40,
Using the four liquid crystal pixels LM00-LM03 for one column at the left end of the matrix display portion 61 of the LCD 60, the lower end is set to 0.
The signal level is displayed in the vertical direction as the / 4 level, and the signal level at the left end where the frequency does not correspond due to the data replacement in step S625 is detected and displayed. Then, in step S630, the data CNT is reduced by 1 and updated, and then in step S631, it is determined whether or not the data CNT is 0. When CNT = 0, the rotary encoder 31
Is rotated and the display position of the matrix liquid crystal display unit 61 is shifted by the designated number of steps to be shifted, and the process returns. On the other hand, in step S631, C
If NT ≠ 0, the process returns to step S622 to repeat the process.

[Procedure Amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0077

[Correction method] Change

[Correction content]

First, in step S331, the VRAM
The pixel data stored in the addresses 50-53 of 40 are stored and updated in the addresses 60-63, and the corresponding signal level is displayed in the vertical direction on the liquid crystal pixels LM60-63 of the matrix liquid crystal display unit 61 of the LCD 60. . Next, in step S332, the pixel data stored in the addresses 40-43 of the VRAM 40 is stored and updated in the addresses 50-53, and the signal level corresponding to the pixel data is vertically changed to the matrix liquid crystal display unit 61 of the LCD 60.
Liquid crystal pixels LM50-53. Further, in steps S333 to S336, the same processing is repeated, and addresses 30-33 and 20-2 of the VRAM 40 are repeated.
Pixel data stored in Nos. 3,10-13,00-03 are assigned addresses 40-43,30-33, respectively.
20-23, 10-13 are stored and updated, and the signal levels corresponding thereto are updated in the vertical direction in the liquid crystal pixels LM40-43, LM3 of the matrix liquid crystal display unit 61 of the LCD 60.
Display on 0-33, LM20-23, LM10-13 and return. Through the above processing, the display position of the signal levels of the reception signals of a plurality of frequencies displayed on the matrix liquid crystal display section 61 of the LCD 60 is shifted to the right by one step.

[Procedure 18]

[Document name to be amended] Statement

[Correction target item name] 0079

[Correction method] Change

[Correction content]

As shown in FIG. 22, first, step S4
In 01, it is determined whether or not the PTT switch SW1 is turned on, and when it is turned on, step S402
Then, the H-level TRSW signal is output to switch the transmission / reception changeover switch 10 to the contact b side to put it in the transmission state, and then the process returns. On the other hand, when the PTT switch SW1 is not turned on (N in step S401
O), in step S403, the L level TRSW signal is output to switch the transmission / reception changeover switch 10 to the contact a side to bring it into the receiving state, and in step S404, the L level ESQ signal is output to output the squelch switch 1
1 is turned off, and a low frequency signal is output to the speaker 13. Next, in step S405, the flag FS5S
= 1 is determined, and when FS5S = 1, the address 00 of the VRAM 40 is determined in step S406.
All the liquid crystal pixels of the matrix liquid crystal display unit 61 are turned off by clearing -63, the flag FS5S is reset to 0 in step S407, and then the process proceeds to step S408. On the other hand, if FS5S = 0 in step S405, the process directly proceeds to step S408.

[Procedure Amendment 19]

[Document name to be amended] Statement

[Correction target item name] 0080

[Correction method] Change

[Correction content]

Next, in step S408, it is determined whether or not the flag FUP = 1, and when FUP = 1, the pixel data Dcm is set to "0" in step S409.
1 ”is stored and the LCD 60 for indicating the center is displayed on the LCD 60.
The liquid crystal pixel of 3b is displayed on the liquid crystal, the scan search upward processing (see FIG. 23) is executed in step S410, and the process returns. On the other hand, in step S408, FUP = 0
, The pixel data Dcm in step S411
"10" is stored in the LCD, liquid crystal pixels of the center designating liquid crystal display unit 63c are displayed on the LCD 60, and step S412 is performed.
In the scan search downward processing (see FIG. 24), the process returns.

[Procedure amendment 20]

[Document name to be amended] Statement

[Correction target item name] 0081

[Correction method] Change

[Correction content]

The scan search unreceivable process (step S16) in FIG. 12 is performed in step S404 in FIG.
22 is the same as the scan search receivable processing (step S17) shown in FIG. 22 except that the ESQ signal of H level is output instead of L level. As a result, in the scan search mode and the unreceivable mode, the signal levels of a plurality of frequencies are displayed as in the scan search receivable process, but the low frequency signal of the received signal can be heard using the speaker 13. It is configured so that it cannot be done.

[Procedure correction 21]

[Document name to be amended] Statement

[Correction target item name] 0087

[Correction method] Change

[Correction content]

First, after the downward display data replacement process (see FIG. 21) is executed in step S511,
In step S512, the L-level ESQ signal is output, the squelch switch 11 is turned off, the low frequency signal of the modulated wave of the received signal can be received using the speaker 13, and the MPU 30 for standby processing The clock time Twp of the clock timer is reset to 0 seconds and the clock starts. Next, in step S513, the central local oscillation frequency data Df _LO is set to the local oscillation frequency data Df _L , and in step S514, the transmission / reception frequency data Df is set.
By setting f _CL in the register 43, it is displayed on the liquid crystal display 67 and the process proceeds to step S515.

[Procedure correction 22]

[Document name to be amended] Statement

[Correction target item name] 0094

[Correction method] Change

[Correction content]

In the search reception processing, the processing 5
00 to 504 are cyclically repeated, and when the level detection display process of one frequency is being performed, the signal levels of the other six frequencies are stored in the VRAM 40 and displayed in the previous level detection display process. Therefore, the matrix display section 61 of the LCD 60 displays the signal levels for all seven frequencies including the upper 3 frequencies, the transmission / reception frequency f _R, and the lower 3 frequencies, and thereby the step frequency Δf Then, the signal levels of a plurality of frequencies including the frequency band from the lowest frequency f _R −3Δf to the highest frequency f _R + 3Δf and having a reception bandwidth of 6Δf are displayed. Also, for example, process 500
Through 502 and processing 504 time (T0 + T1 + T2 + T
3) The time (T0 + T1 + T2 + T3) seconds of the processing 500 to 502 and the processing 504 (the squelch switch 11 is turned off in the processing 500 to 502 and the processing 504) by setting the second as small as possible and the waiting time Tw second sufficiently large. And the low frequency signal of the received signal is not output from the speaker 13), the low frequency signal of the modulated wave of the received signal of the transmission / reception frequency f _R is heard using the speaker 13 in steps S240 to S246. be able to.

[Procedure amendment 23]

[Document name to be amended] Statement

[Correction target item name] 0104

[Correction method] Change

[Correction content]

In the above embodiment, the VRAM 40, which is a memory for storing display data on the LCD 60, and the registers 41, 42, 43, 44 are provided separately from the MPU 30, but the present invention is not limited to this, and these memories can be used. A provided 1-chip microprocessor may be used.

[Procedure correction 24]

[Document name to be amended] Statement

[Correction target item name] 0107

[Correction method] Change

[Correction content]

In the memory channel mode processing (step S4) in the above embodiment, the signal levels of the received signals of a plurality of channels are displayed side by side in the ascending order of the channel numbers. You may display it side by side in descending order.

[Procedure correction 25]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 21

[Correction method] Change

[Correction content]

FIG. 21 is a flowchart of a subroutine of a downward display data replacement process of FIGS. 19 and 24.

[Procedure Amendment 26]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Codes] 1 ... Antenna, 2 ... RF amplifier, 3, 24 ... Mixer, 4 ... Local oscillator, 5 ... IF band pass filter, 6 ... IF amplifier, 8 ... FM demodulator, 9 ... Low pass filter , 10 ... Transmission / reception changeover switch, 11 ... Squelch switch, 12 ... AF amplifier, 13 ... Speaker, 14 ... High pass filter, 15 ... Squelch level adjusting attenuator, 16 ... Noise amplifier, 17 ... Detection circuit, 18 ... Waveform Shaping circuit, 19 ... Detection circuit, 20 ... A / D converter, 30 ... MPU, 31 ... Rotary encoder (RE), 32 ... Numeric keypad, 33 ... Step frequency selection key, 34 ... Frequency change unit selector switch, 40 ... VRAM , 41, 42, 43, 44 ... Registers, 50, 51, 52, 53, 54 ... LCD driver, 60 ... LCD, 61 ... Matri Liquid crystal display unit, 63a, 63b, 63c ... Center indicating liquid crystal display unit, 67 ... 7 segment liquid crystal display unit, OR1 ... OR gate, SW1 ... PTT switch, SW2 ... VFO mode / memory channel mode switch, SW3 ... Normal mode / Search mode selector switch, SW4 ... Receivable mode / Unreceivable mode selector switch, SW5 ... Normal mode / Scan search mode selector switch.

[Procedure Amendment 27]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

[Procedure correction 28]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 11

[Correction method] Change

[Correction content]

FIG. 11

[Procedure correction 29]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 22

[Correction method] Change

[Correction content]

FIG. 22

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyuki Nakayama 1-1-1, Mishimae, Takatsuki City, Osaka Prefecture Alinco Co., Ltd. (72) Inventor Tomoji Tsuguoki 1-1-1, Mishimae, Takatsuki City, Osaka Prefecture No. within Alinco Co., Ltd.

Claims (2)

[Claims] 1. A display device of a receiver for receiving a high-frequency signal at a predetermined reception frequency, wherein the reception frequencies are selectively switched in an arbitrarily set switching order, and the signal strengths of the plurality of received frequencies are received. Detecting and storing means for detecting and storing, and a display means having a plurality of display portions and displaying the stored signal intensities of a plurality of reception frequencies on the plurality of display portions respectively corresponding to the switching order, By shifting the signal strengths of the plurality of reception frequencies stored in the detection storage means in response to the change of the reception frequency, the display position of the signal strengths of the plurality of reception frequencies displayed on the display means is shifted. A display device for a receiver, comprising: a control means. 2. The display device for a receiver according to claim 1, wherein the detection storage means switches the reception frequency in ascending or descending order at a predetermined step frequency.