JPH06311543A - Output buffer type self-routing switch - Google Patents

Abstract

PURPOSE:To reduce adverse effect relating to the signal propagation of a transmitter caused by reflection noise and attenuation by providing plural data conversion circuits and plural address filters in the switch. CONSTITUTION:M sets of data conversion circuits SP10 are connected onto a time division multiplex TD-BUD. Thus, the transmission rate of the TD-BUS is MV and the entire switch rate is KMV. Thus, high rate data are sent stable. Moreover, number of data conversion circuits SP are set to a number by which adverse effect due to reflection noise and attenuation or the like in the signal propagation of a transmission line is not caused. Furthermore, when data to be sent on the plural TD-BUS are found out simultaneously, an address filter AF20 sends all the data to an output buffer 30 receiving them simultaneously.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ATM (Asynchr)
The present invention relates to a switch unit in a nose transfer mode switch, and more specifically to an output buffer type self-routing switch of an ATM switch.

[0002]

2. Description of the Related Art Recently, in digital communication, high speed
A demand for a broadband service is increasing, and a self-routing switch is proposed as a switch applied to a high-speed packet switching system that provides this service.
In addition, various media such as voice, data, images, and various information from high speed to low speed can be efficiently and comprehensively handled.
Research and development of TM exchanges are being conducted.

A conventional technique of this type is, for example, "Characteristic evaluation of cell distribution type ATM switch" by Aramaki et al.
(SSE91-111), "Switching Technology" by Shiraishi, and others.

FIG. 2 is a block diagram showing a configuration example of an output buffer type self-routing switch disclosed in the above-mentioned "Switching Technology" document. In the output buffer type self-routing switch, input ports # 1 to #N
The input data (fixed length packet called cell in case of ATM exchange) is time-division multiplexed and time-division bus TD.
-Output on BUS. The cell has an address area in which switching information called a header added to the information section is written.

The address filter AF connected to the time division bus TD-BUS checks the destination address stored in the header portion of the cell, and when the input cell is the cell to be transmitted from its own output terminal. ,
The cell is taken into the memory FIFO. Memory FIFO
The cells taken in are sequentially output from the output in the order of input.

[0006]

However, in the prior art having the above-mentioned structure, when the input data rate is V and the number of input ports is N, the data rate is NV on the time division bus TD-BUS. Therefore, when attempting to connect this to the memory FIFO via a plurality of address filters AF,
It is necessary to connect high-speed signal lines of speed NV to multiple points (N points).

The multi-connection to N points does not pose a problem in a relatively low-speed signal region where the noise on the signal line can be ignored and the multi-connection can be easily realized. However, in a multiplex bus used in an ATM switch that needs to handle high-speed signals, reflection and attenuation on the signal line cause a great obstacle to signal propagation.

Further, as another method for solving these problems, it is conceivable to prohibit multi-connection and to basically construct one-to-one connection. However, when the implementation is advanced with such a configuration, the time division bus TD-BUS must have N times as many output pins as it is connected to the address filter AF. This is a major disadvantage in terms of hardware implementation, promotion of LSI implementation, and mounting.

The present invention solves the problem of the prior art that reflection noise / attenuation on the signal line becomes an obstacle to signal propagation when multiple high-speed time division buses are connected, and the output is rich in hardware feasibility. An object is to provide a buffered self-routing switch.

[0010]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an output buffer type self-routing switch for switching input cell data, in which the input cell data is transferred to a plurality of time division multiplexed buses. It has a data conversion means for multiplexing, and a plurality of address filters connected to a plurality of time division multiplex buses and having a function of simultaneously selecting the cell data addressed to its own output transmitted on these buses.

[0011]

According to the present invention, the input cell data is multiplexed on a plurality of (K sets) slower time division multiplexed buses,
In addition, multiple (K
Data on the time-division multiplexed bus is received. As a result, the signal speed of the time division multiplex bus, which must be transmitted at the NV signal speed in the past, is reduced to NV / K per route, and the adverse effect on the signal propagation of the transmission path caused by the reflection nozzle / attenuation is reduced. .

[0012]

Embodiments of the output buffer type self-routing switch according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an output buffer type self-routing switch according to the present invention. This switch is used as a switch of an ATM switch, for example. Time division multiplexed bus TD-BUS # 1 to TD-BU
In S # K, a plurality of (M in this embodiment) data conversion circuits SP10- # 11-10 are provided in the same manner as in the prior art.
-# KM is connected.

Each data conversion circuit 10 also generates multiplexed data on the time division multiplexing bus TD-BUS in this embodiment. The difference between the present embodiment and the prior art is that the time division multiplexed bus TD-BUS is formed not by one but by a plurality (K in this embodiment).

In this way, in this embodiment, since the M data conversion circuits SP10 are connected on each time division multiplex bus TD-BUS, the transmission speed of the time division multiplex bus TD-BUS becomes MV, and the entire switch. The speed will be KMV. Therefore, in this embodiment, high-speed data transmission can be stably performed. The number of data conversion circuits SP10 connected to each time division multiplex bus TD-BUS is set to a value that does not cause adverse effects due to reflection noise, attenuation, etc. in signal propagation on the transmission path.

Individual output buffer FIFOs 30-1 to 30-N which are first-in first-out memories
Address filters AF20-1 to AF20-20 on the input side of
-N selects the data addressed to its own output from each time division multiplex bus TD-BUS and sends it to the output buffer / multiplexer circuit FIFO / MUX 30-1 to 30-N of the next stage.
That is, when the address filter AF20 simultaneously finds the data to be selected on the plurality of time division multiplex buses TD-BUS, it outputs the output buffer 30 which takes in all of them at the same time.

The output buffer FIFO 30 has a structure capable of receiving data from a plurality of time division multiplex buses TD-BUS at the same time. This is, for example, the time division multiplexed bus TD.
It can be realized by preparing the output buffer FIFOs 30 as many as the number of BUSs, and the output buffer FIFOs 30.
You may implement a multiplexing process in the input part of.

Although any of these can be selected, the physical location of the multiplex circuit MUX 30 changes depending on which method is used. That is, when a plurality of output buffer FIFOs 30 are prepared, the multiplexing circuit MUX30 is arranged in the subsequent stage of the output buffer FIFOs 30. Also,
When performing multiplex processing on the input side of the output buffer FIFO 30, the output buffer FIFO 30 is arranged in the preceding stage of the output buffer FIFO.

In either arrangement, the address filter AF20, the output buffer FIFO30, and the multiplex circuit MUX30 are physically close to each other, in other words, they can be configured as one functional group (which can be integrated into an LSI).
Therefore, even if a request for high-speed processing is made in this part, it does not hinder signal transmission. Rather, the effect of improving the signal transmission system by reducing the signal speed of the time division multiplexed bus TD-BUS becomes greater. After that, the data taken into the output buffer FIFO 30 is sequentially read out in the same manner as the conventional technique, and the data output lines (# 1 to #) are read.
N).

[0020]

As described above in detail, according to the present invention, in the ATM switch of the output buffer type, the function of multiplexing the input cell data on the plurality of time division multiplexing buses TD-BUS, and the output. An address filter (AF) unit, which is one element that constitutes a buffer, and a subsequent stage thereof are provided with a function of simultaneously capturing multiplexed data sent from a plurality of time division multiplex buses TD-BUS. As a result, it becomes possible to reduce the transmission speed of the time division multiplexed bus TD-BUS itself, suppress the noise of the signal which becomes a problem during high-speed bus transmission, and provide an output buffer configuration method with excellent transmission characteristics. The output buffer type self-routing switch which is highly versatile becomes possible. Also, with the increase in the possible transmission rate of the time division multiplexing bus TD-BUS itself, it becomes possible to provide an output buffer type ATM exchange having a throughput of K times that of the conventional one.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an output buffer type self-routing switch according to the present invention.

FIG. 2 is a configuration diagram of an output buffer type self-routing switch according to a conventional technique.

[Explanation of symbols]

10- # 11 to 10- # NM Data Converter (SP) # 1 to #K Time Division Multiplexing Bus (TD-BUS) 20-1 to 20-N Address Filter (AF) 30-1 to 30-N Output Buffer (FIFO), multiplex circuit (MUX)

Claims (3)

[Claims] 1. An output buffer type self-routing switch for switching input cell data, comprising: data conversion means for multiplexing the input cell data on a plurality of time division multiplexed buses; and a plurality of the time division multiplexed buses. Output buffer type self-routing switch which is connected to the bus and has a plurality of address filters having a function of simultaneously selecting the cell data addressed to the self-output transmitted on these buses. 2. The output buffer type self-routing switch according to claim 1, wherein the switch corresponds to the address filter with a first-in first-out memory and a multiplex circuit having a function of simultaneously receiving the cell data output from the address filter. And an output buffer type self-routing switch, in which cell data is transmitted to a data output line. 3. The output buffer type self-routing switch according to claim 2, wherein the switch is applied to an ATM switch.