JPH0631250U - FSK communication demodulator - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a demodulator capable of suppressing fluctuations in the pulse width of a demodulated signal with high accuracy. An FSK communication demodulator for demodulating a modulated signal whose phase is continuous at a carrier frequency change point by changing the demodulated signal after a time τ from the end of a modulated signal pulse width TB that first appears after the carrier frequency change point. In, a pulse width measurement circuit, a signal change point detection circuit, and a modulation signal pulse width T
A modulation signal pulse width T including B and a carrier frequency change point,
Time τ is calculated from constants C and D that are uniquely determined by the carrier frequency, and τ = when the wave carrier frequency changes in the decreasing direction.
C-2 × {T + TB}, and when the wave carrier frequency changes in the increasing direction, τ = D + T, an arithmetic circuit obtained by an approximate expression and a demodulation signal generating circuit are provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an FSK (Frequency Shift Keying) type communication device, and more particularly to an FSK communication demodulator having an approximate arithmetic circuit and highly accurately demodulating a communication signal.

[0002]

[Prior art]

 Generally, in FSK communication, the carrier frequency is set to 2200 Hz when the communication signal is “1” as shown in FIG. 3 for the communication signal (a) at the baud rate of 1200 bps, and (a) the communication signal. When the carrier frequency is "0", the carrier frequency is set to 1200 Hz, and at the changing point of the carrier frequency, a modulation method such as continuous phase is often used.

Conventionally, as a method of demodulating a modulated signal shown in FIG. 3B, an analog method such as passing through an edge detector and then passing through a low-pass filter has been used, but recently, the modulated signal is converted into an A / D signal. After conversion, a method of demodulating by digital signal processing is also used. As an example of the latter method, as shown in FIG. 4, (a) the change point of the communication signal, that is, (b) the frequency change points a, b, c, and d of the modulated signal are detected from the (b) modulated signal. The (c) demodulated signal which is the output is changed after τ0 to τ3 for a certain time from the edges of the modulation signal pulses T0 to T3 including the frequency change point.

FIG. 5 is a block diagram showing an example of a demodulator that realizes the above-described demodulation method. In FIG. 5, 1 is an A / D converter, 2 is an edge detector, 3 and 9 are counters, 4 and 8 are latches, 5 is a signal change point detector, 6 is a table using a storage device such as ROM, 7 Is a flip-flop circuit, 100 is a modulation signal, 101 is a sample clock, and 200 is a demodulation signal.

The modulated signal 100 is input to the A / D converter 1, the sample clock 101 is connected to the A / D converter 1, the clock input terminals of the counters 3 and 9, and the signal change point detector 5, The output of the converter 1 is connected to the reset terminal of the counter 3 and the load terminal of the latch 4 via the edge detector 2.

The output of the counter 3 is connected to the input terminal of the latch 4, and the output of the latch 4 is connected to the signal change point detector 5 and the table 6. The switching control signal of the demodulation signal which is one output of the signal change point detector 5 includes the frequency change point which is the other output of the signal change point detector 5 at the set terminal of the table 6 and the flip-flop circuit 7. The signals indicating the timing of the edges of the modulation signal pulse width are connected to the load terminals of the counter 9, respectively.

Further, the output of the table 6 is connected to the counter 9, the output of the counter 9 is connected to the reset terminal of the flip-flop circuit 7 and the load terminal of the latch 8, and the output of the flip-flop circuit 7 is passed through the latch 8. The demodulated signal 200 is output.

In the demodulator shown in FIG. 5, the modulation signal 100 is converted into a digital signal by the A / D converter 1, the change point of the modulation signal 100 is detected by the edge detector 2, and the counter 3 is detected by this change point signal. The pulse width of the modulation signal is measured by and is held in the latch 4. The signal change point detector 5 inputs only the modulated signal pulses T0 to T3 in FIG. 4 to the table 6 using a storage device such as ROM as an address, and outputs the table 6 from the time data τ0 in FIG. Get τ3. A flip-flop is provided by the point which changes the demodulated signal obtained by setting this time data in the counter 9 and down-counting, and the control signal which switches the demodulated signal from the signal change point detector 5 to "0" or "1". It controls the circuit 7 and the latch 8 and outputs the demodulated signal 200.

However, in the configuration of FIG. 5, a large storage device is required to increase the sampling frequency or to demodulate accurately, so that a chip area becomes large when the gate array or the like is used as an LSI. It was the cause. In order to solve such a problem, a demodulator equipped with an approximate arithmetic circuit as disclosed in Japanese Patent Application No. 3-233362 has been considered.

There is also a method of using the pulse values before and after the modulated signal to accurately determine the pulse of the modulated signal including the change point of the communication signal. FIG. 6 is a timing diagram showing the operation of such a demodulator. is there. In FIG. 6, (a) is a communication signal, (b) is a modulation signal, and (c) is a demodulation signal. Here, if the pulse width of 2200 Hz and the pulse width of 1200 Hz appear consecutively or one pulse later, it is assumed that there is a change point of the communication signal between them, and the modulation that appears first after detecting this change point. The demodulated signal is changed after a predetermined time has elapsed from the edge of the signal.

Since the phase is continuous at the change point of the communication signal as in the demodulator according to Japanese Patent Application No. 3-233362, if carrier waves of 1200 Hz and 2200 Hz are “f0” and “f1”, respectively, f0・ T0 + f1 ・ T1 = 1/2 (1) f0 ・ T3 + f1 ・ T2 = 1/2 (2)

Here, if Ta = T0 + T1 and "T1" is calculated from the equation (1), T1 = (f0 / (f0-f1)) Ta- (2 (f0-f1)) ^-1 (3) , And Tb = T2 + T3, if "T3" is calculated from the equation (1), T3 = (f1 / (f1-f0)) Tb- (2 (f1-f0)) ^-1 (4).

Further, since the change point of the communication signal and the change point of the demodulation signal must be a constant value, when this value is “C0” as shown in FIG. 6, T1 + 1 / 2f1 + τ1 = C0 (5) T3 + 1 / 2f0 + τ2 = C0 (6), substituting f0 = 1200, f1 = 2200, equations (3) and (4), τ1 = C1 + 1.2Ta (7) τ2 = C2-2.2Tb (8), Therefore, the approximate expression is τ1 = C1 + (T0 + T1) (9) τ2 = C2-2 × (T2 + T3) (10). However, "C1" and "C2" are constants.

“T0 + T1” and “T2 + T3” are modulation signal pulse widths each including a frequency change point. Therefore, when the modulation signal pulse width including the frequency change point is T, when the demodulated signal changes from "0" to "1", "τ = C1 + T", and the demodulated signal changes from "1" to "0". At this time, the time τ to the change point of the demodulated signal can be obtained by the calculation "τ = C2-2 × T". As a result, it becomes possible to perform demodulation with higher accuracy than the demodulator according to Japanese Patent Application No. 3-233362.

[0015]

[Problems to be solved by the device]

 However, in the method shown in FIG. 6, when the frequency of the sample clock is low, (C) the fluctuation of the pulse width of the demodulation signal becomes large. For example, if the frequency of the sample clock is 31. In the case of 25 KHz, as shown in FIG. 7, 7200 pulses are counted for 2200 Hz and 13 pulses are counted for 1200 Hz. Here, assuming that the accuracy of the modulation frequency is ± 1%, the pulse of 2200 Hz is counted 6 to 8, the pulse of 1200 Hz is counted 12 to 14, and the pulse including the change point of the communication signal is 6 to 14 As a result, the rate of change of the pulse width of the demodulated signal becomes + 20% to -16%.

Here, when the approximation formulas (9) and (10) are set to τ = 28-2 × T (11) τ = 7 + T (12), the minimum and maximum values of the pulse width of the demodulated signal are simulated. The value is 21 counts and the maximum value is 30 counts. That is, in the approximate expressions (11) and (12), the pulse width of the demodulated signal fluctuates up to 9 counts. Therefore, an object of the present invention is to realize a demodulator capable of suppressing fluctuation of the pulse width of the demodulated signal with high accuracy.

[0017]

[Means for Solving the Problems]

 In order to achieve such an object, according to the present invention, a modulation signal composed of two types of carrier frequencies, and the carrier frequency is continuously switched in phase at a signal change point of a binary communication signal which is an original signal. In the FSK communication demodulator for demodulation, the pulse width of the modulated signal is measured by changing the demodulated signal after a time τ from the end of the modulated signal pulse width TB that first appears after the carrier frequency change point. A pulse width measurement circuit, a signal change point detection circuit for detecting a change point of the carrier frequency from the pulse width measured by the pulse width measurement circuit, the modulated signal pulse width TB and the carrier measured by the pulse width measurement circuit The time τ is reduced by the wave carrier frequency from the modulation signal pulse width T including the frequency change point and the constants C and D uniquely determined from the two types of carrier frequencies. When it changes to the direction of τ = C−2 × {T + TB}, and when the wave carrier frequency changes to the direction of increase, τ = D + T. And a demodulation signal generation circuit for outputting the demodulation signal based on the output of the change point detection circuit.

[0018]

[Action]

 After the frequency change point of the modulation signal is detected, the time τ from the edge of the modulation signal pulse that appears first to the change point of the demodulation signal is approximated by the modulation signal pulse width T including the frequency change point using an approximate expression, and the demodulation signal To create.

[0019]

【Example】

Hereinafter, the present invention will be described in detail with reference to the drawings. In order to suppress the fluctuation of the pulse width of the demodulated signal, consider the following approximate expression. τ = C4-2 × {T + TB} (13) τ = C3 + T (14) Here, when the demodulated signal changes from “1” to “0”, the equation (14) changes the demodulated signal to “ The approximate expressions when changing from 0 "to" 1 "are shown. However, C4 = C2 + 2 × TB _C , where TB is the actual count value of 1200 Hz pulse, and TB _C is the central value which is the count value with high probability when counting 1200 Hz pulse. It represents.

FIG. 1 is a block diagram showing the configuration of an embodiment of the FSK demodulator for demodulating the modulated signal shown in FIG. 3 using the approximate expressions (13) and (14). Here, 1 to 3, 7 to 9, 100 and 101 have the same reference numerals as those in FIG. In FIG. 1, 4a, 4b and 4c are latches, 5 is a signal change point detector, 10 is a shifter for doubling the input data, 11 is a subtractor, 12 is a multiplexer, 13a and 13b are adders, and 102 is The output signal of the edge detector 2, 103 is a switching control signal of the demodulation signal, 104 is a signal indicating the timing of the edge of the modulation signal pulse width including the frequency change point, 105 and 106 are external input constant signals, and 200a is a demodulation signal. It is a signal. 1, 2 and 3 are pulse width measuring circuits 300, 4a to 4c and 5 are signal change point detection circuits 301, 10, 11, 13a and 13b are arithmetic circuits 302, 7, 8, 9 and 12 Respectively constitute the demodulation signal generation circuit 303.

The modulated signal 100 is connected to the A / D converter 1, and the sample clock is connected to the A / D converter 1, clock terminals of the counters 3 and 9, and the signal change point detector 5. Further, the output of the A / D converter 1 is connected to the reset terminal of the counter 3 and the load terminals of the latches 4a to 4c as the signal 102 via the edge detector 2.

The output of the counter 3 is input to the latch 4a, the output of the latch 4a is input to the latch 4b and the signal change point detector 5, and the output of the latch 4b is the input terminal of the latch 4c and the signal change point is detected. The output of the latch 4c is connected to the input of the adder 5 and one of the adders 13a and 13b, and to the other input of the adder 13a and the signal change point detector 5, respectively. External input constant signals 106 and 105 are input to one input of the subtractor 11 and the other input of the adder 13b, respectively.

The output of the adder 13 a is connected to the other input of the subtractor 11 via the shifter 10, and the outputs of the subtractor 11 and the adder 13 b are connected to the multiplexer 12, respectively. The output signal 103 of the signal change point detector 5 is connected to the set terminal of the flip-flop circuit 7 and the control terminal of the multiplexer 12, and the output signal 104 of the signal change point detector 5 is connected to the load terminal of the counter 9.

The output of the multiplexer 12 is connected to the input terminal of the counter 9, and the output of the counter 9 is connected to the reset terminal of the flip-flop circuit 7 and the load terminal of the latch 8. The output of the flip-flop circuit 7 is output as a demodulation signal 200a via the latch 8.

The operation of FIG. 1 will be described with reference to the timing chart of FIG. (A) In the modulated signal 100, the input edge is detected by the A / D converter 1 and the edge detector 2, and (c) the signal 102 is output. (C) The sample clock 101 between the pulses of the signal 102 is counted by the counter 3 and held by the latch 4a. Further, the data of the latch 4a shifts to the latch 4b and the latch 4c for each output pulse of the (c) signal 102, so that three kinds of count values are held.

The data held in the latches 4b and 4c in the arithmetic circuit 302 is added by the adder 13a, doubled by the shifter 10, and then subtracted from the external constant input signal 106 by the subtractor 11a. The calculation shown in the approximate expression (13) is performed. On the other hand, the data held in the latch 4b is added to the external constant input signal 105 by the adder 13b, and the operation shown in the approximate expression (14) is performed.

The data held in the latches 4a to 4c is input to the signal change point detector 5, the data held in the latches 4a to 4c are compared, and the 2200 Hz pulse and the 1200 Hz pulse are continuously output. The output signal 104 is output at the edge of the (b) modulated signal 100 that first appears after detecting this phenomenon or when it appears one pulse later. Further, when the communication signal is switched from "0" to "1", pulses are output to the signal 103 at the same timing as the signal 104.

One of the two types of data that has been approximately calculated by the arithmetic circuit 302 is selected by the signal 103, the data selected by the signal 104 is loaded into the counter 9, and the signal 103 is set in the flip-flop circuit 7. . When the down-counting is completed, the data of the flip-flop circuit 7 is latched by the latch 8 and output as the demodulation signal 200a.

Here, since the approximate expression (14) is the same as the approximate expression (9), let us consider the approximate expression (13). Substituting the constant “C4” into the equation (13) gives τ = C2 + 2 × TB _C −2 × {T + TB} = C2−2 × T + 2 × {TB _C −TB} (15).

As described with reference to FIG. 7, even with the same pulse, the counted value varies depending on the frequency of the sample clock and its accuracy. In such a case, when a pulse is counted short, the pulses before and after it are counted long. Immediately, if the pulse width T is counted short, the pulse width TB is counted long.

On the other hand, since the “{TB _C −TB}” term in the equation (15) is a deviation from the center value when counting pulses, if “TB” is counted shorter than the center value, then “{” T B _C -TB} "is a positive value, than the center value""if the count long" TB {TB _C -TB} "has a negative value.

As a result, if the expression (15) does not include the “{TB _C −TB}” term, the value of τ becomes large when the pulse width T is counted short, but at this time, the pulse width T B is counted for a long time, and "{TB _C -TB}" has a negative value, so it is corrected that the value of τ becomes large. Also, when the pulse width T is counted long pulse width TB is shorter count, "{TB _C -TB}" because a positive value, it is corrected to the value of τ is small.

For example, when the approximation formulas (13) and (14) are set to τ = 54-2 × {T + TB} (16) τ = 7 + T (17), the minimum and maximum values of the pulse width of the demodulated signal are simulated. The minimum value is 23 counts and the maximum value is 29 counts, and the change rate of the pulse width of the demodulated signal is ± 12%. That is, fluctuations in the pulse width of the demodulated signal can be suppressed.

[0034]

[Effect of device]

 As is clear from the above description, the present invention has the following effects. The time τ from the edge of the pulse of the modulation signal that first appears after detecting the frequency change point of the modulation signal to the change point of the demodulation signal is calculated from the pulse width of the modulation signal that includes the frequency change point of the modulation signal. By approximating with, it is possible to realize an FSK communication demodulator capable of suppressing the fluctuation of the pulse width of the demodulated signal.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of an FSK communication demodulator according to the present invention.

FIG. 2 is a timing diagram illustrating an operation of the communication demodulator of FIG. 1 according to the present invention.

FIG. 3 is a timing diagram showing an example of a modulation signal of conventional FSK communication.

FIG. 4 is a timing diagram showing an operation of a communication demodulator for conventional FSK communication.

FIG. 5 is a configuration diagram showing an example of a conventional communication demodulator for FSK communication.

FIG. 6 is a timing diagram showing another method of the communication demodulator of the conventional FSK communication.

7 is a timing diagram showing a problem of the demodulation method shown in FIG.

[Explanation of symbols]

1 A / D converter 2 Edge detector 3,9 Counter 4,4a, 4b, 4c, 8 Latch 5 Signal change point detector 6 Table 7 Flip-flop circuit 10 Shifter 11 Subtractor 12 Multiplexer 13a, 13b Subtractor 100 Modulation signal 101 sample clock 102, 103, 104 signal 200, 200a demodulated signal 300 pulse width measurement circuit 301 signal change point detection circuit 302 arithmetic circuit 303 demodulated signal generation circuit T pulse width of modulated signal including frequency change point TB detected frequency change point The pulse width of the modulated signal that first appears τ τ The time to the change point of the demodulated signal C, D A constant uniquely determined from two types of carrier frequencies

Claims (1)

[Scope of utility model registration request] 1. A modulated signal, which is composed of two types of carrier frequencies, and whose carrier frequency is continuously switched in phase at a signal change point of a binary communication signal which is an original signal, is provided after the carrier frequency change point. In a FSK communication demodulator that demodulates by changing the demodulation signal after a time τ from the end of the modulation signal pulse width TB that first appears, a pulse width measurement circuit that measures the pulse width of the modulation signal, and this pulse width measurement circuit A signal change point detection circuit for detecting a change point of the carrier frequency from the pulse width measured in 1., and a modulation signal pulse width T including the modulation signal pulse width TB and the carrier frequency change point measured by the pulse width measurement circuit, , And the constants C and D that are uniquely determined by the two types of carrier frequencies, when the time τ changes in the direction in which the wave carrier frequency decreases, τ = C−2 × {T TB}, when the wave carrier frequency is varied in the direction of increasing the tau = D +
An FSK communication demodulator, comprising: an arithmetic circuit that obtains an approximate expression of T, and a demodulation signal generation circuit that outputs the demodulation signal based on the outputs of the arithmetic circuit and the signal change point detection circuit.