JPH06314232A - Memory switching control circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a memory switching control circuit capable of performing exclusive control of a memory in a system in which one memory is accessed by two CPUs. [Configuration] When the request signal R2 and the lock signal LO are output from the CPU 2, the lock control circuit 9 outputs an exclusive request signal R3 to the F / F circuit 10. While the lock signal LO is being output, this exclusive request signal R
The output of 3 is continued. If the CPU 1 is not accessing the memory 8, that is, if the access permission signal E1 is not input to the terminal S of the F / F circuit 10, the access permission signal E
2 is output. While the access permission signal E2 is being output, C
Access to the PU1 is prohibited, the access permission signal E1 is not output from the F / F circuit 3, and this exclusive control is performed during the output of the lock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory switching control circuit, and more particularly to a memory switching control circuit capable of performing exclusive control for prohibiting access by CPUs other than the CPU currently being accessed in a system in which one memory is accessed by a plurality of CPUs. Regarding

[0002]

2. Description of the Related Art Conventionally, there has been proposed a memory switching control circuit for performing memory control for accessing one memory from two CPUs (Japanese Patent Laid-Open No. 58-86653). FIG. 5 is a block diagram of such a conventional memory switching control circuit. Reference numerals 21 and 22 denote CPUs, and 23 denotes a memory control unit. The CPUs 21 and CPUs are based on request signals output from the CPUs 21 and 22 and indicating access requests.
It is determined which one of 22 accesses the memory and outputs a control signal to a gate circuit described later.

Further, 25 and 26 are control signals output from the CPU 21 when the control signals are output from the memory control unit 23, a gate circuit for outputting an address to the memory, and 26 is a control signal output from the memory control unit 23. As a bidirectional buffer, a gate circuit for inputting / outputting data between the CPU 21 and the memory, 28 is a memory, 3
Reference numerals 2 and 33 denote gate circuits that output the control signal and the address output from the CPU 22 to the memory 28 when the control signals are output from the memory control unit 23, respectively.
Is a gate circuit that inputs and outputs data between the CPU 22 and the memory 28 as a bidirectional buffer when a control signal is output from the memory control unit 23.

A1, C1 and R1 are addresses output from the CPU 21, control signals and request signals, D1 is data exchanged between the CPU 21 and the memory 28, A2, C2 and R2 are addresses output from the CPU 22, Control signal, request signal, D2 is data exchanged between the CPU 22 and the memory 28, C
LK is a clock signal.

Next, as an operation of such a memory switching control circuit, an operation when the CPU 21 makes a memory access will be described first. When the CPU 21 makes an access, the CPU 21 outputs a request signal R1 indicating an access request. Then, the memory control unit 23 determines whether or not the CPU 22 is currently accessing the memory 28. If the CPU 22 is not currently accessing the memory, the memory control unit 23 permits the access of the CPU 21 and prohibits the access of the CPU 22. If the CPU 22 is accessing, the CPU 21 waits until the access is completed and permits the CPU 21 to access.

When permitting access of the CPU 21,
The memory control unit 23 outputs a control signal to the gate circuits 25, 26 and 27 at predetermined timings. Therefore, the gate circuits 25, 26, 27 are enabled, and the control signal C output from the CPU 21 is output.
1, the address A1 is output to the memory 28 via the gate circuits 25 and 26. Subsequently, the data D1 is exchanged between the CPU 21 and the memory 28 via the gate circuit 27.

Similarly, when the CPU 22 accesses the memory 28, when the request signal R2 is output from the CPU 22 and the memory controller 23 permits the access, the control signals are sent to the gate circuits 32, 33 and 34. Is output. Then, the control signal C2 and the address A2 output from the CPU 22 are output to the memory 28 via the gate circuits 32 and 33, and the data D2 is exchanged between the CPU 22 and the memory 28 via the gate circuit 33.

In such a memory switching control circuit, the request signals R1 and R2 are sent to the CPU 21 and 22 respectively.
Cycle (for example, 4 times the clock signal CLK in this example)
Clock minutes). So, for example, CP
Request signal R from CPU 21 during U22 access
When 1 is output, the access of the CPU 21 is prohibited for one cycle and the access of the CPU 21 is switched to after the cycle of the CPU 22 is completed. Further, since one instruction is normally composed in several cycles, the CPU 22
That is, the CPU 21 has been accessed several times before the completion of one instruction.

[0009]

Since the conventional memory switching control circuit is configured as described above, if one CPU accesses one instruction while another CPU accesses it, the data stored in the memory will be lost. May be destroyed 1
There is a problem in that exclusive control for preventing such data destruction cannot be performed by prohibiting access of another CPU during access of an instruction. In order to solve the above problems, it is an object of the present invention to provide a memory switching control circuit capable of performing memory exclusive control in a system in which one memory is accessed by two CPUs.

[0010]

According to the present invention, a CPU outputs a request signal indicating an access request and a lock signal indicating an instruction period, and when the request signal and the lock signal are input from the CPU, the lock signal is input during the input period. Controls the memory by determining which CPU to access based on the lock control circuit that outputs the exclusive request signal and the exclusive request signal output from the lock control circuit and the request signal output from another CPU, It has a memory control unit which prohibits access of another CPU while the CPU is accessing and the exclusive request signal is being output.

Also, a CPU outputs a request signal indicating an access request and a lock signal indicating an instruction period, and stops the output of the lock signal when the lock control abnormality signal is input, and the lock signal is input from the CPU. In this case, the lock time detection circuit that measures the input elapsed time and outputs the lock control abnormal signal when the time exceeds a predetermined time, and the CPU
When the request signal and the lock signal are input from the lock control circuit that outputs the exclusive request signal during the input period of the lock signal, and the exclusive request signal output from the lock control circuit and the request signal output from another CPU Based on which CPU is to be accessed, the memory is controlled to control the memory, and while the CPU is being accessed, the access of another CPU is prohibited while the exclusive request signal is output.

Further, instead of the lock time detection circuit, CP
When a lock signal is input from U, the number of times the request signal is output from the CPU is detected, and when the number of times is equal to or more than a predetermined number, a lock control abnormality signal is output and an access number detection circuit is provided.

Further, in place of the lock time detection circuit, when a reset request signal is output from another CPU, there is provided a reset circuit which outputs a lock control abnormal signal to the CPU which is outputting the lock signal.

[0014]

According to the present invention, when the CPU outputs the request signal and the lock signal, the lock control circuit outputs the exclusive request signal during the input period of the lock signal.
When the CPU of the memory controller permits the access of another CPU, the access of another CPU is prohibited while the exclusive request signal is output. When the lock signal is output from the CPU, the lock time detection circuit measures the elapsed time, and when the lock signal is output for a predetermined time or longer, the lock control abnormality signal is output. Then, in the CPU to which the lock control abnormality signal is input, the output of the lock signal is stopped and the exclusive control is released. Further, when the lock signal is output from the CPU, the number of times the request signal is output from the CPU is detected by the access number detection circuit, and when it exceeds the predetermined number, the lock control abnormality signal is output and the exclusive control is released. When a reset request signal is output from another CPU, a lock control abnormality signal is output from the reset circuit and the exclusive control is released.

[0015]

1 is a block diagram of a memory switching control circuit showing an embodiment of the present invention. 1, 2 is CPU, 3 is CP
A request signal R1 from U1 and a flip-flop circuit for CPU2 described later (hereinafter abbreviated as F / F circuit)
An F / F circuit that determines whether or not to permit access of the CPU 1 based on the output of the
4 is a delay circuit for delaying this access permission signal, 5, 6
Is C when the access permission signal is output from the F / F circuit 3.
A gate circuit which outputs the control signal C1 output from the PU1 and the address A1 to the memory, and 7 when the signal is output from the delay circuit 4, the data D1 between the CPU1 and the memory
Reference numeral 8 denotes a gate circuit for inputting and outputting.

Further, 9 is a lock control circuit for outputting an exclusive request signal for requesting access of the CPU 2 based on the request signal R2 from the CPU 2 and the lock signal output during one instruction of the CPU 2, and 10 is the lock control circuit. Exclusive request signal and F / output from the circuit 9
Based on the access permission signal from the F circuit 3, it is determined whether or not to permit the access of the CPU 2, and an F / F circuit that outputs the access permission signal, 11 is a delay circuit that delays this access permission signal, 12 and 13 are When the access permission signal is output from the F / F circuit 10, a gate circuit that outputs the control signal C2 and the address A2 output from the CPU 2 to the memory 8, and 14 is the CPU 2 and the memory 8 when the signal is output from the delay circuit 11. A gate circuit for inputting / outputting the data D2 between them, and 15 are inverters.

Further, E1 is an access permission signal output from the F / F circuit 3 for permitting access of the CPU 1 and inhibiting access of the CPU 2, and E2 permits access of the CPU 2 and inhibits access of the CPU 1. For F
An access permission signal output from the / F circuit 10, LO is a lock signal, and R3 is an exclusive request signal output from the lock control circuit 9. Then, the F / F circuits 3, 10
The delay circuits 4 and 11 and the inverter 15 constitute a memory control section that operates in the same manner as in the example of FIG.

Next, the operation of such a memory switching control circuit will be described. The operation when the lock control circuit 9 does not perform the exclusive control is similar to the example of FIG. 5 as follows. First, when the CPU 1 makes an access, the CPU 1 outputs a request signal R1. And CPU2
Does not access the memory 8, that is, if the access permission signal E2 is not input to the terminal S of the F / F circuit 3,
At the falling edge of the clock signal CLK, the access permission signal E1 is output from the terminal 1 of the F / F circuit 3, and the reply signal indicating that the access is completed is output from the terminal 0.

If the CPU 2 is accessing, it waits until the access is completed and waits for the next clock signal CL.
Similar output is performed at the falling edge of K. While the access permission signal E1 is being output, the request signal R2 is output from the CPU2.
Is output and the lock control circuit 9 outputs the exclusive request signal R3, the CP does not conflict with the access.
The access of U2 is prohibited so that the F / F circuit 10 does not output the access permission signal E2.

On the other hand, the gate circuits 5 and 6 to which the access permission signal E1 is input are in the enable state, and C respectively.
The control signal C1 and address A1 output from PU1 are output to the memory 8. When the access permission signal E1 is input, the delay circuit 4 delays it and outputs it to the gate circuit 7 for a predetermined time. Therefore, the data D1 is exchanged between the CPU 1 and the memory 8 via the gate circuit 7.

The CPU 1 sends the reply signal to the F / F circuit 3
After 1 wait (1 clock) from the output from, the cycle is ended. If the CPU 2 is not accessing the cycle, the cycle is ended with one wait of the minimum cycle.

Next, when the CPU 2 makes a memory access, it is basically similar to the case of the CPU 1, and the CPU 2
When the lock signal LO is not output from the lock control circuit 9, the lock control circuit 9 outputs the request signal R2 output from the CPU 2 to the F / F circuit 10 as the exclusive request signal R3.

If the CPU 1 is not accessing the memory 8, that is, if the access permission signal E1 is not input to the terminal S of the F / F circuit 10, the terminal 1 of the F / F circuit 10 rises at the rising edge of the clock signal CLK. The access permission signal E2 is output, and the reply signal is output from the terminal 0. If the CPU 1 is accessing, the same output is performed at the next rising edge of the clock signal CLK after waiting for the access to end. Similarly to the F / F circuit 3, while the access permission signal E2 is being output, the access of the CPU 1 is prohibited and the F / F circuit 3 outputs the access permission signal E1.
Is not output.

The gate circuits 12 and 13 to which the access permission signal E2 is input are enabled and output the control signal C2 and the address A2 output from the CPU 2 to the memory 8, respectively. In addition, the delay circuit 11
When the access permission signal E2 is input, the signal is delayed by a certain time and then output to the gate circuit 14. Therefore, the data D2 is transferred between the CPU 2 and the memory 8 via the gate circuit 14.
Are exchanged. The reply signal of CPU2 is F
The cycle is ended after one wait after the output from the / F circuit 10.

Therefore, when the lock signal LO is not output from the CPU 2, the same operation as in the example of FIG. 5 is performed. next,
When the request signal R2 and the lock signal LO are output from the CPU 2, the lock control circuit 9 outputs the exclusive request signal R3 to the F / F circuit 10 after the output of the reply signal from the F / F circuit 3 is completed, and the lock signal LO is output. The output of the exclusive request signal R3 is continued while is output. The operation after the exclusion request signal R3 is output is the same as above.

Therefore, even if the request signal R2 is output for only one cycle, the lock signal LO is output during one instruction that continues for several cycles, and as a result, the access permission signal E2 is also output during one instruction. Become CPU
It is possible to perform the exclusive control in which the access of the CPU 1 is prohibited during the period of 1 instruction of 2.

In this embodiment, the exclusive control can be performed only from the CPU 2 side, but the CPU 1 side can also perform the exclusive control by using a similar lock control circuit on the CPU 1 side. Also two CPUs
Alternatively, such exclusive control can be performed by three or more CPUs.

FIG. 2 is a block diagram of a memory switching control circuit showing another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. Reference numeral 16 denotes a lock time detection circuit which measures the output elapsed time of the lock signal LO and outputs a lock control abnormality signal to the CPU 2 when the output time exceeds a predetermined time.

The basic operation is the same as in the example of FIG. 1, but the lock time detection circuit 16 measures the elapsed time after the lock signal LO is output from the CPU 2, and it is equal to or longer than a predetermined time. Then, a lock control abnormality signal is output to the CPU 2. Then, when the lock control abnormality signal is output, the CPU 2 stops the output of the lock signal LO. Therefore, it is possible to prevent a decrease in system processing efficiency due to the exclusive control being released and the CPU 2 occupying the access to the memory 8.

FIG. 3 is a block diagram of a memory switching control circuit showing another embodiment of the present invention, and the same parts as those in FIG. 1 are designated by the same reference numerals. Reference numeral 17 denotes an access number detection circuit that detects the number of times the request signal R2 is output while the lock signal LO is being output, and outputs a lock control abnormality signal when the number of times exceeds a predetermined number.

The basic operation is the same as in the example of FIG. 1, but the access number detection circuit 17 detects the access number of the CPU 2 after the lock signal LO is output from the CPU 2 based on the request signal R2. If the access accompanied by such exclusive control continues for a predetermined number of times or more, a lock control abnormality signal is output. Therefore, like the example of FIG. 2, the exclusive control is released and it is possible to prevent a decrease in the processing efficiency of the system.

FIG. 4 is a block diagram of a memory switching control circuit showing another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. A reset circuit 18 outputs a lock control abnormality signal to the CPU 2 when the reset request signal is output from the CPU 1.

The basic operation is the same as in the example of FIG. 1, but the reset circuit 18 outputs a lock control abnormal signal to the CPU 2 when the CPU 1 outputs a reset request signal which is an emergency access request. Therefore, in the case of emergency access from the CPU 1, the exclusive control is canceled and the CPU
Memory access can be performed from 1.

In the examples of FIGS. 1 to 4, since exclusive control is performed based on the lock signal LO output during one instruction, exclusive control can be performed only for a maximum of one instruction. Therefore,
The lock time detection circuit 16, the access count detection circuit 17, and the reset circuit 18 shown in FIGS. 2, 3, and 4 hold the output of the lock signal LO output to the lock control circuit 9 once the lock signal LO is input, and output the lock signal LO. If the locks are released based on the output duration of the lock signal LO, the number of accesses of the CPU 2, and the reset request signal from the CPU 1, exclusive control of one or more instructions can be performed.

[0035]

According to the present invention, by using the lock control circuit, it is possible to perform the exclusive control for prohibiting the access of another CPU during the instruction period of the CPU.

Further, by using the lock time detecting circuit or the access number detecting circuit, it is possible to prevent the deterioration of the processing efficiency of the system due to the occupation of the memory access, and it is possible to smoothly perform the exclusive control on the memory.

When an emergency access is made from another CPU by using the reset circuit, the exclusive control can be canceled and the access can be made from another CPU.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory switching control circuit showing an embodiment of the present invention.

FIG. 2 is a block diagram of a memory switching control circuit showing another embodiment of the present invention.

FIG. 3 is a block diagram of a memory switching control circuit showing another embodiment of the present invention.

FIG. 4 is a block diagram of a memory switching control circuit showing another embodiment of the present invention.

FIG. 5 is a block diagram of a conventional memory switching control circuit.

[Explanation of symbols]

 1, 2 CPU 3, 10 F / F circuit 4, 11 Delay circuit 5-7 Gate circuit 8 Memory 9 Lock control circuit 12-14 Gate circuit 16 Lock time detection circuit 17 Access frequency detection circuit 18 Reset circuit

Claims (4)

[Claims] 1. A memory switching control circuit for accessing one memory from a plurality of CPUs, the CPU outputting a request signal indicating an access request and a lock signal indicating an instruction period, and the request signal and the lock signal from the CPU. A lock control circuit that outputs an exclusive request signal during the input period of the lock signal, and which CPU based on the exclusive request signal output from the lock control circuit and the request signal output from another CPU A memory control unit for controlling the memory by deciding whether or not to access, and for prohibiting access of another CPU while the exclusive request signal is being output during the access of the CPU. Control circuit. 2. A memory switching control circuit for accessing one memory from a plurality of CPUs outputs a request signal indicating an access request and a lock signal indicating a command period, and when a lock control abnormality signal is input. A CPU that stops the output of the lock signal; a lock time detection circuit that measures the input elapsed time when the lock signal is input from the CPU and outputs the lock control abnormality signal when the input elapsed time exceeds a predetermined time; When a request signal and a lock signal are input from the CPU, a lock control circuit that outputs an exclusive request signal during the input period of the lock signal, and an exclusive request signal that is output from the lock control circuit and that is output from another CPU Based on the request signal, determine which CPU to access to control the memory, Memory switching control circuit while the lock request signal in PU access is output, characterized in that it comprises a memory control unit to prohibit access another CPU. 3. The memory switching control circuit according to claim 2, wherein when a lock signal is input from the CPU instead of the lock time detection circuit, the number of output of the request signal from the CPU is detected and a predetermined number of times or more is detected. A memory switching control circuit having an access frequency detection circuit that outputs a lock control abnormality signal when 4. The memory switching control circuit according to claim 2, wherein when a reset request signal is output from another CPU instead of the lock time detection circuit, a lock control abnormality signal is output to the CPU that is outputting the lock signal. A memory switching control circuit having a reset circuit for outputting.