JPH06318931A - Error correction code transmission method - Google Patents

Abstract

PURPOSE:To enable error correcting encoding in a transmission system at a high bit rate by housing a vertical parity inspection code at a previously decided position inside a section overhead. CONSTITUTION:A digital signal frame is an STM(synchronous transport module) frame and is composed of the section overhead and a pay load. As the vertical parity inspection code, a 1/3 frame BIP-16 code is used. The vertical parity inspection code of two bytes is defined from the data of 808 bytes, and this is transmitted by using the 1/3 STM-1 frame. At such a time, this vertical parity inspection code is housed at the previously decided position inside the section overhead. Namely, the internal bytes of the 1/3 STM-frame are defined as an inspection target block, and vertical parity bytes are housed at any position of 'a', 'b' or 'c'. Thus, the bit rate is increased only by a horizontal parity inspection code.

Description

Detailed Description of the Invention

[0001]

The present invention is used for long-distance, large-capacity optical transmission. In particular, CCITT (International Telegraph and Telephone Advisory Committee)
STM (Sy defined in Recommendations G707, 708, 709)
Although it was invented to improve the frame, it can also be used for other systems.

[0002]

BACKGROUND OF THE INVENTION Optical fibers have been capable of transmitting gigabit per second digital signals over long distances of tens of kilometers due to their low loss, wide bandwidth and non-inductive nature. Before the optical amplifier was used, the optical power that can be input into the fiber was about several mW at the peak value, so that the long repeater interval was mainly achieved by reducing the fiber loss and increasing the sensitivity of the receiving section. . Furthermore, in recent years, the research and development of optical direct amplifiers have made rapid progress,
It is possible to input optical power of several mW or more into the fiber.

However, since the core portion where the optical power is concentrated in the optical fiber has a diameter of at most 10 μm, the optical power density in the core becomes abnormally high, and the signal waveform is deteriorated due to the influence of the nonlinear effect of the fiber material. The possibilities are emerging.
Although nonlinear effects have various manifestations, for example, stimulated Brillouin scattering distorts the waveform by backscattering the optical power in the fiber and substantially limits the optical power that can be input. The self-phase modulation is a phenomenon in which the spectrum of the optical signal spreads due to the fluctuation component of the intensity-modulated optical signal, and the signal waveform deteriorates due to dispersion of the optical fiber.

On the other hand, in order to realize the same code error characteristic at a higher bit rate, the number of photons per bit must be kept constant even in an ideal optical receiver having a constant noise power. I have to. That is, increasing the bit rate means increasing the transmission power peak value per bit. Such a contradiction between the optical power and the bit rate is essential, and suggests the limit of the transmission distance product by the single mode optical fiber.

The 1988 recommendation by CCITT states that
N in SDH (Synchronous Digital Hierarchy)
The STM is defined as a frame structure that an NI (Network Node Interface) should have, and is used in a high-speed and large-capacity digital transmission system. In this frame structure,
The STM-N frame has an S of 155.52 Mbit / s.
It is defined as an N-byte multiplex of a TM-1 frame (however, in detail, it is slightly different from a simple multiplex).
In this STM-N frame, in order to detect a code error that has occurred on the transmission path, even parity BIP (Bit Interl
eaved Parity) is defined and the transmission quality is monitored in real time. FIG. 13 shows BIP code positions in the STM-N frame. FIG. 13A shows the bit arrangement of the first layer, and FIG. 13B shows the bit arrangement of the second to Nth layers. For error monitoring between repeaters, the parity of every 8 bits of all bytes of the scrambled frame is BIP-
8 and the resulting 8-bit parallel parity is B1.
It is written as a byte in the next frame (FIG. 13A).
In addition, for error monitoring between terminal stations, BIP-24x
N is defined. This is the parity of every 24xN bits of all bytes of the frame except the 1st to 3rd lines of the section overhead before scrambling, which is BIP-24x.
It is defined as N, and the obtained 24 × N bit parallel parity is written in the next frame as B2 byte (see FIG. 1).
3 (a), (b)). Section overhead 1
The third to third lines may be rewritten by a regenerator in the middle, and are therefore excluded from the monitoring targets between the terminal stations. These BIP codes can detect an error occurring on the transmission path in real time, but have no correction function.

401 km, 622 Mbi by Gabra et al.
t / s and 357km, 2.488Gbit / s intensity modulation / direct detection non-relay transmission experiment uses an erbium optical amplifier and a 255/239 Reed-Solomon error correction code (PMGabla et al., "401 km. , 622 Mbit / s
and 357 km, 2.488 Gbit / s IM / DD Repeaterless Transm
ission Experiments using Erbium-Doped Amplifiers a
nd Error CorrectingCode ", Post deadline paper # 15
in the Topical Meeting on Optical Amplifiers and t
heir Applications, June 24-26, 1992). Redundancy is 1
4% and the transmission line rates are 710 Mb each
It / s has risen to 2.843 Gbit / s. In order to use an error correction code in a higher bit rate transmission system, a code which can be realized by a simple circuit and whose increase in transmission rate is suppressed as much as possible is required.

[0007]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method which is easy to implement, has a small increase in transmission rate, and is capable of performing error correction coding in a high bit rate transmission system. And

[0008]

An error correction code transmission method of the present invention is characterized by introducing a product code into an STM frame. That is, a parity check is performed on a predetermined multiple bit unit in a digital signal frame, a horizontal parity check code is added, and a parity check is performed on a multiple bit unit at every predetermined number of bits in the digital signal frame. In the error correction code transmission method in which the vertical parity check code is added, the digital signal frame is a frame of a digital synchronous network composed of a section overhead and a payload, and the vertical parity check code is placed at a predetermined position in the section overhead. It is characterized by accommodating.

As a vertical parity check code, CCITT
The BIP parity check code defined in the recommended STM frame may be used.

Depending on the method of horizontal and vertical parity checking, the horizontal parity check code as well as the vertical parity check code can be accommodated in the section overhead.

[0011]

In order to realize product coding while minimizing the increase in bit rate, which is considered to be the most severe constraint factor in ultra-high-speed communication, at least the vertical parity check code in the product code is included in the section overhead of the STM frame. Defined to accommodate. In the case of accommodating the vertical parity check code, the bit rate is increased only by the horizontal parity check code. If the horizontal parity check code can also be accommodated in the section overhead, the bit rate will not increase. Especially ST
The BIP-N code in the M frame is the vertical parity check code. At this time, one check circuit for the vertical parity check code can be omitted.

[0012]

1 is a format diagram showing an example of an error correction transmission line code for carrying out the present invention. here,
An example is shown in which a 16B2P code is used as the horizontal parity check code, that is, a code that adds 2 bits of horizontal parity in 16-bit units, and a 1/3 frame BIP-16 is used as the vertical parity check code.

This code performs a parity check in units of 16 bits in a digital signal frame, adds horizontal parity bits p ₁ and p ₂ , and performs a parity check in units of 404 bits every 18 bits in a digital signal frame. Vertical parity bits b ₁ ^{o to} b ₈ ^o , b ₁ ^{e to} b ₈
^It is obtained by adding ^e . b _i ^o represents the i th bit in the odd numbered byte and b _i ^e represents the i th bit in the odd numbered byte. The horizontal parity bit p ₁ is obtained by odd-numbered bits, and the horizontal parity bit p ₂ is obtained by even-numbered bits.

FIG. 2 is a format diagram showing another example of the error correction transmission line code. In this example, an 8B1P code is used as the horizontal parity check code, that is, a code in which one horizontal parity bit is added in 8-bit units. As the vertical parity check code, the 1/3 frame BIP-16 code is used as in the example of FIG.

Here, in order to correspond to FIG. 1, horizontal parity bits are shown by p ₁ and p ₂ , but in this case the horizontal parity bit p ₁ is parity by odd-numbered bytes, and the horizontal parity bit p ₂ is even-numbered bytes. Is the byte parity. In addition, a parity check is performed in units of 18 bits, and vertical parity bits n ₁ ^{o to} n _{8 are} added.
adding ^o or n ₁ ^e ~n ₈ ^e. n _i ^o represents the i th bit in the odd numbered byte and n _i ^e represents the i th bit in the odd numbered byte.

The resistance to 2-bit continuous error is as follows.
The symbols shown in FIG. 1 are clearly advantageous.

In these two examples, the [405/404] code is used as the vertical parity check code. This is S
It is suitable for inspecting 1/3 of the TM-1 frame. That is, 2-byte vertical parity check code N ₁ is defined from 808-byte data, and this is defined as STM-
It can be transmitted using 1/3 of one frame. In the present invention, this vertical parity check code N ₁ is accommodated at a predetermined position within the section overhead. In this way, the increase in bit rate is only due to the addition of horizontal parity bits. For this reason,
The bit rate increase in the above two codes is only 9/8 times as high as in the case without coding.

In order to suppress an increase in bit rate, it is possible to add a 1-bit horizontal parity check code in units of 2 bytes. In that case, it becomes 16B1P code,
The speed increase is 17/16.

FIG. 3 shows the accommodation position of the vertical parity byte in the STM-N frame. FIG. 3 (a) shows ST to be multiplexed.
The first layer of the M frame, (b), shows the accommodation positions in the second layer to the Nth layer. In the figure, the part surrounded by a thick frame is 1
This corresponds to an STM-1 frame of / 3 and the internal byte is the block to be inspected. Since 2 bytes are generated for the vertical parity byte, "a" or "i" shown in the figure,
Any position of "u", that is, second row fifth and sixth bytes, second row eighth and ninth bytes or third row eighth and ninth bytes of section overhead of 9 rows x 9 bytes, 5th row 5th and 6th bytes, 5th row 8th and 9th bytes or 6th row 8th and 9th bytes, 8th row 5th and 6th bytes, 8th row 8th and 9th bytes or Accommodates the 9th row, 8th and 9th bytes. In FIG. 3, the block to be inspected is shown as a partial frame starting from the beginning of the second line, but the length is 1 / of the frame.
3 and may start from any position as long as it is a partial frame that ends before the accommodating position of the vertical parity byte.

FIG. 4 shows a vertical parity check code [13
5/134] Shows the accommodating position of the vertical parity byte when the simple parity check code is used. Also in this case, as in FIG. 3, (a) is the first layer of the STM frame, and (b) is
Indicates the accommodation position in the second to Nth layers. In this example, there are 2 vertical parity bytes every 1/9 frame.
Since the bytes are generated, the nine sets of byte positions in the section overhead described above, namely "A" in the figure,
All bytes shown by "i" and "u" are used. Also in this case, the inspection target has only to have a length corresponding to one line of the STM-1 frame, and it is not necessary to start from the beginning of each line as shown in the figure.

In any of the above cases, the vertical parity check code is calculated in 1-byte units, and 9 bytes in the above-mentioned SOH are calculated.
It is also possible to use each half of the set of byte positions.

FIG. 5 shows the vertical parity check code CCITT.
An example with the same definition as the BIP-8 code in the recommendation will be shown. The horizontal parity check code is 8B2P.

If the vertical parity check code is defined as the BIP-8 code, the vertical parity check circuit can be used also as the BIP-8 code detection circuit. At this time, the vertical parity check code is a [2430N, 2430N-1] simple parity check code. However, N indicates the multiplicity of STM-N.

The horizontal parity bits p ₁ and p ₂ are
The parity for the odd-numbered and even-numbered bits for the horizontal parity check target may be obtained, or the parities of the first half and the second half may be used. In this case, the inspection target is 8 bits instead of 16 bits as shown in FIGS. It is also possible to define only 1 bit of parity for 8 bits to be inspected. While the bit rate increase when adding 2 bits of horizontal parity is 5/4,
In the case of only 1 bit, it becomes 9/8, which is advantageous in realizing a high speed circuit.

FIG. 6 shows the vertical parity check code as CCITT.
An example with the same definition as the BIP-24 code in the recommendation will be shown. In this case as well, as in the example shown in FIG. 5, the vertical parity check circuit can be used also as the BIP-24 code detection circuit. In this case, the vertical parity check code is [81
0,809] is a simple parity check code. This code is independent of STM-N multiplicity.

In this example, a 24B2P code is used as the horizontal parity check code. Horizontal parity bits p ₁ , p
₂ may be obtained by obtaining the parity for the odd-numbered and even-numbered bits for the horizontal parity check target, or may be the parity of the first half and the second half. The inspection target in this case is 24 bits. It is also possible to define only 1 bit of parity for 24 bits to be inspected. When the horizontal parity is added by 2 bits, the bit rate increase is 13/12, whereas when it is only 1 bit, it is 25/24. A 24B3P code in which horizontal parity is provided for each byte can also be used, but the bit rate increases by 9/8.

In the above example, the encoding for the vertical parity check is the product encoding of the simple parity check code.
Therefore, although it is possible to correct the occurrence of an error that becomes an independent error in each inspection target, a correct correction function cannot be guaranteed for errors that occur at the same time. However, since optical fibers generally provide a stable transmission path, errors are random even if they occur,
The error rate is very small.

FIG. 7 generally shows the error correction performance. As a result of calculation, the horizontal parity check target is fixed to 10 bits and the vertical parity check target is changed from 10 bits to 100,000 bits by one digit. Is illustrated.
The broken line is the asymptote on the low error rate side. As mentioned above, the errors that occur in optical fibers are random,
Moreover, the probability can be suppressed lower than that of the wireless transmission path. Therefore, if the triple error is negligible, when the transmission path error rate is Pe, the vertical parity check target bit number per parity bit is N _t , and the horizontal parity check target bit number N _y , the decoding error P _dec can be approximated by the following formula.

P _dec = (N _t × N _y ) · Pe ² This is indicated by the broken line in FIG. Since the first term on the right side is determined by the total number of codes to be inspected, it is referred to as a code error deterioration coefficient here. Table 1 shows the code error deterioration coefficient, the bit rate increase and the redundancy when the present invention is implemented.

[0030]

[Table 1] According to this table, the smallest decoding error degradation coefficient is
This is a case where the vertical parity check target is 134 bits and the 16B2P or 8B1P code is used for the horizontal parity check. At this time, the deterioration coefficient is 1072, and when the transmission path error rate is 10 ⁻⁸ , the decoding error rate is 1.07 × 10 ⁻¹³ . However, in this case, since the redundancy becomes 11%, the bit rate increases to 9/8. This may make the load on the ultra-high speed circuit too heavy.

Next, the decoding error deterioration coefficient is small when the vertical parity check target is 134 bits and the 16B1P code is used for the horizontal parity check. At this time, the redundancy is 5.9% and the bit rate is increased to 17 /
16 Also, the decoding error deterioration coefficient is suppressed to 2144.

When the vertical parity check code has the same definition as the BIP-n code in the CCITT recommendation, BI
The use of P-8 can reduce the decoding error degradation coefficient by about one digit as compared with the case of using BIP-8. When the BIP-24 code is used as the vertical parity check code and the 24B1P code is used as the horizontal parity check code, the decoding error deterioration coefficient 6456 can be realized with a redundancy of 4%.

In the above embodiment, the case where only the vertical parity check code is accommodated in the section overhead has been described, but the horizontal parity check code can also be accommodated in the section overhead depending on the parity check method. Such an example will be described with reference to FIGS.

FIG. 8 shows an example in which the 144B1P code is used for the horizontal parity check and the BIP-144 code is used for the vertical parity check. One STM frame includes 2430 bytes, the first 81 bytes of which is the section overhead, and the subsequent 2349 bytes is the payload. For this frame, the horizontal parity bits p ₁ to
p ₁₃₅ is obtained and vertical parity bits b _{1 to} b ₁₄₄ are obtained by checking the parity every 144 bits. The number of bytes required to transmit all these parity check codes is given by the horizontal parity check 13
A total of 35 bytes, 17 bytes containing 5 bits and 18 bytes obtained by the vertical parity check. Recommendation G
There is 36 undefined bytes in the section overhead of the STM frame defined in 708, 35 bytes of which can accommodate all parity check codes.
These parity check codes are the STM that was the subject of the check.
Placed in the next section overhead of the frame. Also, the horizontal parity bit p ₁₃₆ of the vertical parity byte itself can be accommodated in the 17-byte horizontal parity byte. Therefore, there is no increase in the transmission bit rate due to encoding, which is the same as the case without encoding.

FIG. 9 shows an example in which the 120B1P code is used for the horizontal parity check and the BIP-120 code is used for the vertical parity check. That is, horizontal parity bits p _{1 to} p ₁₆₂ are obtained by calculating the parity of continuous 120 bits, and vertical parity bits b _{1 to} b ₁₂₀ are obtained by checking the parity every 120 bits. The number of bytes required to transmit all of these parity check codes is 36 bytes, which is 21 bytes accommodating 162 bits obtained by the horizontal parity check and 15 bytes obtained by the vertical parity check. Therefore, all parity check codes can be accommodated in the section overhead. These parity check codes are placed in the next section overhead of the STM frame that is the check target. Also, the horizontal parity bit p ₁₆₃ of the vertical parity byte itself can be accommodated in the 21-byte horizontal parity byte. Therefore, there is no increase in the transmission bit rate due to encoding, which is the same as the case without encoding.

FIG. 10 shows the accommodation positions of the horizontal and vertical parity check codes in the STM-N frame. (A) shows the bit arrangement of the first layer, and (b) shows the bit arrangement of the second to Nth layers. That is, of the 9-row by 9-byte section overhead, the second-row second, third, fifth, sixth, eighth, and ninth bytes, third-row second, third,
5th, 6th, 8th and 9th bytes, 5th row 5th, 6th, 8th and 9th bytes, 6th row 2nd, 3rd, 5th,
6th, 8th and 9th bytes, 7th row 2nd, 3rd, 5th, 6th, 8th and 9th bytes, 8th row 2nd, 3rd,
A parity check code can be stored in the 36th byte of the 5th, 6th, 8th and 9th bytes and the 8th and 9th bytes of the 8th row.

FIG. 11 shows another accommodation position example of the horizontal and vertical parity check codes. (A) shows the bit arrangement of the first layer, and (b) shows the bit arrangement of the second to Nth layers. In this example, of the section overhead
The 5th row, 1st to 3rd, 5th, 6th, 8th, and 9th bytes, all the 6th to 8th bytes, and the 9th row's 8th and 9th bytes are used. At this time, the conventional BIP
The B2 byte portion inserted on the transmitting side as −N × 24 is also used, but this B2 byte can be calculated from the vertical parity code on the receiving side. For example, if 144B1P code is used for the horizontal parity check and BIP-144 code is used for the vertical parity check, the parity b _{6k + 1} (k = 0, 1, ... 2
3), for example _{b 1, b 7, b 13} , b 19, ..., performs a parity calculation for b _139, the resulting parity bits B _k
Thus, BIP-N × 24 can be obtained. Also,
If the 120B1P code is used for the horizontal parity check and the BIP-120 code is used for the vertical parity check, BIP-N × 24 can be similarly obtained from the parity of every 5 bits. Therefore, it can be used for the same error monitoring as in the past.

FIG. 12 shows the error correction performance when the horizontal parity check target is 144 bits and the vertical parity check target is 135 bits. The broken lines are the asymptotes on the low error rate side, and the decoding error P described with reference to FIG.
Represents _dec . In either example of FIG. 8 or FIG. 9, N _t × N
_y is 19440, which is a transmission line error rate of 10 ^−10.
It is shown that the error rate can be improved up to 10 ^-15.7 by the error correction function.

Since the coding example described with reference to FIGS. 8 to 12 accommodates the parity bit in a completed form for each layer of the STM-N frame, all S satisfying N ≧ 1 is satisfied.
The same can be done with TM-N frames.

[0040]

As described above, the error correction code transmission method of the present invention realizes product coding while minimizing bit rate information which is considered to be the most severe constraint factor in ultra high speed communication. This makes it possible to realize high transmission quality in an ultrahigh-speed optical digital transmission line in which SN is difficult to improve.

[Brief description of drawings]

FIG. 1 is a format diagram showing an example of an error correction transmission line code for implementing the present invention.

FIG. 2 is a format diagram showing another example of an error correction channel code.

FIG. 3 is a diagram showing a storage position of a vertical parity byte in an STM-N frame.

FIG. 4 is a diagram showing a storage position of a vertical parity byte when a [135/134] simple parity code is used as the vertical parity code.

FIG. 5 is a diagram showing an example in which a vertical parity check code has the same definition as a BIP-8 code in CCITT recommendation.

FIG. 6 is a diagram showing an example in which a vertical parity check code has the same definition as a BIP-24 code in CCITT recommendation.

FIG. 7 is a diagram showing error correction performance.

FIG. 8 is a diagram showing an example of an error correction channel code suitable for use in an STM frame defined in Recommendation G708, in which 144B1P code is used for horizontal parity check and BIP-144 code is used for vertical parity check. The figure which shows the frame structure in a case.

FIG. 9 is a diagram showing a frame structure in the case where an 120B1P code is used for the horizontal parity check and a BIP-120 code is used for the vertical parity check.

FIG. 10: STM- of horizontal and vertical parity check codes
The figure which shows an example of the accommodation position in N frame.

FIG. 11: STM- of horizontal and vertical parity check codes
The figure which shows another example of the accommodation position in N frame.

FIG. 12 is a diagram showing error correction performance when a horizontal parity check target is 144 bits and a vertical parity check target is 135 bits.

FIG. 13 is a diagram showing BIP code positions in an STM-N frame.

Claims (3)

[Claims] 1. A parity check is performed on a predetermined unit of a plurality of bits in a digital signal frame to add a horizontal parity check code, and a parity check is performed on a unit of a plurality of bits at a predetermined number of bits in the digital signal frame. In the error correction code transmission method in which the vertical parity check code is added, the digital signal frame is a frame of a digital synchronization network composed of a section overhead and a payload, and the vertical parity check code is added in advance in the section overhead. An error correction code transmission method characterized in that the error correction code is stored in a predetermined position. 2. The vertical parity check code is CCITT.
The error correction code transmission method according to claim 1, which is a BIP parity check code defined in an STM frame according to Recommendation G708. 3. The digital signal frame is CCIT
2. The error correction code transmission method according to claim 1, wherein the error correction code is an STM frame defined by T recommendation G708, and the horizontal parity check code is accommodated in a predetermined position in the section overhead together with the vertical parity check code.