JPH0631984B2 - Musical sound generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone generator, and more particularly to a musical tone generator that manipulates the shape of a musical tone waveform and changes it with time to simulate a natural musical instrument sound.

Conventional configuration and its problems Conventionally, to simulate natural musical instrument sounds, a sine wave synthesis method, a frequency modulation method, a subtraction method (mainly analog processing such as VCO, VCF, VCA However, there are problems that the circuit scale is large and it is difficult to realize, and that there is a limit in the method.

OBJECT OF THE INVENTION It is an object of the present invention to provide a musical tone generating apparatus capable of simulating a natural musical instrument sound with a simple structure and producing a sound with no turbidity.

According to the musical sound generating apparatus of the present invention, at least two or more musical sound waveforms among a plurality of musical sound waveforms from the start of musical sound generation to the end of sound generation are independently prepared for each musical range, and the selected and extracted musical sound waveforms. , A data memory unit for storing control data used when forming a synthesized waveform using, a note clock generation unit for determining a tone scale, and an output signal of the note clock generation unit and the data memory unit based on range specification data. A data reading section for reading two waveform sample data and control data from the waveform reading section, a waveform calculating section for obtaining combined waveform sample data using the two waveform sample data and control data read by the data reading section, and the waveform calculation The digital output signal of the unit is provided with a conversion unit for converting the signal to an analog signal so that a tone waveform is generated. The configuration is such that the shape of the musical tone waveform can be changed with time to generate a musical tone waveform close to that of a natural musical instrument, and the aliasing components that occur and sample wave components that occur due to quantization are all harmonics of the fundamental frequency. You can eliminate the noise by matching the waves.

Description of Embodiments An embodiment of the present invention will be described below with reference to the drawings. First, the principle of the present invention will be described. FIG. 1 shows a musical tone waveform of one cycle of a musical tone which is discretely extracted. The relationship between the passage of time from the start of pronunciation and the tone waveform is shown below.

As can be seen from FIG. 1, the shape of the musical tone waveform changes over time. The present invention focuses on the point that the shape of a musical tone waveform changes with time, and generates a musical tone like a natural musical instrument by changing the shape of a waveform with time.

Description of contents stored in data memory FIG. 2 shows an example of the envelope envelope state of the musical tone waveform from the start of sound generation to the end of sound generation. From the start of sounding of the envelope envelope shown in FIG. 2 to the end of sounding, it is divided into I (I = 0, 1, ..., I, ..., I-1). Then, one period of the musical tone waveform selected and extracted from each division point is divided into N portions. FIG. 3 shows an example of the musical tone waveforms selectively extracted.
N waveform sample values obtained by dividing one period of the extracted I musical tone waveforms into N, that is, N × I waveform sample values, and control data used to generate a musical tone (in the present invention, I am considering the control data for insertion)
And are stored in the data memory.

Description of Waveform Interpolation Method As a waveform interpolation method, i + 1 (i = 0, 1, 2, ..., I-1) from sample wave positions i selected by I division and extracted
It is assumed that one period of the musical tone waveform repeats M times and the virtual sample value existing between the waveform samples f (X _{i, n} ) and f (X _{i + 1, n} ) Is used to virtually calculate a waveform sample value at a virtual sample point to obtain an approximate value.
The interpolation formula is shown below.

i is a sample position extracted by I division and is a waveform number. (I = 0, 1, 2, ..., I-1) m represents a position in which the waveform number i to i + 1 is being repeated M times. (M = 0,
1, 2, ..., M-1) n is a waveform sample NAND at a sample position obtained by dividing one period of the tone waveform into N.

(N = 0, 1, 2, ..., N-1) FIG. 4 (a) shows an example of interpolation using the equation (1). As can be seen from the figure, discontinuity occurs at the joint between the waveforms. When the level difference between the discontinuities is large, it may cause a hearing problem as an unnecessary noise component. Therefore, in this embodiment, a correction term is added to the equation (1) to prevent the occurrence of discontinuities as shown in FIG. 4 (b). An interpolation formula in which a correction term is added to formula (2) is shown.

Description of the method of adding envelopes There are two types of musical sounds: organ type envelopes and piano type envelopes. FIG. 5 shows an example in which organ type and piano type envelopes are added. In the figure, (a) is an organ type, and (b) is a piano type.

In this explanation, unlike the above, the waveform stored in the data memory is not the waveform until the end of sounding, but the steady part of the musical tone or the place where the waveform shape is stable, and the subsequent waveform generation is stored in the data memory. The last stored waveform shall be used repeatedly.

Description of Organ Type When the key signal is turned on at point A in FIG. 5, the waveform data in the data memory is used to perform waveform interpolation to synthesize a musical tone. Then, when the time advances to point B, the final waveform data is obtained, and thereafter, the final waveform is repeatedly generated. After that, when the key signal is turned off at the point C, the envelope signal has an attenuation characteristic and the output waveform is attenuated.

Description of the piano type When the key signal is turned on at point A in FIG. 5, the waveform data in the data memory is used to perform waveform interpolation to synthesize a musical tone. Then, when it goes to point B, it becomes the final waveform data,
After that, the final waveform data is repeatedly used, the envelope signal becomes in the attenuation characteristic state, and the output waveform attenuates in accordance with the attenuation characteristic.

Explanation of pitch generation method To determine the scale, a clock signal corresponding to 12 scales is generated. Regarding the octave relation, the octave relation pitch is generated by changing the number of samples of one period of the tone waveform stored in the data memory.

If the C ₀ note is 512 samples, the scale clock signal is 32.
703Hz x 512 samples ≒ 16.74KHz. Table 1 shows the scale clock frequencies, and Table 2 shows the number of waveform samples and the octave relationship.

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram of an electronic musical instrument which employs the musical sound generating apparatus of the present invention. (601) is the keyboard section (KB), (602) is the operation section (TAB) that is composed of on / off switch for tone tabulation switch, vibrato effect, on / off switch for glide effect, etc., and (603) is the central processing unit (CPU). ), Similar to those used in computers, etc., (6
04) is a readable / writable storage device (random access memory called RAM), (605) is a read-only storage device (seed only memory called ROM) that stores a program that determines the operation of the CPU (603), Reference numeral (606) is a ROM that stores waveform sample data for synthesizing musical tones, control data for waveform interpolation, and the like. (607) is ROM
A tone generation unit that generates a tone using the waveform sample data and control data stored in (606) is a filter that removes sampling noise (608), and an electroacoustic transducer (609).

Keyboard part (601), operation part (602), CPU (603), RAM (604), ROM
(605) and (606) and the tone generating section (607) are connected by a data bus, an address bus and a control line. In this way, the data bus and The method itself for connecting the dress bus and the control line is a known method as a construction method centering on a minicomputer or a microcomputer. About 8 to 16 data buses are used, and data is transmitted and received on this bus line not in one direction but in multiple directions in a time division manner. A plurality of address buses, for example, 16 are also prepared. Normally, the CPU (603) outputs the address code, and the other parts receive the address code. Control lines are usually memory request line (▲ 詔 ▼), I / O request line (▲)
▼), lead wire (▲ ▼), write wire (▲ ▼), etc. are used.

▲ ▼ indicates reading / writing memory, ▲
▼ indicates that the contents of the input / output device (I / O) are taken out, ▲ ▼ indicates the timing to read data from the memory or I / O, and ▲ ▼ indicates the timing to write data to the memory or I / O. . Microprocessor Z80 manufactured by Zylog Co., Ltd. can be used as such a control line.

Next, the operation of the electronic musical instrument shown in FIG. 6 will be described. Keyboard part (6
01) is configured so that a plurality of key switches are divided into a plurality of groups and the ON / OFF states of the key switches in the group can be collectively sent to the data bus. For example, in the case of a 61-key keyboard, it is divided into 10 groups of 6 keys (half octave) and 11 groups of 1 key, and one address code is assigned to each group. An address code indicating one of the above groups arrives on the address line, and signals ▲ ▼ and ▲
When ▼ is applied, the keyboard section (601) decodes the address code and outputs 6-bit or 1-bit data indicating ON / OFF of the key switch in the corresponding group to the data bus. These can be configured using a decoder, a bus driver and some gate circuits. Operation part
Of the (602), the doublet switch is the keyboard
A configuration similar to (601) can be adopted.

The CPU (603) reads the instruction code from the address of the ROM (605) corresponding to the code of the program counter in the CPU (603), decodes it, and performs arithmetic operations, logical operations, reading and writing of data, and the contents of the program counter. Performs operations such as jumps on orders due to changes. The procedures for these operations are written in the ROM (605). First, the CPU (603) is RO
The command for fetching the data of the keyboard section (601) is read from M (605), and the code indicating ON / OFF of each key of the keyboard section (601) is fetched for each group. Then, the depressed key code is assigned to a finite channel of the tone generation unit (607), and tone generation data corresponding to the key code is transmitted.

Next, the CPU (603) sequentially reads a group of instructions for fetching data from the operation unit (602) from the ROM (605), decodes them, and decodes the address code and control signal corresponding to the operation unit (602). ▼ and ▲ ▼ are output, a code expressing the state of the switch of the operation unit (602) is output to the data bus, and the code is read into the CPU (603). Based on the data read into the CPU (603), the tone color is selected and predetermined effect control data is generated, and the tone color selection data is sent to the ROM (606) and the effect control data is sent to the musical tone generating unit (607). The method of assigning the depressed key code to the finite channel of the musical sound generating section (607) is known as a generator assigner function.

The tone generator (607) fetches predetermined waveform sample data and control data from the tone synthesis data ROM (606) based on the tone generation data supplied from the CPU (603) and performs waveform interpolation processing to perform tone waveform Is generated, and a musical sound is generated from the electroacoustic transducer (609) via the filter (608). In addition,
The internal processing of the musical sound generating unit (607) is as described above.

FIG. 7 shows a time chart when the data is supplied from the CPU (603) to the musical sound generating unit (607). I / O to address bus
It supplies the port address and the tone generation data and effect control data to the data bus. Then, at the timing when the control signals ▲ ▼ and ▲ ▼ change from the logic low level (hereinafter abbreviated as “O”) to the logic high level (hereinafter abbreviated as “1”), the channel specified by the I / O port address is changed. Latch the contents of the data bus.

Next, various data supplied to the musical sound generating unit (607) will be described.

Table 8 shows the contents of I / O port addresses and various data. The I / O port address is displayed in hexadecimal. The data corresponding to the I / O port addresses (00) ₁₆ to (07) ₁₆ are musical tone generation data for eight channels, that is, eight tones can be generated. The I / O port address (08) ₁₆ is sustain data, and designates the attenuation characteristic of the envelope signal described in FIG. I / O port address (09)
Reference numeral ₁₆ is damper data that is effective when the envelope characteristic is a piano type, and designates the attenuation characteristic of the envelope signal like the sustain data. I / O port address
(OA) ₁₆ is beat data for designating a frequency shift when two musical tones are generated. The I / O port address (OB) ₁₆ is effect control data, and is composed of a vibrato on / off signal and a glide on / off signal.

Table 4 shows the composition of the tone generation data. Bit positions D0 to D3 are note clock designation data for designating scale frequencies. Bit position D4 D6 are waveform sample number designation data for designating the generated sound range. The bit position D7 is a key on / off signal associated with the on / off operation of the key switch, which is "0" when it is off and "1" when it is on.

Table 5 shows the code contents of the waveform sample number designation data SD0 to SD2 and the number of samples in one cycle of the waveform designated by the code. Waveform sample number specification data SD is (000) ₂ to (111) ₂
Up to 8 types of waveform sample numbers can be designated. In this embodiment, 512 to 4 samples are designated.

Table 6 shows the relationship between the contents of the chords represented by the note clock designation data ND0 to ND3 and the designated scale designated by the chords.

Table 7 shows the structure of the effect control data. The bit position D0 is a vibrato on / off signal VIB, which is "0" when the vibrato on / off switch in the operation unit (602) is off and "1" when it is on.

Bit position D1 is the delay vibrato on / off signal DV
IB, delay vibrato effect control signal The delay vibrato on / off switch in the operation unit (602) is "0" when it is off and "1" when it is on.

Bit position D2 is ground on / off signal GL
It is "0" when the ground switch in (602) is off and "1" when it is on.

Bit position D3 is organ type / piano type designation signal OPS
In this case, the envelope characteristic is designated, which is "0" for the organ type and "1" for the piano type.

The bit position D4 is a damper on / off signal DMP, which is effective only when the envelope characteristic is a piano type, and is "0" when the damper is off and "1" when the damper is on.

Bit position D5 is the generator assigner operation mode signal
In GAM, it is a designated signal when two channels are used to generate a tone with one key. When the GAM signal is "0", one channel uses one channel (eight notes are generated), and when "1", it is 1
Key 2 channel is used (4 sounds are generated).

FIG. 8 is a block diagram of the musical sound generating unit (607). In FIG. 8, (801) is a main oscillator, (802) is a sequencer for controlling the operation contents of the tone generating section (607), and (803) is an input register for latching various data supplied from the CPU (603). Department, (8
(04) is a timer, (805) is a comparison register section, (806) is a frequency data processor (hereinafter abbreviated as FDP) that generates frequency data corresponding to the frequency to be sounded, and (807) is described in (2) above. ) Is a waveform data processor (hereinafter abbreviated as WDP) that performs the waveform interpolation processing of Eq.
Data read processor (hereinafter abbreviated as DRP) that reads waveform sample data and control data from 6), (809)
Is a read pulse forming unit that generates a pulse signal of a predetermined pulse width, (810) is a calculation request flag generating unit that requests the WDP (807), DRP (808), and the like to perform arithmetic processing, and (811) is an analog digital signal. The digital / analog converter (abbreviated as DAC hereinafter) for converting to a signal, (812) is composed of two analog switches and one capacitor per channel, and an analog buffer memory section for holding analog signals, (813) Is the integrator.

In the above configuration, (804) (805) (806) (810) constitutes a note clock generation unit that determines the tone scale, and based on the output signal, the DRP (808) that is the data read unit is the musical tone synthesis data ROM. Predetermined data is read from (606).

In addition, the input register (803), comparison register (805), FD
P (806), WDP (807), DRP (808), calculation request flag generator (8
In step 10), the sequence of processing is determined by the sequencer (802).

When the tone generation data is supplied from the CPPU (603) to a predetermined channel, for example, the channel 1, the FDP (806) and WDP (807) are input from the input register unit (803) at a predetermined timing determined by the sequencer (803). , DRP (808) is supplied with tone generation data. Then, the DRP (808) reads the waveform sample data and the control data from the music composition data ROM (606). Then, f (X _{i, n} ) shown in the equation (2) is supplied as data WDI and f (X _{i + 1, n} ) is supplied as data WDII to the WDP (807). Further, the numerator term of the interpolation coefficient shown in the equation (2) based on the read control data is supplied to the WDP (807) as data MLP. When the final waveform data is reached, the WEF signal indicating the final waveform data is supplied to the WDP (807).

In WDP (807), data WDI, WDI supplied from DRP (808)
Using I and MLP, perform the waveform calculation process of equation (2) and perform DAC (811)
Supply to. Then, in the DAC (811), the digital signal supplied from the WDP (807) is converted into an analog signal and supplied to the analog buffer memory section (812) as an analog signal, and the capacitor charge corresponding to the channel 1 is stored. .

On the other hand, in the FDP (806), frequency data based on the tone generation data supplied from the input register unit (803) is generated and supplied to the register corresponding to the channel 1 of the comparison register unit (805). Then, the data supplied to the comparison register (805) is compared with the time data supplied from the timer (804), and if a match is detected, a match pulse is read out and a calculation request flag is output with the pulse forming unit (809). Supply to the generation unit (810).

Then, the read pulse forming unit (809) generates a read signal having a predetermined pulse width and supplies the read signal to the analog buffer memory unit (812). Analog buffer memory section (81
The charge stored in the capacitor corresponding to the channel 1 in 2) flows into the integrator (813) by the read signal.

In the calculation request flag generator (810), the next waveform sample, that is, the virtual sample point Generate and hold a calculation request flag for calculating Then, when the processing timing again becomes channel 1,
Since the calculation request flag is generated, the waveform interpolation processing is performed in the same manner as described above, and the electric charge is stored in the capacitor in the analog buffer memory unit (812). After that, waveform interpolation processing is performed corresponding to the calculation request flag, and a musical tone waveform is generated.

The charge stored in the capacitor is And the sample waveform value obtained this time It corresponds to the difference with. Then, by the integrator (813),
Waveform sample value obtained this time Will be restored. Analog buffer memory section (8
12) and the operation around the integrator (813), see Japanese Patent Application No. 57-12.
6413 “Waveform readout device”.

FIG. 9 is a block diagram of a specific example of the sequencer (802). In the figure, (901) is a two-phase clock generator that generates two-phase clock signals φ1 and φ2, (902) is an 11-ary counter that determines the operation sequence per channel, and (903) is the current arithmetic processing. A counter that generates a channel code that is running, (904) is a ROM that stores the operating procedure, (905)
Is a decoder. FIG. 10 shows a timing chart of the sequencer (802).

A master clock (MCK) signal is supplied from the main oscillator (801) to the two-phase clock generator (901). 2-phase clock generator (90
In 1), two-phase clock signals φ1, φ as shown in Fig. 10
2 is generated. The signal φ1 is supplied to the 11-ary counter (902) and the counter (903).

The 11-ary counter (902) has a 4-bit configuration, and the count-up processing is performed at the timing when the signal φ1 changes from "0" to "1", and the output signal becomes (1111) ₂ .
Next, when counting up, it is set to (0101) ₂ . As a result, the output signal of the 11-ary counter (902) becomes 11 states, that is, (0101) ₂ to (1111) ₂ . This is used as an instruction step signal.

The counter (903) has a 3-bit configuration, and the count-up processing is performed every time the output signal of the 11 counter (902) changes from (1111) ₂ to (0101) ₂ . As a result, the output signal of the counter (903) is in the state of 8, that is, (000) ₂ to (11
1) ₂ This is used as a channel code.

The ROM (904) reads the instruction code based on the instruction step signal supplied from the 11-decimal counter (902), and the decoder (9
Supply to 05). The decoder (905) decodes the instruction code supplied from the ROM (904) and supplies a processing control signal to each unit.

As a result, the calculation time per channel becomes 2.75 μs, and each arithmetic processing is performed in 11 instruction steps. Then, the calculation timing is returned every 22 μs.

FIG. 11 shows a block diagram of a specific example of the analog buffer memory unit (812). In the figure, (1101) is input, (1102) an output terminal, (1103) - (1108) the analog switch, C ₁ -C ₈ denotes a capacitor.

The signals AW1 to AW8 supplied to the gate inputs of the analog switches (1103) (1105) (1107) are supplied from the WDP (807). The signals AR1 to AR8 supplied to the gate inputs of the analog switches (1104) (1106) (1108) are supplied from the read pulse forming section (809).

The analog signal converted by the DAC (811) is applied to the input terminal (1101) and supplied to the analog switches (1103) (1105) (1107). If the data corresponds to the channel 1, only the analog switch (1103) is turned on and the input terminal (110
A charge corresponding to the analog signal applied to 1) is stored in the capacitor C ₁ .

After that, the read pulse AR1 corresponding to the channel 1 is output from the read pulse generator (809) to the analog switch (1104).
When supplied to the gate input of, the electric charge stored in the capacitor C ₁ is supplied to the integrator (813) via the output end (1102).

Since the analog switches (1103) (1105) (1107) are synchronized with the operation timing of the WDP (807), a plurality of analog switches cannot be turned on at the same time. Since the analog switches (1104) (1106) (1108) are turned on in synchronization with the scale frequency, a plurality of analog switches can be turned on at the same time.

FIG. 12 is an internal operation timing chart of the musical sound generating unit (607). Figure 12 shows the timing for four channels.

Explanation of abbreviations in the figure CRF is a calculation request signal for each channel. Then, the request start time point is synchronized with the coincidence signal supplied from the comparison register unit (805). That is, it is synchronized with the scale frequency. For example, in the C scale, it is 59.74μ.
It occurs every s.

CLC indicates the waveform calculation timing.

The DAC is an analog buffer memory (812) via the DAC (811).
The timing to store the charge in the internal capacitor is shown.

OTC is a timing at which the electric charge stored in the capacitor in the analog buffer memory (812) is supplied to the integrator (813), and is generated in synchronization with the scale frequency like CRF.

The time chart of the channel 1 will be described. The calculation timing corresponding to the channel 1 is determined by the channel code generated in the sequencer (802), and as shown in the figure, the calculation timing is generated every 22 μs.

... Signal CRF1 occurs in the middle of channel code 1. Waveform interpolation processing is not performed at the timing of occurrence.

... signal CRF1 simultaneously signal OTC1 to occur has occurred, the charge of the capacitor C ₁ in the analog cross Hua memory (812) is supplied to the integrator (813). The pulse width of the signal OTC is 2 μs
It is a degree.

When the channel code becomes 1 again, the process of reading the waveform sample data, the process of waveform interpolation, and the process of updating the frequency data are performed.

... When the calculation process of the channel 1 is finished, the signal DAC1 is generated, electric charge stored in the capacitor C ₁ via the DAC (811).

... When the arithmetic processing of the channel 1 is completed, the signal CRF1 is reset to cancel the calculation request.

.. Similarly to the above, at the timing when the signal CRF1 is generated again, the charge accumulated in the capacitor C ₁ at the above timing is supplied to the integrator (813).

Thereafter, similar to the above, each time the signal CRF is generated, the virtual waveform sample value calculation processing is performed once, and the waveform calculation result is synchronized with the generation timing of the signal CRF, that is, the scale synchronization, and the waveform calculation result is integrator (813). Is supplied to.

The relationship between the calculation cycle and the scale cycle is such that the calculation timing of the same channel is twice within the minimum scale cycle and the calculation result can be stored in the capacitor in the analog buffer memory unit (812). That is, within the minimum scale period, 10
It suffices to provide a calculation timing corresponding to the channel.

Description of Method of Generating Scale Period FIG. 13 shows a transition of frequency data supplied from the FDP (806) to the comparison register unit (805). Timer (804) is constituted by a binary counter 10 bits and represents the output state in hexadecimal notation, (000) performs a sequential count up-from ₁₆ to (3FF) _16, again from (3FF) ₁₆ ( 000) ₁₆ and (000) ₁₆
To (3FF) ₁₆ are repeated based on the signal MCK supplied from the main oscillator (801). That is, the repeating cycle T _R of the timer (804) is given by the following equation.

The output data transition state of the timer (804) is described as timer output data in FIG.

The method of generating the scale cycle is to compare the output signal of the timer (804) with the frequency data supplied from the FDP (806), and if a match is detected, compare the match pulse with the register pulse.
Send from (805). The generation cycle of the coincidence pulse becomes the scale cycle of the scale to be generated.

As shown in FIG. 13, a note clock signal can be generated by updating the frequency data. That is, the FDP (806) performs the arithmetic processing shown in the following equation.

NFD = MOD (OFD + PD, TD _max ) ... (4) NFD is new frequency data.

OFD is frequency data before updating.

PD is scale data that is determined by the generated scale.

TD _max is the number of output states of the timer (804). If TD _max of this example is 2 ¹⁰ i.e. 1024.

Table 8 shows scale data PD corresponding to 12 scales.

FIG. 14 is a block diagram of a specific example of the FDP (806). In FIG. 14, reference numeral (1401) denotes a cent scale data generation unit (hereinafter abbreviated as CPD generation unit) that generates scale data (CPD) represented by a cent scale, and is composed of a ROM that stores the cent scale data. The note clock specified data (N
D), the waveform sample number designation data (SD), and the CPD based on the organ type / piano type designation signal (OPS) are selectively generated. (1402) is a beat data gate that selects beat data, (1403) is a vibrato signal generator that generates a vibrato signal, (1404) is a glide signal generator that generates a glide signal, and (1405) is a cent scale. An exponential converter that converts the frequency value obtained into frequency data that is directly proportional to the frequency, (1406) is a computing unit, (1407) is a latch (AL), (1408) is a latch (BL), (1409) Is an adder (denoted as FA), (1410) is a buffer, and (1411) is a gate. (1412) (1413) (1414) are bus lines, (1412) is FA bus, (1413) is FB bus, and (1414) is FC bus.

The beat data CBD, the vibrato data CVD, and the glide data CGD are also shown on the cent scale.

Structure of various data St. Pitch data (CPD) 11-bit structure. Upper 4 bits represent 12-note equal temperament, and lower 7 bits represent each chromatic scale into 128 equal parts.

Beat data (CBD), vibrato data (CVD), glide data (CGD) Each bit structure is 8 bits and uses a two's complement representation and has a resolution of 128 equal chromatic scales. Then, positive and negative beat components, vibrato components, and glide components are represented.

Description of Vibrato Signal Generating Unit (1403) FIG. 22 is a block diagram showing a specific example of the vibrato signal generating unit (1403). In the figure, (2201) is a vibrato ROM for storing the vibrato data CVD, (2202) is a vibrato ROM (2201)
Vibrato address register for storing address data for reading the vibrato data stored from
(2203) is a shifter used for the day vibrato effect,
(2204) is a gate that supplies the output signal (vibrato data CVD) of the shifter (2203) to the FB bus by the signal RDCVD, and (220
5) is the signal KD supplied from the input register unit (803),
A condition setting unit that sets the operating conditions of the vibrato signal generation unit (1403) based on the signal VIB, the signal DVIB, and the signal CHC supplied from the sequencer (802), (2206) is a gate, (2207)
Is a gate, and (2208) is an AND gate.

The address data stored in the register (2202) has a 14-bit configuration, and the lower 11 bits are vibrato ROM (2201).
Address data, and the upper 3 bits are shift data for the shifter (2203). The shifter (2203) controls the amplitude of the vibrato data CVD supplied from the vibrato ROM (2201) based on the shift data. The relationship between the shift data VSFD and the output data OSFD of the shifter (2203) is as follows.

VSFD = (000) ₂ ... OSFD = (00) ₁₆ , VSFD = (001) ₂ ... OSFD = (C
VD / 64), VSFD ＝ (010) ₂ … OSFD ＝ (CVD / 32) ， ……, VSFD ＝
(110) ₂ ... OSFD = (CVD / 2), VSFD = (111) ₂ ... OSFD = (CVD) The condition setting section (2205) sets the following operating conditions.

Vibrato off Vibrato on / off signal VIB is “0”,
The output of the gate (2206) is forced to always (00) ₁₆ . Then, the shift data of the shifter (2203) is always (000) ₂ . As a result, the output data of the shifter (2203) becomes (00) ₁₆ . That is, the vibrato data CVD is always (00) ₁₆ .

Vibrato on When the vibrato on / off signal VIB is "1" and the signal DVIB is "0", the vibrato is on. Register (2
The address data stored in 202 is supplied to the gate (2207) and the shifter (2203) via the gate (2206). Note that the upper 3 bits of the address data, that is, the shift data is forcibly set to (111) ₂ . Then, the output of the vibrato ROM (2201) is input to the input of the gate (2204) (vibrato data C
VD) will be supplied as is.

Daylight vibrato When the vibrato on / off signal VIB and the daylight vibrato on / off signal DVIB are “1”, the daylight vibrato state is set. When any one of the key on / off signals KD of the eight channels is turned off from the off state, the gate (2206) is controlled so that the address data is set to (000) ₁₆ . Then, in the shifter (2203), the amplitude control of the vibrato data CVD (0, CVD / 64, CVD / 32, CVD
/ 16, CVD / 8, CVD / 4, CVD / 2, CVD). Then, when the shift data becomes (111) ₂ , the shift data is forcibly set to (111) ₂ as in the vibrato on state. The address data stored in the register (2202) is the sequencer
The gate (220) is supplied by the signal RDVAD supplied from (802).
It is supplied to the FB bus via 7).

The address data added by the arithmetic unit (1406) is a signal
It is stored in the register (2202) from the FC bus at the rising edge of the signal φ2 by WRVAD. Further, the signal RDCVD supplies the vibrato data CVD stored in the vibrato ROM (2201) to the FB bus via the shifter (2203) and the gate (2204).

Description of glide signal generator (1404) The glide signal generator (1404) also includes the vibrato signal generator (1404).
Glide RO that stores glide data in the same way as (403)
M, a glide address register for reading out predetermined glide data from the glide ROM, and a controller for controlling generation.

There are two operation modes: glide off and glide on.
There are types.

Glide-off signal When the signal GL is "0", the glide-off state is set. The glide data CGD is always (00) ₁₆ .

Glide-on signal When the signal GL is “1”, the glide-on state is set. It is similar to the commonly known glide effect. That is, the glide data CGD is read from the glide ROM when the key-on / off signal KD of 8 channels is turned off and the key-on / off signal KD of any one channel is turned on. Then, when the predetermined time has elapsed, the glide data CGD becomes (00) ₁₆ again.

Description of exponential converter (1405) The exponential converter (1405) has a built-in conversion ROM that stores conversion data for converting cent scale data into frequency data ED that is directly proportional to frequency.

In this embodiment, the upper 4 bits (bit positions 7 to 10) of the frequency data CFD on the cent scale are used as the address data.
An EXP ROM and a ΔEXP ROM that uses 11 bits from bit positions 0 to 10 as address data are available.

Then, the register that stores the frequency data CFD on the cent scale that has been subjected to the addition processing in the arithmetic unit (1406) by the signal WREXP, and the above-mentioned EXP ROM that uses the data stored in the register as the address data, ΔEXP・ ROM and signal RDEX
P, RD ΔEXP is used to configure the gates that supply the data stored in EXP ROM and ΔEXP ROM to the FA bus and FB bus, respectively.

EXP / ROM stores 16 words of frequency data at 100 cent intervals. ΔEXP / ROM divides 100 cents by 2 ⁷ or 128 to obtain 0.78 cent intervals of 15 × 128 = 1920 points of difference frequency data. I remember.

FIG. 15 is a processing flow chart showing the data processing procedure of the EDP (806). By performing the arithmetic processing shown below, the old frequency data OF
The new frequency data NFD is calculated from D and the comparison register (80
Supply to 5).

, CPD = CPD + CVD, CPD = CPD + CGD, CPD = CPD + CBD, PD = EXP (CPD) + ΔEXP (CPD), NED = OFD + PD Next, the operation of FIG. 14 will be described. The FDP (806) performs arithmetic processing according to the processing command signal sent from the sequencer (802).

Table 9 shows the flow of the arithmetic processing sequence. By sequentially executing the instruction steps shown in Table 9, the processing described in FIG. 15 is realized and the new frequency data NFD is calculated.

The symbols used in Table 9 are explained below.

AL latches the data supplied to the FA bus at the falling edge of signal φ2.

BL latches the data supplied to the FB bus at the falling edge of signal φ2.

CRAL is an instruction to clear latch AL with signal φ2 "1".

ADD1 is an instruction to add "1" to the carrier input of FA (1409).

TCA is an instruction to supply the result of arithmetic processing in FA (1409) to FA bus.

RDCPD is an instruction for supplying the cent data CPD generated by the CPD generator (1401) to the FA bus.

RDCBD opens the beat data gate (1402) gate to F
Command to supply beat data CBD to B bus.

RDCVD is an instruction to supply the vibrato data CVD generated by the vibrato signal generator (1403) to the FB bus.

RDCGD is an instruction to supply the glide data CGD generated by the glide signal generation unit (1404) to the FB bus.

RDEXP is the FA that converts EXP (CPD) converted in the exponential converter (1405).
Instructions to supply to the bus.

RDΔEXP is ΔEXP (CPD) converted in the exponential converter (1405)
To supply to the FB bus.

RDFD is an instruction to read the old frequency data OFD from the comparison register unit (805) and supply it to the FB bus.

RDVAD is an instruction to supply the contents of the vibrato counter in the vibrato signal generator (1403) to the FB bus.

RDGAD is an instruction to supply the contents of the glide counter in the glide signal generator (1404) to the FA bus.

WRVAD is an instruction to write the result calculated by FA (1409) to the vibrato counter in the vibrato signal generator (1403) at the rising edge of signal φ2.

WRGAD is an instruction to write the result calculated by FA (1409) to the glide counter in the glide signal generator (1404) at the rising edge of signal φ2.

WREXP is the exponent converter (1405) that calculates the result of FA (1409).
Command to write to the rising edge of signal φ2.

WRFD is the comparison register (80
Command to write to 5) at the rising edge of signal φ2.

The 11 states generated in the 11-ary counter (902) in the sequencer (802) shown in FIG. 9 correspond to the instruction steps 1 to 11 shown in Table 9.

Description of operation contents by signal GAM (generator assigner operation mode signal) When signal GAM = "0", 1 key 1 channel operation is performed.
In this case, the beat data CBD is in the compulsory (00) ₁₆ state. That is, no beat effect is added.

When the signal GAM = "1", 1-key 2-channel assign operation is performed. In this case, 1 channel and 5 channels, 2 channels and 6 channels, 3 channels and 7 channels, 4 channels and 8 channels are the same tone data. Then, the beat data CBD used for 1 to 4 channels is forcibly set to (00) ₁₆ and the beat data CBD used for 5 channels to 8 channel is set by using the beat data supplied from the CPU (603). The beat effect can be generated.

As described above, since a plurality of comparators are used and the comparison data is calculated and obtained, a plurality of high-speed frequency dividers (for the number of channels) are arranged in parallel. The circuit scale can be reduced because there is no need to provide it.

Further, using the signal GAM, the channels 1 to 4 are set to beat data CBD = (00) ₁₆ and the beat data CBD of the channels 5 to 8 are set.
Using the beat data supplied from the CPU (603), channels 1 and 5; channels 2 and 6; channels 3 and 7; channels 4 and 8 are the same tone generation data The beat effect can be easily realized without adding.

Furthermore, a channel-independent glide effect can be added simply by preparing the glide address counters in the glide signal generator (1404) for the channels.

FIG. 16 is a block diagram showing a specific example of the comparison register section (805). In the figure, (1601) (1602) (1603) are frequency data registers FDR1 to FDR8, which are prepared for eight channels. (1604)
(1605) and (1606) are the gates GT1 to GT8, with 8 channels available. Reference numerals (1607), (1608) and (1609) are comparators, (1610) and (1611) are decoders, and (1612) is an AND gate.

The output signals TM0 to TM9 of the timer (804) are compared to the comparators (1607) to (16
It is commonly supplied to 09). Then, the new frequency data NED calculated by the FDP (806) is supplied to the inputs of the registers FDR1 to FDR8 from the FC bus respectively, and the signal WRFD and the signal CLRF are supplied.
When both (calculation request flag signals) are "1", the new frequency data NFD is written in the predetermined register FDR. That is, the data is written only when the calculation request is generated.

Also, when the old frequency data OFD is required in FDP (806),
The signal FDFD is supplied to the decoder (1610), which opens the predetermined gates of GT1 to GT8 and supplies the old frequency data OFD to the FB bus.

When the new frequency data NFD in the data processing means described in FIG. 15 is written to any of the registers FDR1 to FDR8 according to WR1 to WR8, and then read through the gates GT1 to GT8 according to RD1 to RD8. Is the new frequency data
The NFD will be supplied to the FB bus as the old frequency data OFD.

On the other hand, the comparators (1607) to (1609) compare the signals TM0 to TM9 from the timer (804) with the frequency data FD stored in the registers FDR1 to FDR8, and if a match is detected, a match signal is detected. Output as NC1 to NC8.

FIG. 17 is a block diagram showing a specific example of the calculation request flag generating section (810). In the figure, (1701) to (1710) are NAND gates, and (1
711) is the decoder, (1712) to (1719) is the RS flip-flop.
(RSFF) and (1720) are selectors, and (1721) is a D-type flip-flop (DFF).

Match signals NC1 to NC8 supplied from the comparison register block (805)
The main oscillator (801) with NAND gates (1701) to (1708)
The logical operation is performed with the signal MCK supplied from, and the result is supplied to each input of RSFF (1712) to (1719). When the match signal becomes “1” (match is detected by the comparator), RSFF
"0" is supplied to the input of and the output Q becomes "1",
The calculation request signal CRF described in FIG. 12 becomes “1”.

The selector (1720) selects the signal CRF corresponding to the operation timing and supplies it to the input D of the DFF (1721). Then, the signal W in the control data supplied from the sequencer (802)
When RCLF becomes "1", DFF is generated at the falling edge of signal φ2.
The calculation request signal CRF selected by the selector (1720) is latched in (1721) and output as the calculation request flag signal CLRF. If the calculation request is generated, the flag signal CLRF becomes "1", and if not, the flag signal CLRF becomes "0".

The timing at which the signal WRCLF is generated is generated at the instruction step 1. That is, the presence or absence of the calculation request is determined at the beginning of the arithmetic processing.

After that, at the timing of the instruction step 11, the reset (clear) signal CRCLF which is one of the control data supplied from the sequencer (802) is supplied. Then, if the flag signal CLRF is “1”, the NAND gate (1709)
Output signal becomes "0", "0" is supplied to the predetermined input of RSFF (1712) to (1713) selected by the decoder (1711) by the channel code CHC, and RSFF is reset (output Q
= “0”). This operation corresponds to the timing of resetting the calculation request signal CRF described in FIG.

Detailed description of the data read processor DRP (808) First, the tone synthesis data ROM (606) (hereinafter referred to as the data bank (D
BK)) will be described.

FIG. 18 is a data configuration diagram of DBK (606). Address (000
0) In the area of ₁₆ to 128 words, the start address indicating the start position of the subsequent composite data is stored. The synthetic data is composed of control data and waveform data. The control data is composed of repeat number designation data between waveforms and final waveform flag data.

The number-of-times designation data will be described. In this embodiment, the interpolation coefficient shown in equation (2) The following is a method of simplifying the calculation of

In equations (1) and (2), the increment value of the N · m + n term was 1, but the numerator increment value of the interpolation coefficient is α.

(2) Interpolation coefficient Replace with.

(3) Fix the M, N, and α terms as 2 ¹⁶ .

As a result, the interpolation coefficient becomes (M · N + n) α / 2 ¹⁶ ,
For the 1/2 ^16th term, it suffices to perform a right shift operation.
It is not necessary to calculate the term, and the interpolation coefficient can be calculated easily. Table 10 shows the relationship between the repeat designation data, the increment α, the number of samples in one cycle of the waveform, and the number of repeats.

If the repeat number designation data is (F) ₁₆ , it is used as a final waveform flag (signal WEF) indicating the final waveform.

The control data area of DBK (606) is fixed as 128 words regardless of the number of corrugated boards. Further, one word of control data has a structure of 16 bits, and the repeat designation data is divided into 4 groups of 4 bits as follows.

Bit positions 0 to 3 ... C, C ^# , D sound Bit positions 4 to 7 ... D ^# , E, F sound Bit positions 8 to 11 ... F ^# , G, G ^# sound bit positions 12 to 15 ... A, A ^# , B tone In this way, the control data can be set differently depending on the scale, and even if the same waveform data in one octave is used, the rise time of the musical tone and the change time of the waveform shape are made constant. It becomes possible. Waveform data is 1 word 16
Bit-structured PCM data.

FIG. 19 is a block diagram showing a specific example of the DRP (808). In the figure, (1901) is a DBK address register for storing address data for reading out predetermined synthesis data from the tone synthesis data ROM (DBK) (606), and (1902) is a tone synthesis data ROM (DBK) (60
DBK input buffer fetched from 6) into the synthesized data DRP (808), (1903) is a reference start address gate that outputs address data for reading the start address stored in DBK (606), (1904) is Waveform data memory I, which stores a value in the waveform sample corresponding to f (X _{i, n} ), is stored in f (X
_The waveform data memory II, (1906), which stores values in the waveform sample corresponding to _{(i + 1, n} ), corresponds to the numerator of the interpolation coefficient (N ·
m + n) coefficient data memory that stores α, (1907) is the start address register , (1908) is the increment value α of the (Nm + n) α term of the interpolation coefficient
(1909) is a waveform sample number memory that stores the sample number n within one cycle of the waveform,
(0) is the waveform number memory that stores the waveform number i, (1911)
Is the offset data gate, (1912) is the accumulation register (AC
(C) and (1913) are arithmetic units composed of full adders, latches, carry flag registers, etc., (1914) are arithmetic units (1913)
DA bus for supplying data to latch AL in (1915) is DB bus for supplying data to latch BL in operation unit (1913), (191
6) is a DC bus for supplying the results of the operation performed by the operation unit (1913) to each register, and (1917) is a DBK bus for supplying the output of the DBK input buffer (1902) to the waveform data memory I (1904).

Next, the configuration of each part will be described. Waveform data memory I
(1904), waveform data memory II (1905), DBK (60
6) Registers R (WDI) and R (WDII) for temporarily storing the waveform data read from the sequencer (802) by the signals WRWDI and WRWDII in the control data supplied from the sequencer (802),
It is composed of 16 bits × 8 words of memories M (WDI) and M (WDII) for storing waveform data of 8 channels. Normally, the memory is in a read state, and the channel waveform data ▲ ▼ and ▲ ▼ based on the channel code CHC supplied from the sequencer (802) is supplied to the WDP (807).

Then, the signal W in the control data from the sequence (802)
The RRAM causes the memory to be in a write state, and the waveform data stored in the registers R (WDI) and R (WDII) is written to a predetermined address of the memory based on the channel code CHC.

The coefficient data memory (1906) is a register R (MD) for temporarily storing the calculation result of the calculation unit (1913) by the signal WRMD in the control data supplied from the sequencer (802),
A 16-bit x 8-word memory M (MD) for storing coefficient data for 8 channels, and a signal RDMD for output data from the memory M (MD).
It consists of a gate that supplies to the DB bus. Normally, the memory is in the read state, and the sequencer (8
02) The address coefficient data (M (MD)) based on the channel code CHC composed of
(807).

Then, in response to the signal WRRAM, the memory enters the write state, and the new coefficient data stored in the register R (MD) is written to the predetermined address of the memory based on the channel code CHC.

The start address register (1907) supplies the start address read from the DBK (606) to the gate 1 that supplies the start address to the DA bus by the signal TDA in the control data (same below) from the sequencer (802) and the signal WRTAD. The register R (TAD) for temporarily storing the read start address and the gate 2 for supplying the start address stored in the register R (TAD) to the DB bus by the signal RDTAD.

The increment generation section (1908) temporarily stores the control data read from the DBK (606) by a signal WRREP.
And a selector for selecting predetermined repeat designation data from the control data stored in the register R (REP) based on the note clock designation data ND supplied from the input register unit (803), and the selector. A converter that converts the repeat number designation data into the increment value α shown in Table 10, a detector that detects the final waveform flag and outputs the final waveform flag WEF [“1”], and a signal RDREP. It is composed of a gate that supplies the output data (increment value α) of the device to the DA bus.

The waveform sample number memory (1909) has a register R (WSN) for temporarily storing the calculation result (new waveform sample number n) of the calculation unit (1913) by the signal WRWSN and a waveform sample number n for 8 channels. 16 bits x 8 words of memory M (WSN) for storing the data and the output data of the memory M (WSN) as the signal RDWS.
It consists of a gate supplied to the DB bus by N.
Normally, the memory M (WSN) is in a read state, and the channel waveform sample number n based on the channel code CHC supplied from the sequencer (802) is supplied to the above gate.

Then, the signal WRRAM causes the memory M (WSN) to be in a write state, and the new waveform sample number n stored in the register R (WSN) is written to a predetermined address of the memory based on the channel code.

The waveform number memory (1910) stores a calculation result (new waveform number i) of the calculation unit (1913) temporarily by a signal WRWND, and a waveform number i for 8 channels.
16-bit x 8-word memory M (WND) for storing the data and the output data (waveform number) of the memory M (WND) are input to the register section.
Waveform sample number specification data SD supplied from (803)
Shifter (i × number of samples) based on the above, and the shifter unit that outputs the waveform number address WNA and the signal RDWND
The gate 1 that supplies the output data of the memory to the DB bus by the, the gate 2 that supplies the output data of the shifter section to the DB bus by the signal RDWNA, and the waveform sample number designation data SD
, And a gate 3 which supplies the output data of the sample number generator to the DB bus by the signal RDNWS.

The normal memory M (WND) is in a read state, and supplies the waveform number i of the channel based on the channel code CHC supplied from the sequencer (802) to the gate 1 and the shifter section.

Then, the signal WRRAM causes the memory M (WND) to be in a writing state, and the new waveform number i stored in the register R (WND) is written to a predetermined address of the memory based on the channel code.

The accumulation register (ACC) (1912) is a register R (ACC) for temporarily storing the calculation result of the calculation unit (1913) by the signal WRACC.
And a gate for supplying the data stored in the register R (ACC) to the DA bus by the signal RDACC.

FIG. 23 is a block diagram showing a specific example of the calculation unit (1913).
(2301) is a latch AL that stores the contents of the DA bus at the falling edge of the signal φ2, and is cleared by the signal DCRAL. (230
2) is a latch BL that stores the contents of the DB bus at the falling edge of the signal φ2, (2303) is a 16-bit adder (FA) having a carry input (CI) and a carry output (CO), and (3204) is A carry flag register that stores the carrier output signal of FA (2303) by signal WRMD, (2305) is a gate that supplies the output data of FA (2303) to the DA bus by signal TCA, and (2306) is FA ( 2303) is a gate for supplying the output data to the DC bus, (2307) is a gate for supplying the data (0000) ₁₆ to the DC bus, and (2308) is a key on / off signal KD supplied from the input register section (803). And a signal RDFLG and a channel code CHC are input, and an on / off detection unit that outputs a detection signal by detecting the timing when the key signal changes from the off state to the on state independently for each channel, (2309) to (2313) ) Is an AND gate, (2314) (2315) (231
6) is an OR gate.

If both the final waveform flag signal WEF and the signal RDNWS supplied from the increment generator (1908) are "1", the AND gate
The output signal of (2309) becomes "1" and the latch BL (2302) is reset. When both the signal WEF and the signal WRMD are "1", the output signal of the AND gate (2312) becomes "1" and the data (0000) ₁₆ from the gate (2307) is supplied to the DC bus.

The offset data generated in the offset data gate (1911) is 256 in decimal number, which corresponds to the control data storage area.

Like the FDP (806), the DRP (808) also performs the arithmetic processing described below based on the control signal supplied from the sequencer (802).

Read the start address TAD stored in DBK.

The tone generation data (ND, SD) supplied from the input register section (803) is transferred to the signal RD supplied from the sequencer (802).
Supply to DC bus by RTA. Then, the signals ND and SD on the DC bus are sent to the DBK address register (190
Stored in 1) and supplied to DBK (606). The head address data TAD read from the DBK (606) is stored in the register R (TAD) of the head address register (1907) by the signal WRTAD.

Reading process of the specified number of repeats

Read start address data TAD and waveform number memory
Addition processing with the waveform number i stored in (1910) (TAD
+ I) is performed by the operation unit (1913), the addition result is stored in the DBK address register (1901), the repeat number designation data is read from DBK (606), and the register R (R) of the increment generation unit (1908) is read.
EP).

Reading process of waveform sample f (X _{i, n} ).

Addition processing of the start address data TAD stored in the start address register (1907) and the offset data (256) ₁₀ (WAD1
= TAD + 256) in the calculation unit (1913) and the addition result is ACC
Store in R (ACC) of (1912). Addition processing of the address data WAD1 stored in the ACC (1912) and the waveform sample number n stored in the waveform sample number memory (1910) (WAD1 =
WAD1 + n) is calculated by the operation unit (1913) and the addition result is calculated by ACC (191
Store in 2). Then, the address data WAD1 ′ and the waveform number i stored in the ACC (1912) are shifted based on the waveform sample number designation data SD (i × sample number; i = 0, 1, 2, ..., I -1) and addition process (WA
D1 ″ = WAD1 ′ + i × number of samples) is calculated by the operation unit (1913) and the addition result is ACC (1912) and DBK address register (1901)
The waveform sample data corresponding to f (X _{i, n} ) is stored in the DBK (606) and is read from the register R in the waveform memory I (1904).
Store in (WDI).

Reading process of waveform sample f (X _{i + 1, n} ).

Address data WAD1 ″ stored in ACC (1912) and the number of waveform samples NWS specified in the waveform sample number specification data SD
Addition process (generated in the waveform number memory (1910)) (WA
D2 = WAD1 '+ NWS) is performed by the operation unit (1913) and the addition result is D
It is stored in the BK address register (1901), and f (X
_The waveform sample data corresponding to ( _{i + 1, n} ) is read and stored in the register R (WDII) in the waveform memory II (1905).

Update processing of waveform sample number n.

A calculation unit (191) performs addition processing (n = n + 1) of the waveform sample number n and the signal DADD1 supplied from the sequencer (802).
3) and store it in the waveform number register R (WSN) in the waveform sample number memory (1909).

Update process of the interpolation coefficient (N · m + n) α.

Interpolation coefficient stored in coefficient data memory (1906) [(N
[M + n) α] and the increment value α generated in the increment generation unit (1908) are added by the calculation unit (1913), and the addition result is added to the coefficient data register R in the coefficient data memory (1906).
In addition to storing it in (MD), when the addition result is over-followed, the carry flag register CF in the arithmetic unit (1913) is set to "1".

Waveform number i update processing.

The calculation unit (1913) performs addition processing (i = i + CF) between the waveform number i stored in the waveform number memory (1910) and the contents of the carry flag register CF described above, and the waveform number memory (1910) Waveform number register R (WND) in
To store.

Register R (WND), R (WSD), R (MD), R (WDI), R (WD
Data transfer processing of various data stored in II) to each memory area specified by the channel code CHC. At the timing of the instruction step 11, data transfer processing is performed based on the signal WRRAM supplied from the sequencer (802). When the calculation request flag signal CLRF is "0", the transfer process is not performed. This is because no new waveform sample is calculated.

Table 11 shows the DRP (808) operation sequencer.

By sequentially executing the instruction steps shown in Table 11,
The processes described in the above are realized.

The key on / off signal KD described in Table 4 is "0".
The first process that changes from "1" to "1" is an initial process, and the following condition setting is performed.

The signal [“1”] instructing the initial processing is generated by the on / off detecting unit (2308) in the arithmetic unit (1913) shown in FIG.

Waveform sample number n = (0) ₁₀ setting.

Signal WRWS at the timing of instruction step 7 shown in Table 11
N is supplied to the calculation unit (1913). Then, AND gate
The output signal of (2310) becomes "1", and the gates (2306) (2307)
"1" is supplied to the control input of. As a result, (0000) ₁₆ is supplied to the DC bus and the waveform sample number memory (190
Store (0000) ₁₆ in the register R (WSN) in 9).

Waveform number i = (0) ₁₀ setting.

At the timing of instruction step 10 shown in Table 11, signal WR
WND is supplied to the calculation unit (1913). Then, the output signal of the AND gate (2311) becomes “1”, and the gate (2306) (230
"1" is supplied to the control input of 7). As a result, (0000) ₁₆ is supplied to the DC bus, and (0000) ₁₆ is stored in the register R (WND) in the waveform number memory (1910).

Through the above process, the waveform number i and the waveform sample number n are initialized each time the key-on / off signal KD changes from off to on.

In addition, the repeat specified data read from DBK (606)
(F) ₁₆ That is, if the final waveform flag is WEF, the condition setting as described below is performed.

Numerator term of interpolation coefficient (Nm + n) α = (0) ₁₀ setting.

Signal WRMD at the timing of instruction step 9 shown in Table 11
Is supplied to the AND gate (2312) in the arithmetic unit (1913). Then, the output signal of the AND gate (2312) becomes "1", and "1" is supplied to the control inputs of the gates (2306) and (2307). As a result, (0000) ₁₆ is supplied to the DC bus, and (0000) ₁₆ is stored in the register R (MD) in the coefficient register memory (1906).

Waveform sample number NWS = (0) ₁₀ setting.

Signal RDNW at the timing of instruction step 7 shown in Table 11
S is supplied to the AND gate (2309) in the arithmetic unit (1913). Then, the output signal of the AND gate (2309) becomes "1", and the storage state of the latch BL (2302) is cleared (0000) ₁₆ .
As a result, a DB for reading the waveform sample f (X _{i + 1, n} )
The address data of K (606) is the waveform sample f (X _{i, n} )
Becomes equal to the read address data.

With the above settings, when the final waveform data is reached,
The waveform interpolation processing is not substantially performed, and the final waveform data is repeatedly used.

Description of signals shown in Table 11 The signals described below are supplied from the sequencer (802).

RDOSD supplies the offset data (256) to the DA bus.

RDACC is an instruction to supply the data stored in the register R (ACC) in the ACC (1912) to the DA bus.

RDREP sets the increment value α generated in the increment generator (1908) to D
Instruction to supply to the A bus.

RDWSN is the waveform sample number n read from the memory M (WSN) in the waveform sample number memory (1909).
Instruction to supply to the B bus.

RDWND is an instruction to supply the waveform sample number i read from the memory M (WND) in the waveform number memory (1910) to the DB bus.

RDWNA is an instruction to supply the waveform number address (WNA) generated in the shifter section in the waveform number memory (1910) to the DB bus.

RDTAD is the register R in the start address register (1907)
An instruction to supply the start address stored in (TAD) to the DB bus.

RDNWS is an instruction to supply the number of samples generated by the sample number generator in the waveform number memory (1910) to the DB bus.

RDMD is an instruction to supply the coefficient data read from the memory M (MD) in the coefficient data memory (1906) to the DB bus.

RDRTA is an instruction to supply the tone generation data (ND, SD) supplied from the input register unit (803) to the DC bus.

WRDBK transfers data on the DC bus to the DBK address register (190
Instruction to store in register R (DBK) in 1).

WRACC transfers the data on the DC bus to the register R in ACC (1912).
Instruction to store in (ACC).

WRWSN is an instruction to store the data on the DC bus in the register R (WSN) in the waveform sample number memory (1909).

WRMD is an instruction to store the data on the DC bus in the register R (MD) in the coefficient data memory (1906).

WRWND is a waveform number memory (1910) for data on the DC bus.
Instruction to be stored in the internal register R (WND).

TDA is an instruction to supply the start address read from DBK to the start address register (1907) to the DA bus.

TCA is an instruction to supply the data on the DC bus to the DA bus.

DCRAL is an instruction to clear the latch AL (2301) in the operation unit (1913).

DADD1 is an instruction to supply the carrier input signal (+1) to the FA (2303) in the arithmetic unit (1913).

RDFLG is an instruction to take in the new key on / off signal KD to the on / off detection part (2308) in the operation part (1913).

WRRAM is the register R (WD
I), the register R (WDII) in the waveform data memory II (1905),
The data stored in the register R (MD) in the coefficient data memory (1906), the register R (WSN) in the waveform sample number memory (1909), and the register R (WND) in the waveform number memory (1910), Memory M (WDI), M (WDII), M (M
D), M (WSN), M (WND) write command.

As described above, by storing the start address of the composite data (waveform data, control data) in the data memory (DBK), the waveform data that differs only by the data content operation in the data memory can be performed without complicating the circuit configuration. Can be selected,
Different musical tones can be easily generated.

In addition, multiple sets of control data (data for specifying the number of repetitions)
When preparing and synthesizing, the predetermined control data is selected and used, so the control data can be set differently depending on the scale, and the same waveform data within one octave is used. Even if the rise time of the musical sound,
The change time of the waveform shape can be made constant.

Furthermore, since the waveform data, control data, and start address are stored in the same database and various data are read in a time-division manner, the circuit configuration of the data memory (DBK) can be simplified and the data memory and Interface processing with DRP (808) can be simplified.

Detailed Description of Waveform Data Processor WDP (807) FIG. 20 is a flowchart of the arithmetic processing of WDP (807). WDP (807)
There are four types of calculation processing.

Virtual waveform sample value by performing waveform interpolation operation Ask for.

Virtual waveform sample value And the envelope data ED are multiplied, and the envelope added waveform sample value Ask for.

Previously obtained envelope added waveform sample value Old And the envelope added waveform sample value obtained this time The difference waveform sample value Df (X
_{i, m, n, q, r} ) is calculated.

The envelope data ED is updated.

Next, the envelope data ED and the envelope addition method will be described.

The envelope data ED consists of 20 bits. The upper 4 bits are EDU (Q) and the lower 16 bits are EDL (R).

The method of updating the envelope data ED is: new ED = old ED + ΔED
The calculation processing is called. The incremental envelope data ΔED is the sustain data DSUS or damper data supplied from the CPU (603) to the input register section (803).
Use DDMP. The sustain data and the damper data are selected according to the organ type envelope, the piano type envelope, and the key on / off signal.

The equation below is used to calculate the envelope added waveform sample value.

q = 0,1,2, ..., Q-1 (Q = 2 ⁴ ) r = 0,1,2, ..., R-1 (R = 2 ¹⁶ ) Envelope data ED monotonically increases, that is, new ED = old ED
By setting + ΔED (constant) and executing the equation (5), the attenuation (falling) envelope of the exponential characteristic can be added. Also, by monotonically decreasing, that is, new ED = old ED−ΔED (constant), a rising envelope of the exponential characteristic can be added. By performing such processing, it is possible to obtain the envelope data ED with a simple configuration, which is obtained only by calculation without generating the envelope of the exponential characteristic.

FIG. 21 is a block diagram showing a specific example of WDP (807). In the figure
(2101) is a waveform data gate I, (2102) is a waveform data gate II, (2103) is an envelope increment generating section (ΔED generating section) that generates an increment value of the envelope data ED, and (2104) is an old waveform sample value. The old waveform data memory section storing (2105), the envelope data memory section (ED memory section) storing the envelope data ED (2106) is the multiplying section, and (2107) is the expression (5). A shifter section that performs 1/2 ^q or 1/2 ^{q + 1} operation, (2
108) is a full adder, an arithmetic unit composed of latch and carry flag registers, etc., (2109) is a differential waveform sample value To store the output buffer register (OBR), (211
0) controls the on / off of the analog switch (1103) - in analog cross Hua memory unit (812) (1107) (switch for storing a charge in the capacitor C ₁ -C ₈₎ (Figure 11) Writing The pulse generator (2111) is the latch in the calculator (2108).
WA bus that supplies data to AL, (2112) a WB bus that supplies data to latch BL in computing unit (2108), (2113) computing unit
Supply the calculation result of (2108) to each register.
It is a WC bus.

Next, the configuration contents of each unit will be described. ΔED generator (210
3) is a selector for selecting either sustain data DSUS or damper data DDMP as the increment data ΔED and a key on / off signal KD and an organ type / piano type designation signal OPS supplied from the input register section (803). A controller that generates a selection signal from the damper on / off signal DMP, and an increment generation unit (190) in the signal KD, the signal OPS, the signal DMP, and the DRP (803).
8) A virtual key signal generator that generates a virtual key on / off signal from the final waveform flag signal WEF supplied from 8) and outputs a virtual key signal EADG. Table 12 shows the selection contents of the increment data ΔED and the generation state of the virtual key signal EADG.

When the signal OPS shown in Table 7 is "0", that is, when the organ type is designated, the virtual key signal EADG is the key on / off signal.
It is equal to the on (“1”) and off (“0”) state of KD.

When the signal OPS is "1", that is, when the piano type is designated, the virtual key signal EADG is in the state described below.

When the signal WEF is "0" (a) When the signal DMP (damper on / off signal shown in Table 7) is "0", the virtual key signal EADG is in the "on" state.

(b) When the signal DMP is "1", the virtual key signal EADG becomes equal to the on / off state of the key on / off signal KD.

When the signal WEF is "1", the virtual key signal EADG is turned off regardless of the states of the signal DMP and the key on / off signal KD.

Explanation of the function of the virtual key signal EADG When the signal WEF becomes "1" and the final waveform data is repeatedly used to generate the musical tone of the connecting person, if the organ type is designated, it will be equal to the musical tone characteristic of the organ type and a problem will occur. do not do.

When the piano type is designated, it is necessary to set the tone characteristic to be the attenuation characteristic, and the signal WEF = "1". Even if a connection person is generated by repeatedly using the final waveform data, the virtual key signal EADG is turned off and the attenuation is performed. Envelope characteristics are added to force the musical sound characteristics to be attenuation characteristics.

The old waveform data memory unit (2104) has a register R (OWD) for temporarily storing the operation result of the operation unit (2108) by the signal WROWD supplied from the sequencer (802) and an envelope for eight channels. Additional waveform sample value Is composed of a 16-bit × 8-word memory M (OWD) for storing data and a gate for supplying the output data of the memory M (OWD) to the WB bus by a signal RDOWD. The normal memory M (OWD) is in a read state and supplies the envelope added waveform sample value of the address based on the channel code CHC supplied from the sequencer (802) to the above-mentioned gate. Then, the signal WRRAM causes the memory M (OWD) to be in a write state, and the data stored in the register R (OWD) is written to the memory M (OWD).

The ED memory unit (2104) outputs the calculation result of the calculation unit (2108) to the signal WR.
Register R (ED that temporarily stores each by EDL, WREDU
L), R (EDU), and envelope data ED for 8 channels
Memory M (EDL), M (EDU) and memory M (EDL)
Of the memory M (EDU) is supplied to the WB bus by a signal RDEDU and a gate U of the memory M (EDU) is supplied to the WB bus by a signal RDEDU. The memory M (EDL) has 16 bits × 8 words, and the memory M (EDU) has 4 bits × 8 words. Normal The memories M (EDL) and M (EDU) are in the read state, and the envelope data ED of the address based on the channel code CHC is read and supplied to the gate L and the gate U, respectively. The signal EDU is supplied to the multiplication unit (2106) and the signal EDL is supplied to the shifter unit (2107).

Then, the memories M (EDL) and M (EDU) are in a write state by the signal WRRAM, and the data stored in the registers R (EDL) and R (EDU) are stored in the memories M (EDL) and M (EDU). Written.

The multiplication unit (2106) is a register R (MLP1) for temporarily storing the waveform data by the signal WRMLP, and a signal D when the signal SELWE = "0".
A register R (MLP2) for temporarily storing the coefficient data MLP supplied from the RP (808) and temporarily storing the envelope data EDL supplied from the ED memory unit (2105) when the signal SELWE = "1", Multiply 16 bits x 16 bits = 32 bits by using the data stored in register R (MLP1) as the multiplicand (2's complement representation) and the data stored in register R (MLP2) as the multiplier (absolute value representation). And a gate for supplying the upper 16 bits of the multiplication result of the multiplier by the signal RDMLP to the WB bus.

The shifter unit (2107) outputs the calculation result of the calculation unit (2108) to the signal WRSF.
Register R (SFT) temporarily stored by T and register R
Shift operation of the data stored in (SFT) based on the envelope data EDU supplied from the ED memory unit (2105) Shifter, a register R (SFA) for temporarily storing the output data of the shifter by the signal WRSFA, a gate A for supplying the data stored in the register R (SFA) by the signal RDSFA to the WA bus, and a signal RDSFB. The shifter data directly to W
It is composed of a gate B that supplies the B bus.

FIG. 24 is a block diagram showing a specific example of the calculation unit (2108).
(2401) is an inversion gate that inverts the data on the WA bus by the signal INV, and (2402) is a latch AL that temporarily stores the output data of the inversion gate (2401) at the falling edge of the signal φ2. Therefore, the storage status becomes (0000) ₁₆ . That is, it is reset. (2403) is data φ2 on the WB bus
Latch BL temporarily stored at the falling edge of (2404) is a 16-bit adder (FA) with a carrier input and a carrier output, (240
5) is a carry flag register ECF that stores the carry output of FA (2404) by the signal WREDL and resets it by the signal RDEDL, (2406) is an AND gate, (2407) is an OR gate, and (240
8) is a gate A which supplies the output data of FA (2404) to the WA bus by the signal WTCA, (2409) is a gate B which supplies the data (FFFF) ₁₆ to the WC bus, and (2410) is a WB to the WC bus. Gate C, which supplies data on the bus, (2411) outputs the output data of FA (2404).
Gate (D) supplied to the WC bus (2412) is data (0000) ₁₆
Gate E supplied to the WC bus, (2413) is signal TBC, signal WRE
Gate B (2409) to gate E based on the output signals (bit position 4) of DU, signal WREDL, signal EADG and FA (2404)
A gate selector for selecting any one of (2412).

The gate selected by the gate selector (2413) will be described. The gate C (2410) is selected by the signal TBC supplied from the sequencer (802), and the data on the WB bus is supplied to the WC bus.

Virtual key signal EADG supplied from ΔED generator (2103)
Is ON, gate E (2412) is selected by signal WREDL or signal WREDU, and data (0
000) ₁₆ will be supplied. That is, the envelope data ED
Both U and EDL will be set to (0000) ₁₆ . As a result, the envelope added waveform sample value Becomes

When the output signal (bit position 4) of FA (2404) is "1" and the signal WREDU is supplied, the gate B (2409) is selected and the data (FFFF) ₁₆ is supplied on the WC bus. That is,
Envelope data EDU will always be set to (F) ₁₆ .

In states other than the above, gate D (2411) is selected and FA (2
The output data of (404) is supplied to the WC bus.

The old waveform data memory section (2105) and ED memory section (2106)
The signal WRRAN supplied to is the same as the signal WRRAM described in DRP (808). WDP (807) also DRP (808), EDP
Similar to (806), the following arithmetic processing is performed based on the control signal supplied from the sequencer (802), and
The processing contents of are realized.

A virtual waveform sample value f (X _{i, m, n} ) is obtained.

D by signals RDWDI and RDWDII (corresponding to instruction step 2)
The waveform sample values f (X _{i, n} ) and f (X _{i + 1, n} ) supplied from RP (808) are supplied to the WA bus and WB bus, and are input to the latches AL and BL of the calculation unit (2108). The waveform sample value is stored at the falling edge of the signal φ2. Signal INV applied to the calculation unit (2108) at this time
Therefore, the data stored in the latch AL is the inverted data, that is, Becomes

Then, addition processing is performed by the calculation unit (2108) using the data stored in the latch AL (2402) and the latch BL (2403). That is, [f (X _{i-1, n} ) −f (X _{i, n} )] is executed, the operation result is output to the WC bus, and the multiplication unit (210
6) is written in the multiplicand register R (MLP1) at the rising edge of the signal φ2, and the interpolation coefficient (N · m + n) α supplied from the DRP (808) is used in the multiplier register R (MLP).
It is stored in 2).

Then, multiplication of [f (Xi-1, n) −f (Xi, n)] × (N · m + n) α is executed in the multiplication unit (2106). It is assumed that the multiplication result has a correct value by the end of the instruction step 4. Next, the rectangular sample value f (X _{i, n} ) is supplied to the WA bus by the signal RDWDI and the multiplication result is supplied to the WB bus by the signal RDMLP, and the latch AL and BL are respectively supplied at the trailing edge of the signal φ2. Store data (corresponding to instruction step 5). The multiplication result is the higher order of the multiplier
Uses 16 bits. This is equivalent to 1/2 ¹⁶ processing.

The virtual waveform sample value f (X _{i, m, n} ) represented by the equation (2) is obtained by executing the addition process in the calculation unit (2108).

Envelope added waveform sample value Ask for.

Virtual waveform sample value By the signal WRMLP and the signal WRSFT (corresponding to the instruction step 6), the multiplicand register R (MLP in the multiplication unit (2106)
1) and the register R (SFT) in the shifter unit (2107) are stored at the rising edge of the signal φ2. Further, the envelope data EDL supplied from the ED memory unit (2105) to the multiplication unit (2106) is supplied to the multiplication unit (21) by the signal SELWE (corresponding to the instruction step 6).
Stored in multiplier register R (MLP2) in 06), and multiply To execute.

On the other hand, the virtual waveform sample value stored in the register R (SFT) in the shifter unit (2107) Shift operation based on the envelope data EDU (Q) supplied from the ED memory unit (2105) to the shifter unit (2107). Then, it is stored in the output register R (SFB) in the shifter unit (2107) by the signal WRSFB (corresponding to the instruction step 7).

Then, the multiplication result obtained by the multiplication unit (2106) is converted into the signal TB.
C, the signal WRSFT (corresponding to the instruction step 8) is stored in the register R (SFT) in the shifter unit (2107), and the shift operation is performed based on the envelope data EDU (Q).

Signals RDSFA and RDSFB (corresponding to instruction step 9)
The data [f (X _{i, m, n} ) / 2 ^q ] stored in the output register R (SFB) in the shifter unit (2107) is used as the latch B in the arithmetic unit (2108).
Shift result data of shifter part (2107) to L Is logically inverted by the signal INV and stored in the latch AL in the arithmetic unit (2108).

Then, the addition unit is executed in the calculation unit (2108) to obtain the envelope added waveform sample value. Is required.

The differential waveform sample value Df (X _{i, m, n, q, r} ) is obtained.

Envelope added waveform sample value Is stored in the register R (OWD) in the old waveform memory unit (2104) by the signal WROWD, and FA (2
The output data of (404) is supplied to the WA bus, logical inversion is performed by the signal INV, and the result is stored in the latch AL in the arithmetic unit (2108). The old envelope added waveform sample value is read from the old waveform memory unit (2104) by the signal RDOWD and stored in the latch BL in the arithmetic unit (2108).

Then, the difference waveform sample value is calculated by executing addition processing in the calculation unit (2108). Is obtained, and the differential waveform sample value is stored in the register R (OBR) in the OBR (2109) by the signal WOBR.

Update envelope data ED.

The signals RDEDL, RDΔED (corresponding to the instruction step 8) cause the envelope data ED from the ED memory unit (2105) to be Δ
Incremental data ΔED is read out from the ED generator (2103) to the WA bus and WB bus, respectively, and the arithmetic unit operates at the falling edge of the signal φ2
It is stored in each of the latches AL and BL in (2108).

Then, the addition processing (EDL + ΔED) is executed by the arithmetic unit (2108) to obtain the new envelope data ED, and the signal WREDL (corresponding to the instruction step 4) is used to register R (EDL) in the ED memory unit (2105) The new envelope data ED is stored in and the carrier output of the adder FA (2404) in the arithmetic unit (2108) is stored in the flag register ECF (2405) in the arithmetic unit (2108).

The envelope data EDU is read by the signal RDEDU (corresponding to the instruction step 6), and the addition unit of the contents of the register ECF (2405) and the envelope data EDU is executed by the arithmetic unit (2108) to obtain the new envelope. Calculate the data EDU.
The obtained envelope EDU is stored in the register R (EDU) in the ED memory unit (2105) by the signal WREDU.

Then, like the DRP (808), various data stored in the registers R (EDL), R (EDU), and R (OWD) by the signal WRRAM are stored in the respective memory areas designated by the channel code CHC. Transfer data.

The timing of supplying data to the analog buffer memory unit (812) and the DAC (811) will be described.

A signal CRDAS (corresponding to the instruction step 9) resets the write pulse generated in the write pulse generator (2110). Then, the signal WROBR (corresponding to the instruction step 11) is sent to the register R (OBR) in the OBR (2109) for the difference waveform sample value. Is stored, supplied to the DAC (811) to convert the digital signal to an analog signal and supplied to the analog buffer memory section (812), and also to the channel specified by the channel code CHC in the write pulse generation section (2110). The corresponding write pulse is set and supplied to the analog switches AW1 to AW8 in the analog buffer memory section (812). At this time, signal CL
When RF is "0" (when no calculation request is made), the write pulse is not set.

Table 13 shows the operation sequence of WDP (807). By sequentially executing the instruction steps shown in Table 13, the processing described above is realized.

The control signals shown in Table 13 will be described.

The signals described below are supplied from the sequencer (802).

RDWDI is the waveform data WDI supplied from DRP (808).
Instruction to supply to the WA bus.

RDWDII is the waveform data WDII supplied from DRP (808).
To supply to the WB bus.

RDΔED is the increment data ΔED based on the sustain data DSUS or damper data DDMP selected in the ΔED generator (2103).
As an instruction to supply to the WA bus.

RDSFA uses the output data of the shifter in the shifter block (2107) as WA
Instructions to supply to the bus.

RDEDL is an instruction to supply the envelope data EDL read from the memory M (EDL) in the ED memory unit (2105) to the WB bus.

RDMLP is the output data of the multiplier in the multiplication unit (2106) (upper 1
6 bits) command to supply to the WB bus.

RDEDU is an instruction to supply the envelope data EDU read from the memory M (EDU) in the ED memory unit (2105) to the WB bus.

RDSFB is the data stored in the register R (SFB) in the shifter unit (2107) / 2 ^q ) command to feed WB bus.

RDOWD is the WB of the envelope-added waveform sample value read from the memory M (OWD) in the old waveform memory unit (2104).
Instructions to supply to the bus.

WRMLP is an instruction to store the data on the WC bus in the multiplicand register R (MLP1) in the multiplication unit (2106).

WREDL is an instruction to store the data on the WC bus in the register R (EDL) in the ED memory unit (2105).

WRSFT is an instruction to store the data on the WC bus in the register R (SFT) in the shifter unit (2107).

WREDU is an instruction to store the data on the WC bus in the register R (EDU) in the ED memory unit (2105).

WROWD stores the data on the WC bus in the old waveform data memory section (21
Instruction to store in register R (OWD) in 04).

WROBR transfers the data on the WC bus to register R in OBR (2109).
Instruction to store in (OWR).

INV is an instruction that inverts the logic of the data on the WA bus and supplies the inverted data to the latch AL (2402) in the arithmetic unit (2108).

WADD1 is the input signal to FA (2404) in the calculation unit (2108).
An instruction to supply (+1).

WCRAL is an instruction to clear the latch AL (2402) in the operation unit (2108).

SELWE is a data selection instruction to be stored in the multiplier register R (MLP2) in the multiplication unit (2106). The selection data are coefficient data (MLP) supplied from the DRP (808) and envelope data EDL supplied from the ED memory unit (2105).

WRSFB is an instruction to store the output data of the shifter in the shifter unit (2107) in the register R (SFB) in the shifter unit (2107).

TBC is an instruction to supply the data on the WB bus to the WC bus.

CRDAS is an instruction to reset the write pulse supplied from the write pulse generator (2110) to the analog buffer memory (812).

TCA is an instruction to supply the output data of the FA (2404) in the calculation unit (2108) to the WA bus.

When the virtual key signal EADG shown in Table 12 is on, the gate E (2412) is selected by the gate selector (2413) in the arithmetic unit (2108), and the envelope data EDL, EDU Are both data (0000) ₁₆ . As a result, the envelope added waveform sample value (Q = 0, r = 0).

Then, when the virtual key signal EADG is turned off, the updating process (ED = ED + ΔED) of the envelope data ED is started. As a result, the arithmetic processing for obtaining the envelope-added waveform sample value shown in the equation (5) is performed, and the tone waveform having the attenuation characteristic is obtained.

Further, when the updating process of the envelope data ED progresses and the envelope data EDU becomes the state of (1111) ₂ , the gate B (2409) in the arithmetic unit (2108) is selected at the update timing of the envelope data EDU, and the envelope data EDU is selected. Is always
(1111) The state becomes ₂ . This state corresponds to the stop of sound generation of the musical tone waveform.

As described above, the waveform interpolation method is as shown in equation (2),
Interpolation coefficient with correction term Since it is realized by, it is possible to prevent the generation of unnecessary noise components even if the level difference between the waveforms is large.

Further, where there is little change in the waveform shape, the data can be compressed by reducing the waveform data stored in the data memory unit and increasing the number of repetitions.

In addition, the converter that converts analog signals into a single DAC
And an analog buffer memory section, so DA
Since only one C is required and each channel operates independently, intermodulation distortion due to quantization distortion does not occur even if two channels are played simultaneously.

Furthermore, because the sampling frequency is an integral multiple of the fundamental frequency of the waveform, it is possible to match all the aliasing components that occur and the sample wave components that occur due to quantization with the harmonics of the fundamental frequency. It is possible to create a sound that does not have any dirt.

Next, the mutual relation of each part in the musical sound generating unit (607) will be described.

First, the input register section (803) will be described. The input register unit (803) is a register R (ADD), R (DAT) for temporarily storing I / O port address data supplied from the CPU (603) and musical tone generation data or sustain data, and a CP.
A flag register (which stores the signal (using the signals ▲ ▼ ・ ▲ ▼ supplied from the CPU (603)) indicating that new data has been supplied from the U (603) to the input register unit (803) When the register WRCF gives an instruction, it becomes “1”, and the address stored in the register R (ADD) is the write address, and the channel code CHC supplied from the sequencer (802) is the read address.
A register file that stores the tone generation data stored in the register R (DAT) (stores eight channels of tone generation data and has a capacity of 8 bits × 8 words), and a register R
Sustain data based on (ADD) address data,
It is composed of an effect register section for storing damper data, beat data and effect control data.

The timing at which the new data stored in the register R (DAT) is transferred to the register file or the effect register section is the sequencer (80) when the register WRCF is "1".
When the signal WRDAT is supplied from 2), the data stored in the register R (DAT) is transferred to a predetermined address based on the I / O port address stored in the register R (ADD). After that, the register WRCF is reset.

The signal WRDAT supplied from the sequencer (802) is a control signal for fetching data into the register file or the effect register section, and is input at every timing of the instruction step 1 shown in Tables 9, 11, and 13. It is supplied to the register unit (803).

The reason why new data is loaded into the register file or effect register section at the timing of instruction step 1 is EDP (80
6), if the tone generation data and various effect data change during execution of various arithmetic processing inside the WDP (807) or DRP (808), correct arithmetic processing is not performed. Therefore, it is fetched in the instruction step 1 for starting the arithmetic processing.

Explanation of Mutual Relations The explanation corresponding to Channel 1 will be given. It is assumed that the calculation request flag signal CCRF is generated.

When the channel code CHC generated by the sequencer (802) reaches the timing of channel 1, the input register (80
The tone generation data corresponding to the channel 1 is supplied to the FDP (806), WDP (807), and DRP (808) from the register file in 3).

Then, as described in the detailed description of the DRP (808), the head address, the control data, the waveform data f (X _{i, n} ) from the DBK (606) are generated based on the tone generation data in the DRP (808). And f (X
_{i + 1, n} ) and the waveform data f (X _{i, n} ) and f (X _{i + 1, n} ) read from the coefficient data (N · m + n) α and DBK (606) obtained based on the control data. ) And are stored in the memory M (MD), the memory M (WDI), and the memory M (WDII) in the DRP (808) at the timing of the instruction step 11.

On the other hand, the WDP (807) reads from the memory M (MD), the memory M (WDI), and the memory M (WDII) in the DRP (808) based on the channel code CHC during the timing of instruction steps 1 to 10. The coefficient data and waveform data f (X _{i, n-1} ) and f (X
_{i + 1, n-1} ) is used to perform the waveform calculation processing as described in the detailed description of the WDP (807). Then, at the timing of instruction step 11, the calculation result (difference waveform sample value Is stored in register R (OBR) in WDP (807), and DAC (811)
Is supplied to.

The above-mentioned processes (1) to (4) are executed at the same timing of the instruction steps 1 to 11 corresponding to the channel 1 of the channel code CHC generated from the sequencer (802).

And again, the channel code CHC corresponding to channel 1
Is generated from the sequencer (802), the following processing is performed.

Similar to the above description, the musical tone generation data corresponding to the channel 1 is supplied to the FDP (806), WDP (807) and DRP (808).

Similar to the above description, the DRP (808) stores the start address, control data, and waveform data f (X
_{i, n + 1} ) and f (X _{i + 1, m + n} ) are read and stored in the memory M (MD), the memory M (WDI), and the memory M (WDII).

However, the difference from the contents explained above is that DBK (606)
The control data and the waveform data to be read from are data based on the above-mentioned timing, that is, the waveform number i and the waveform sample number n updated at the previous calculation timing of the channel 1.

Similar to the above, the waveform calculation processing is performed based on the data read from the memory M (MD), the memory M (WDI), and the memory M (WDII) in the DRP (808).

The data used for the waveform calculation processing at this calculation timing is the DRP (808) at the previous calculation timing of channel 1.
Waveform data f, coefficient data that has been read in
(X _{i, n} ) and f (X _{i + 1, n} ).

After that, based on the calculation request flag signal CLRF, the channel 1
The above processing is repeated at the calculation timing corresponding to.

As described above, the data read by the DRP (808) is
It is used for the waveform calculation processing performed by the WDP (807) at the next calculation timing (when the calculation request flag signal CLRF is generated).

As described above, the reading and waveform calculation processes are not all executed within the same calculation timing, but the processing timing is divided and the pipeline process is performed, whereby the operation speed of the constituent elements of each unit can be reduced.

In the above description, the waveform data stored in the data memory (DBK) was stored in the form of PCM data for one waveform cycle, but the result of performing waveform symmetry, DPCM conversion, and ADPCM conversion was Is stored in the DBK as the waveform data, and the decompression process is performed inside the DRP (808), whereby the data compression of the waveform data becomes possible.

EFFECTS OF THE INVENTION As described above, the musical tone generating apparatus of the present invention is configured so that at least two or more musical tone waveforms among a plurality of musical tone waveforms from the start of musical tone generation to the end of the musical tone generation are independent of each musical range or plural musical range. Data memory section for storing control data used for forming a synthesized waveform using a musical tone waveform, a note clock generating section for determining a note scale, and a signal output of the note clock generating section and a range or scale. A data reading unit that reads out two waveform sample data and control data independently prepared for each range or scale from the data memory unit based on designated data, and two waveform sample data and control data read by the data reading unit And the waveform calculation section for obtaining the synthesized waveform sample data, and the digital output signal of the waveform calculation section. A conversion unit for converting the signal into an analog signal, and the contents of calculation executed by the waveform calculation unit are two waveform samples f (Xi, n) read by the data reading unit,
f (Xi + 1, n) and the number of waveform transitions from f (Xi) to f (Xi + 1) are M
Using the control data and the waveform interpolation calculation described in the claims, the virtual sample value Since (Xi, m, n) is generated and a musical tone waveform is generated, the musical tone generation shape can be smoothly changed with time, and a natural musical instrument sound can be simulated. .

In addition, note clocks are generated independently for each scale, and the range is generated by the number of musical sound waveform samples.Therefore, the sampling frequency, which is the output signal of the note clock generator, is multiplied by an integer multiple of the fundamental frequency of the waveform. Therefore, it is possible to make all the folded portions to be reproduced and the sample wave components generated by the quantization coincident with the harmonics of the fundamental frequency, and to produce a sound without any turbidity.

Further, there is an advantage that an independent tone waveform can be generated for each tone range and a fixed-formant tone can be realized.

[Brief description of drawings]

1 to 5 are explanatory views of the operation of the present invention, FIG. 6 is a block diagram of an electronic musical instrument employing the musical tone generating apparatus of the present invention, and FIG.
The figure is a time chart when the data is supplied from the CPU (603) to the musical sound generating unit (607). Fig. 8 is a block diagram of the musical sound generating unit (607). Fig. 9 is a specific example of the sequencer (802). FIG. 10, FIG. 10 is an operation time chart of the sequencer (802), FIG. 11 is a block diagram of a specific example of the analog buffer memory unit (812), and FIG. 12 is an inside of the tone generation unit (607). The operation time chart and Fig. 13 show the comparison register section (8
Fig. 14 shows the transition of the frequency data supplied to the FDP (80).
6) A configuration diagram of a specific example, FIG. 15 is a process flow chart showing the data processing procedure of the FDP (806), and FIG. 16 is a comparison register unit (805).
FIG. 17 is a block diagram showing a concrete example of the calculation request flag generator (810), FIG. 18 is a data block diagram of DBK (606), and FIG. 19 is a DRP (808). ) Is a block diagram showing a specific example, FIG. 20 is a flow chart of the calculation processing of WDP (807), and FIG.
FIG. 22 is a block diagram showing a concrete example of P (807), FIG. 22 is a block diagram showing a concrete example of a vibrato generator (1403), and FIG.
913) is a block diagram showing a specific example, and FIG. 24 is a block diagram showing a specific example of a calculation unit (2108). (601) ... keyboard part, (602) ... operation part, (603) ... central processing unit, (604) ... RAM, (605) ... ROM, (606) ... tone synthesis data ROM, ( 607) ... Music tone generator, (801) ... Main oscillator, (802) ... Sequencer, (803) ... Input register, (804) ... Timer, (805) ... Comparison register, (8
06) …… Frequency data processor, (807) …… Waveform data processor, (808) …… Data read processor, (809)
...... Read pulse formation unit, (810) …… Calculation request flag generation unit, (811) …… DAC, (812) …… Analog buffer memory unit, (813) …… Integrator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masataka Nikaido 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Tatsuya Adachi, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. 72) Inventor Tetsuhiko Kinaki 1006, Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-54-39616 (JP, A) JP-A-54-65020 (JP, A) 55-60192 (JP, U)

Claims (1)

[Claims] 1. At least two or more musical tone waveforms among a plurality of musical tone waveforms from the start of tone generation to the end of tone generation are independently prepared for each musical range or a plurality of musical scales, and a synthetic waveform is formed using the musical tone waveforms. A data memory unit that stores control data used when forming, a note clock generation unit that determines a sounding scale, a signal output of the note clock generation unit, and a range or a range from the data memory unit based on the range or scale designation data. A data reading section for reading out two waveform sample data and control data independently prepared for each scale, and a waveform calculation for obtaining synthetic waveform sample data using the two waveform sample data and control data read by the data reading section And a converter for converting the digital output signal of the waveform calculator into an analog signal. The contents of calculation executed by the waveform calculation unit are the two waveform samples f (Xi, n) and f (Xi + 1, n) read by the data reading unit and f (Xi) to f (Xi + 1). Using the control data with the number of waveform transitions to M A musical tone generating device that generates a musical tone waveform by obtaining (Xi, m, n). i = 0,1,2, ..., I-1 waveform number m = 0,1,2, ..., M-1 repeated number n = 0,1,2, ..., N-1 waveform number of samples