JPH06324105A - Semiconductor test equipment - Google Patents

Abstract

PURPOSE:To control the load impedance of a circuit by providing a control function of output impedance on the buffer amplifier of a load circuit consisting of the buffer amplifier of threshold voltage, high and low level current sources, and a diode bridge circuit. CONSTITUTION:A test pattern formed by a pattern generator 1 and a timing signal formed by a timing generator 2 are applied to a waveform formatter 3 to form a test waveform. The test waveform is converted to the theoretical voltage level of an element 18 to be tested by a driver 5, and applied to the element 8. The element 8 outputs a signal as the reply to the test waveform. This signal is received by a comparator 6, and compared with the logic level voltage of the element 8 to conduct high and low level judgment, and the result is outputted to a digital comparator 4. The comparator 4 compares it with the expected value of the signal for good element to be tested of the generator 1 at the timing of the signal of the generator 2 to conduct non-defective/ defective judgment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for testing semiconductor elements, and more particularly to a semiconductor test apparatus capable of accurately controlling load characteristics of an element under test.

[0002]

2. Description of the Related Art Conventional semiconductor test equipment is the Proceedings International Test Conference.
(1986) pp. 161 to 168 (Proceed
ingsInternational Test Conference (1986) p
p. 161 to 168). As shown in FIG. 6, the load circuit of the device under test of this semiconductor test apparatus is composed of a current buffer 16, diodes 15a to 15c, and constant current sources 14a to 14b. Current buffer 16
When the output voltage of the device under test rises above the threshold voltage VT input to, the current IOH is taken from the device under test by the constant current source 14b. On the other hand, when the output voltage of the device under test drops below the threshold voltage VT input to the current buffer 16, the constant current source 14a causes the current IOL to flow into the device under test, and the load condition specified in the specifications is met. We are conducting semiconductor tests.

[0003]

According to the above-mentioned conventional technique, a specified current can be flown while the device under test outputs a high level and a low level, but the current-voltage characteristic of the circuit shown in FIG. As can be seen from the above, the characteristics at the time of transition from the high level to the low level and from the low level to the high level are the characteristics of the diode bridge composed of the diodes 14a to 14d.
Did not always match the characteristics of. Therefore, the AC characteristics such as the access time of the high-speed device under test cannot be accurately measured. An object of the present invention is to perform a semiconductor test including a load circuit capable of controlling not only the high level current I0H and the low level current I0L but also the load impedance between the high level and the low level in the voltage-current characteristics of the load circuit as described above. To provide a device.

[0004]

In order to achieve the above object, a load circuit according to the present invention is a load including a threshold voltage buffer amplifier, a high level current source, a low level current source, and a diode bridge circuit. In the circuit, the buffer amplifier is provided with a control function of output impedance.

[0005]

The output impedance of the load circuit between the maximum output current values can be controlled by varying the output impedance of the buffer amplifier of the load circuit.

[0006]

Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a semiconductor test apparatus equipped with a load circuit according to the present invention. Figure 1
In the semiconductor test apparatus, the pattern generator 1, the timing generator 2, the waveform formatter 3, the digital comparator 4, the driver 5, the comparator 6, the load circuit 7, D
It is composed of A converters 10a to 10d, a control computer 9, and a bus 11 connecting them. Load circuit 7
Prior to the test, the control computer 9 applies each set value to the DA converters 10a to 10d via the bus 11.
Since its output is connected to the load circuit, the threshold voltage VT, the high level current IOH, and the low level current IO
L and the gain VGAIN of the load circuit 7 are set.

Next, the operation of the embodiment of the present invention will be described. The test pattern created by the pattern generator 1 and the timing signal created by the timing generator 2 are applied to the waveform formatter 3 to create a test waveform. The created test waveform is converted into the logic voltage level of the device under test 8 by the driver 5 and applied to the device under test 8.
The device under test 8 outputs a signal in response to the applied test waveform. The output signal is received by the comparator 6 and compared with the logic level voltage of the device under test 8 to determine the high level and the low level, and the result is output to the digital comparator 4. The digital comparator 4 is a timing signal generated by the timing generator 2 based on the logic value of the signal output by the non-defective device under test created by the pattern generator 1, that is, the expected value and the output logical value of the device under test 8 from the comparator. The comparison is judged at the timing of, and the good product and the defective product are judged. Here, the load circuit 7 is the device under test 8
Outputs a signal, the active signal ON-P of the load circuit 7 is activated by the signal generated by the timing generator 1 and enters the operating state. Therefore, when the voltage value of the output signal of the device under test 8 is equal to or higher than the threshold voltage VT, a high level current IOH is passed, and when the voltage value is equal to or lower than the threshold voltage VT, a low level current IOL is passed through the device under test 8. . The load circuit 7 according to the present invention provides an output impedance between the high level output voltage and the low level output voltage of the device under test 8 with a gain V.
Since it can be controlled by GAIN, it is possible to accurately satisfy the load condition at the time of the test specified by the test specification.

Next, the operation of the load circuit 7 will be described with reference to FIGS. FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3, 4, and 5 show voltage-current characteristics of the output of the load circuit 7. The load circuit 7 according to the present invention includes a current buffer BUF and a diode bridge D1 to D1 of the conventional load circuit.
A resistor R1 for controlling the output impedance of the current buffer and a variable gain OP amplifier OP3 are provided between D4. The threshold voltage VT is applied to the input of the current buffer BUF. The high level current terminal IOH and the low level current terminal IOL for setting the maximum current
Is applied with a voltage proportional to the amount of current.

First, the state where the active signal ON-P is high will be described with reference to FIG. FIG. 3 shows the relationship between the output voltage VDUT of the device under test by the load circuit 7 and the current IO flowing from the output of the device under test.
When the output voltage VDUT of the device under test is smaller than the threshold voltage VT, the current designated by the low level current IOL is passed through the device under test. On the other hand, the output voltage V of the device under test
When the DUT is higher than the threshold voltage, the load circuit 7 causes the current indicated by the high level current IOH to flow through the device under test. If the voltage gain of the variable gain OP amplifier OP3 is controlled by the gain control terminal VGAIN, the resistance R1
The impedance Z1 at both ends of is: Z1 = R1 / (1 + Av) (1) However, since Av becomes the voltage gain of OP3, the impedance at both ends of the resistor can be controlled by the voltage gain. Therefore, if the voltage gain is sufficiently large by the gain control terminal VGAIN,
Since the impedance between both ends of the resistor R1 becomes small,
The voltage-current characteristic of the load circuit shown in FIG.
By T, the high level current IOH and the low level current IO
It becomes the characteristic that L changes immediately. On the other hand, FIG. 4 shows a characteristic in which the voltage / current gain is adjusted by the gain control terminal VT, and an intermediate current value between the high level current and the low level current exists near the threshold value. Since the slope of this portion can be changed by the voltage value applied to the gain control terminal VGAIN, it is possible to match the input characteristics of the TTL that is the load condition of the LSI, and the number of TTL that is the load and the load. The impedance at both ends of the resistor R1 can be changed according to the equation (1) according to the logic element to be expressed as follows. Therefore, the load characteristic can be changed. FIG. 5 shows the active signal O
This is the output characteristic of the load circuit when N-P is at the low level. When the semiconductor test apparatus applies a test signal to the device under test 8, the active signal ON-P of the timing signal generated by the timing generator 2 causes a high impedance state so that it does not become a load on the driver of the semiconductor test apparatus. Operate. This is the active signal ON-
Since P is input to the current switch composed of the transistors Q3 to Q6 supplying the current to the diodes D1 to D4 forming the diode bridge via the level shift circuit, the current is cut off, so that FIG. As shown, the output of the load circuit has a high impedance because it does not flow a current regardless of the output voltage of the device under test.

Next, a method of controlling the currents IOH and IOL will be described. First, the low level current IOL will be described. The low level current IOL is the OP amplifier OP
1, transistors Q1 and Q2, and resistors R2 and R3.
Created by R6. The transistors Q1 and Q2 and the resistors R2 and R6 have the same size and the same resistance value. Therefore, the collector currents of the transistors Q1 and Q2 are the same, and this current is
3 and the voltage is error-amplified with the set value of the low level current IOL by the OP amplifier OP1, and the transistor Q
Since the bases of 1 and Q2 are driven, the collector current of the transistor Q2 becomes IOL. In the description here, the collector currents flowing through the transistors Q1 and Q2 are the same, but the size of the transistor Q1 is 1 / N and the resistance R2 is 2.
By multiplying the value of R3 by N times, the transistor Q1
Even if the collector current of 1 is set to 1 / N, the same effect can be obtained, and the current consumption can be reduced.

On the other hand, the high-level current IOH has the same structure as the low-level current IOL, and the direction of the current is opposite. Therefore, the transistor is changed from PNP to NPN and the polarity of the power source is reversed. Therefore, it is self-evident that it has the same function except that the direction of the low-level current and the current to be controlled are opposite, which will not be described again here.

In the load circuit according to the present invention, the resistor R
Since 3 and R4 detect the amount of current flowing through them, absolute precision is required, but other resistors need only have relative precision with each other, and transistors are similar, so it is easy to use monolithic ICs. Can be Resistors R3 and R
Regarding No. 4, a resistor such as NiCr or SiCr
If it can be used in an IC process and laser trimming can be performed, the entire load circuit can be made into a monolithic IC. Furthermore, the DA converter for setting has recently been monolithic I.
It is self-evident that it has been made into C and that a one-chip IC can be made including this.

In this embodiment, one load circuit has been described, but in practice, it is sufficient to prepare a sufficient number of circuits for testing the device under test, and the effectiveness of the present invention is limited by the number of load circuits. It will not be done.

[0015]

Since the present invention is configured as described above, a gain adjusting circuit for controlling the output impedance is provided in the load circuit that constitutes the semiconductor test apparatus that produces the effects described below. IC, LS
Since the test can be performed under a load condition equal to the load condition such as TTL described in the specification of I, an accurate test can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor test apparatus showing an embodiment of the present invention.

FIG. 2 is a block diagram of the load circuit of FIG.

FIG. 3 is a voltage-current characteristic diagram of a load circuit.

FIG. 4 is a voltage-current characteristic diagram of a load circuit.

FIG. 5 is a voltage-current characteristic diagram of a load circuit.

FIG. 6 is a block diagram of a conventional load circuit.

FIG. 7 is a voltage-current characteristic diagram of a conventional load circuit.

[Explanation of symbols]

 1 ... Pattern generation circuit, 2 ... Timing generator, 3 ... Waveform formatter, 4 ... Digital comparator, 5 ... Driver, 6 ... Comparator, 7 ... Load circuit, 9 ... Control computer, 10 ... DA converter, 11 ... Bus .

Claims (2)

[Claims] 1. In a semiconductor test apparatus, each means for controlling a threshold voltage, a high level current, a low level current and an output voltage / current characteristic near the threshold voltage as a load of an element under test, and these means. A semiconductor test apparatus comprising a load circuit provided with means for enabling or disabling the operation of the means. 2. A load circuit comprising a threshold current buffer and an IO.
The semiconductor test according to claim 1, wherein the semiconductor test comprises a current source for L and IOH, a diode bridge, a current switch, a level shift circuit, a resistor and a variable gain amplifier, and the gain of the variable gain amplifier is externally adjusted. apparatus.