JPH06324935A - Address generator and address generation system - Google Patents

Abstract

PURPOSE:To provide an address generator which can efficiently perform the preparing operation of data transfer. CONSTITUTION:This two-dimensional address generator is composed of MXN (M and N are integers showing the number of data or the number of addresses of a memory) pieces of rectangular areas and provided with multiplexers 106, 109 and 110, adder 107, integration registers 111 and 112, start address data storage device 101, storage device 102 for increased data in a main scanning direction, storage device 103 for increased data in a sub scanning direction, storage device 104 for the number of data in the main scanning direction, storage device 105 for the number of data in the sub scanning direction and control circuit 108. Start address data, the increased data in the main scanning direction, the increased data in the sub scanning direction, the number of data in the main scanning direction and the number of data in the sub scanning direction are selected and set in one cycle corresponding to selector configuration and a mode control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generator and an address generating system for generating a two-dimensional address for accessing an internal image memory or an external image memory by a digital signal processor or the like.

[0002]

2. Description of the Related Art Generally, data stored in a memory in a two-dimensional manner such as image data must be mapped in a one-dimensional address space. Normally, in the case of image data, the images are mapped to one-dimensional addresses in the order of raster scanning. When treating this data as two-dimensional data, a rectangular area is often cut out and used.

In the case of image data, which is a typical example of two-dimensional data, image processing using a local neighborhood of a pixel of interest or division of all images used in image data compression into block images is not possible. , 3 × 3 pixels or 8 × 8
A rectangular area such as a pixel is a processing target. 9 and 10
The image data is mapped in the one-dimensional address space. In FIGS. 9 and 10, 901 is an access target rectangular area (M × N), 902 is entire image data (Q × P), and 903 is actual mapping on a memory.

As shown in FIGS. 9 and 10, a rectangular area containing image data is divided and arranged in a memory, and in order to continuously extract the data in the rectangular area, two areas are required.
An address generator is needed to generate the dimension address.
DMA (direct memory access) transfer from an external image memory to an internal image memory is performed using this address generator, and digital signal processing is performed in synchronization with memory access by the address generator.

As a conventional address generator of this type,
For example, there is one as shown in FIG. The configuration of the conventional address generator will be described below with reference to FIG. In this case, the two-dimensional data will be described as certain image data. In FIG. 7, 701 is a start address register, and 70
2 is a main scanning direction increment data register, 703 is a sub scanning direction increment data register, 704 is a main scanning direction data number register, 705 is a sub scanning direction data number register, 7
06 is the first multiplexer, 707 is an adder, and 708
Is a control circuit, 709 is a second multiplexer, 710 is a third multiplexer, 711 is a first accumulation register,
712 is a second accumulation register, 713 is a first control signal,
Reference numeral 714 is a second control signal, and 715 is a third control signal.

The operation of the conventional address generator will be described below with reference to FIG. An M × N rectangular area is the access target. First, using the 0th to 4th cycles, a start address register 701, a main scanning direction increment data register 702, a sub scanning direction increment data register 703, a main scanning direction data number register 704, and a sub scanning direction data number register 705 are used. The start address, the increment data in the main scanning direction, the increment data in the sub-scanning direction, the number of data in the main scanning direction, and the number of data in the sub-scanning direction are set in each of the five registers, one by one, for each cycle. In the above five cycles, various data are registered in the register 7
It is set to 01 to 705.

After that, in the 0th cycle of the two-dimensional address generation (different from the 0th cycle of the above data setting), the second multiplexer 709 selects the start address data of the start address register 701 by the second control signal. Then, a start address is set as an initial value in the first accumulation register 711 and the second accumulation register 712.

In the next first cycle, the first multiplexer 706 is operated by the first, second and third control signals.
To select the sub-scanning direction increment data in the sub-scanning direction increment data register 703, to select the addition result of the adder 707 in the second multiplexer 709, and to select the third multiplexer 7
Select the data of the first accumulation register 711 with 10,
The data in the first accumulation register 711 and the sub-scanning direction increment data in the sub-scanning direction increment data register 703 are added by the adder 707, and the addition result is written in the first accumulation register 711.

After that, each cycle from the second cycle to the (M-1) th cycle continues the same operation as the first cycle. Next, in the Mth cycle, the first, second and third
Control signal of the first multiplexer 706 selects the increment data register 702 in the main scanning direction, the second multiplexer 709 selects the addition result of the adder 707, and the third multiplexer 710 selects the second accumulation register 712.
Data of the second accumulation register 712 and the main scanning direction increment data of the main scanning direction increment data register 702 are added by the adder 707, and the addition result is stored in the first accumulation register 711. And the second accumulation register 7
Write in 12 and.

Similarly, from the (M + 1) th cycle to the (2M-1) th cycle.
Up to the cycle, ... In each cycle from the (N−1) M + 1th cycle to the NM−1th cycle, the first multiplexer 70 is controlled by the first, second and third control signals.
6 selects the sub-scanning direction increment data of the sub-scanning direction increment data 703, the second multiplexer 709 selects the addition result of the adder 707, and the third multiplexer 710 selects the data of the first accumulation register 711. Is selected, the data of the first accumulation register 711 and the sub-scanning direction increment data of the sub-scanning direction increment data register 703 are added by the adder 707, and the addition result is written to the first accumulation register 711. Take control.

The Mth cycle, the second M cycle,
..., in each cycle of the (N-1) Mth cycle,
The first and second control signals select the increment data register 702 in the main scanning direction by the second and third control signals, the second multiplexer 709 selects the addition result of the adder 707, and the third multiplexer 710 selects the second data. Data of the second accumulation register 712 and main scan direction increment data register 7 are selected.
No. 04 increment data in the main scanning direction and the addition result is added to the first accumulation register 711 and the second accumulation register 71.
2 and write control.

Then, the data of the first accumulation register 711 is output from the 0th cycle to the NM-1th cycle.
Normally, a digital signal processor transfers an image data of a two-dimensional array stored in an external memory to an internal memory in an M × N rectangular area from one external memory to one internal memory. This is a data array transfer, and one data is stored for each cycle in the source side memory (external memory).
It was an extremely simple address generation system characterized by reading data from the memory and writing the read data to the memory (internal memory) on the destination side every cycle.

A conventional address generating system of this type is, for example, as shown in FIG. In FIG. 8, 801 is an external memory, 802 is a processor, and 803.
Is a control circuit, 804 is an external memory address generator, 8
05 is an arithmetic unit, 806 is an internal memory address generator,
807 is an internal memory, 808 is a first clock signal, 80
9 is an external memory address, 810 is external memory data,
Reference numeral 811 indicates a second clock signal, 812 indicates an internal memory address, and 813 indicates internal memory data. The address generator of FIG. 7 is used as the external memory address generator 804 and the internal memory address generator 806.

The operation of the address generation system of FIG. 8 will be described with reference to FIG. FIG. 11 shows how the image data is actually accessed. In FIG. 11, 1001
Is the rectangular area to be accessed stored in the external memory,
Reference numeral 1002 is the entire image data stored in the external memory, 1003 is the access target rectangular area stored in the internal memory, and 1004 is the overall image data stored in the internal memory. In this case, 0 to 59 are the actual memory addresses, and (0) to (15) represent the pixel numbers to be accessed.

On the external memory side, 1 is set as the sub-scanning direction increment data, and the number of data of 1 line is set as 10 as the main scanning direction increment data. In the 0th cycle, 13 is set as the start address, and in each cycle from the 1st cycle to the 3rd cycle, the increment data 1 in the sub-scanning direction is sequentially added to 13 to generate the addresses 14, 15 and 16.

In the fourth cycle, the increment data 1 in the main scanning direction is stored in the address 13 held in the second accumulation register.
0 is added to generate the address 23. In each cycle from the fifth cycle to the seventh cycle, 23 is sequentially added with the sub-scanning direction increment data 1 to add addresses 24, 25,
26 is generated. Similarly, the addresses 33, 3
4, 35, 36, 43, 44, 45, 46 are sequentially generated, and the rectangular area 1001 on the external memory side can be accessed.

The address generation of the rectangular area 1003 on the internal memory side is similar to that on the external memory side, but the address generated for each pixel transferred is one cycle longer on the internal memory side than on the external memory side. Running late. The state is shown in FIG. In FIG. 12, the first clock signal 80
8, external memory address 809, external memory data 81
0, second clock signal 811, internal memory address 81
2 is shown.

Further, the external memory data 810 is input to the pipelined arithmetic unit 805, and the arithmetic unit 805
It is also possible to output the internal memory data 813 from the device and perform various processes on the transfer data.

[0019]

However, in the address generator as shown in FIG. 7, the start address register 701, the main scanning direction increment data register 702, and the sub scanning direction increment data register 703 are accessed each time one rectangular area is accessed. The number of data in the main scanning direction data count register 704 and the data in the sub scanning direction data count register 705 must be set one by one in each cycle in any order, and a large number of cycles are required. is there.

In addition, in the address generation system as shown in FIG. 8, the internal memory 807 and the external memory 801 are accessed in synchronization with each other. Normally, the operating speed of the external memory 801 is lower than that of the internal memory 807. Since a slow memory has to be used, the transfer rate is limited to the access cycle of the external memory 801. Therefore,
The operation speed can be improved by reading multiple data of the same address from multiple external memories at the same time, but some of the data are valid and invalid, and it is necessary to distinguish between them. .

The object of the present invention is to reduce the number of cycles to 2
An object of the present invention is to provide an address generator that enables a preparatory operation for accessing dimension data. Another object of the present invention is to
An object of the present invention is to provide an address generation system capable of performing data transfer at an arbitrary multiple of the operation speed of an external memory.

[0022]

SUMMARY OF THE INVENTION The address generator of the present invention stores start address data, main scanning direction increment data, sub scanning direction increment data, main scanning direction data number and sub scanning direction data number which are actually used. According to the selector configuration and the control signal, data selected in advance is selected and a plurality of data is set in one cycle. That is, this address generator is M × N
An address generator that generates an address of a rectangular area (M and N are integers and indicates the number of data or the number of memory addresses), and includes first, second and third multiplexers, an adder, First and second accumulation registers, start address data storage device, main scanning direction incremental data storage device, sub scanning direction incremental data storage device, main scanning direction data number storage device, and sub scanning direction data number A memory device and a control circuit are provided.

Then, according to the control signal from the control circuit,
The start address data storage device, the main scanning direction incremental data storage device, the sub-scanning direction incremental data storage device, the main scanning direction data number storage device, and the sub-scanning direction data number storage device respectively store one data each in advance. The selected main scanning direction increment data and the sub scanning direction increment data are input to the first multiplexer, and either the main scanning direction increment data or the sub scanning direction increment data is selected by the first multiplexer. , The data of the first accumulation register and the data of the second accumulation register are input to the third multiplexer, and the data of the first accumulation register and the data of the second accumulation register are input by the third multiplexer. And the data selected by the first multiplexer and the data selected by the third multiplexer are added by the adder. The addition result of the adder and the start address data of the start address data storage device are input to the second multiplexer, and either the addition result of the adder or the start address data of the start address data storage device is input to the second multiplexer. The output of the second multiplexer is selected and input to the first accumulation register and the second accumulation register.

Further, in the 0th cycle, the start address data of the start address data storage device is selected by the second multiplexer, and the output of the second multiplexer is transferred to the first accumulation register and the second accumulation register. Set,
From the 1st cycle to the (M-1) th cycle, from the (M + 1) th cycle to the 2ndM-1 cycle, ..., (N-1) M + 1
In each cycle from the cycle to the NM-1th cycle, the third cycle
Multiplexer selects the data in the first accumulation register, the first multiplexer selects incremental data in the sub scanning direction, and the adder adds the data in the first accumulation register and the incremental data in the sub scanning direction. Then, the result is selected by the second multiplexer and written in the first accumulation register, and the control is performed. The Mth cycle, the second M cycle, ...
.. In each cycle of the (N-1) Mth cycle, the third multiplexer selects the data of the second accumulation register, the first multiplexer selects the increment data in the main scanning direction, and the adder Control for adding the data of the second accumulation register and the increment data in the main scanning direction, selecting the result by the second multiplexer, and writing the result in both the first accumulation register and the second accumulation register. The data of the first accumulation register is output in each cycle from the 0th cycle to the NM-1th cycle.

The address generating system of the present invention is such that data transfer to the internal memory is performed by a control circuit that prohibits writing of data other than valid data read from the external memory. In other words, this address generation system has Y (Y is an integer) external memory,
An internal memory and an external memory address generator (claim 1
Either the described configuration or the conventional configuration may be used.)
And an internal memory address generator (either the structure according to claim 1 or the structure according to the related art may be used), the first control circuit and the second control circuit, and the Y-input multiplexer.

Then, an M × N two-dimensional data array is mapped to the Y external memories so that the Y continuous data in the sub-scanning direction become the same address of another external memory one by one. The first control circuit generates the first clock signal, and the Y pieces of data depending on the same address of the Y pieces of external memories are simultaneously read out and read out every one cycle of the first clock signal. The Y data is input to the multiplexer, the first control circuit generates the second clock signal at a speed Y times that of the first clock signal, and is synchronized with the second clock signal within one cycle of the first clock signal. The configuration is such that Y pieces of data input to the multiplexer in the order from the first external memory to the Yth external memory are selected one by one, and L × N desired by the external memory address generator is used.
MY × N (MY indicates an integer) rectangular area (MY
mod L <X) address is generated, and Y data corresponding to the address is simultaneously read out for each cycle of the first clock signal and distributed to Y different data by the multiplexer, and the second control circuit is provided. The configuration is such that the second clock signal is input to generate the third clock signal from the second control circuit, and it depends on the first N addresses in the main scanning direction from the MY × N data output from the multiplexer. Desired M × N in the data sequence consisting of Y × N data
Of the data contained in the range of the rectangular region and the last N of the data in the Y × N data depending on the address in the main scanning direction, within the range of the desired M × N rectangular region. Only when the included data and all the data in the data string consisting of Y × N data that depends on a plurality of N addresses in the main scanning direction on the way are input as internal memory data. A second clock signal whose rising edge is valid is generated as a third clock signal from the second control circuit, and is synchronized with the third clock signal by the internal memory address generator to generate an arbitrary L × N rectangular area of the internal memory. I try to write it.

MYmod L means the remainder of MY ÷ L.

[0028]

According to the address generator of the present invention, conventionally, the start address data, the main scanning direction increment data, the sub scanning direction increment data, the main scanning direction data number, and the sub scanning direction data number are set one by one in a plurality of cycles. This is because the start address data storage device, the main scanning direction incremental data storage device, the sub-scanning direction incremental data storage device, the main scanning direction data number storage device, and the sub-scanning direction data number storage device are preloaded with data. By storing the data and selecting one data from each storage device, it becomes possible to execute the preparation operation for accessing the two-dimensional data in one cycle.

Further, according to the address generating system of the present invention, it is possible to read a plurality of data from a plurality of external memories at the same time and write only valid data to the internal memory, thereby increasing the data transfer speed.

[0030]

【Example】

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of the address generator of the present invention. The configuration of this address generator will be described with reference to FIG. Here, the two-dimensional data will be described as image data. In FIG. 1, 101 is a start address data storage device, 102 is a main scanning direction incremental data storage device, 103 is a sub scanning direction incremental data storage device, 104 is a main scanning direction data number storage device, and 105 is a sub scanning direction data number storage device. Device, 106 is a first multiplexer, 107 is an adder, 108 is a control circuit, 109
Is a second multiplexer, 110 is a third multiplexer, 111 is a first accumulation register, 112 is a second accumulation register, 113 is a first control signal, 114 is a second control signal, and 115 is a third control signal. Signal, 116 is the fourth control signal, 1
Reference numeral 17 is a field access target parameter.

This address generator stores the start address data storage device 101 and the main scanning direction incremental data storage by the first to fourth control signals (mode control signals) 113, 114, 115 and 116 from the control circuit 108. Device 102 and sub-scanning direction incremental data storage device 103
And the data stored in the main scanning direction data number storage device 104 and the sub scanning direction data number storage device 105 are selected one by one, and the selected main scanning direction increment data and sub scanning direction increment data are selected. The data is input to the first multiplexer 106 and either the main scanning direction increment data or the sub scanning direction increment data is selected by the first multiplexer 106, and the data of the first accumulation register 111 and the second accumulation register are selected. 112 data and the third multiplexer 1
10, the data of the first accumulation register 111 and the second accumulation register 112 are input to the third multiplexer 110.
Of the data, and the first by the adder 107
The data selected by the multiplexer 106 and the data selected by the third multiplexer 110 are added, and the addition result of the adder 107 and the start address data of the start address data storage device 101 are added to the second data.
To the first multiplexer 109, and the second multiplexer 109 selects either the addition result of the adder 107 or the start address data of the start address data storage device 101, and outputs the output of the second multiplexer 109 to the first accumulation. The arithmetic register 111 and the second accumulation register 112 are input.

The operation of the address generator of FIG. 1 will be described below with reference to FIG.
Will be described with reference to. In FIG. 4, 401 is an access target rectangular area stored in the memory, and 402 is the entire image data (10 × 6) stored in the memory. In this case, the 6 × 3 rectangular area is the access target. First, in one cycle, the value 12 stored in the start address data storage device 101, the value 20 stored in the main scanning direction incremental data storage device 102, and the value 1 stored in the sub scanning direction incremental data storage device 103. And the value 3 stored in the main scanning direction data number storage device 104
And the value 6 stored in the sub scanning direction data number storage device 105 is selected by the first control signal 113. That is, for all of the five storage devices 101 to 105, the field access target parameter 1
One piece of data is selected from the data held in advance as 17.

There is a frame as a unit of two-dimensional image data, and field access means that a data row in the sub-scanning direction of a frame is an odd-numbered sub-scanning-direction data row in the main scanning direction from top to bottom. Or an even-numbered sub-scanning direction data string in the main scanning direction is collectively accessed, which is often used in the field of image processing.

In the 0th cycle of address generation, the start address data storage device 101 is selected by the second multiplexer 109 by the third control signal 115, and the first accumulation register 111 and the second accumulation register 112 are selected. To
As the initial value, the value 12 of the start address is set.
In the next first cycle, the first multiplexer 106 selects the sub-scanning direction incremental data storage device 103 by the second, third, and fourth control signals, and the second multiplexer 109 selects the addition result of the adder 107. , The third multiplexer 110 selects the first accumulation register 111, and the data of the first accumulation register 111 and the value 1 selected from the sub-scanning direction increment data register storage device 103 are added. The value is added by the unit 107 and the result is written in the first accumulation register 111.

Thereafter, in each cycle from the second cycle to the fifth cycle, the same operation as the first cycle is continued. Next, in the sixth cycle, the second, third and fourth
In accordance with the control signal of 1, the first multiplexer 106 selects the main scanning direction incremental data storage device 102, the second multiplexer 109 selects the addition result of the adder 107,
In the third multiplexer 110, the second accumulation register 11
2 is selected, the data of the second accumulation register 112 and the increment data 20 in the main scanning direction are added by the adder 107, and the addition result is the first accumulation register 111 and the second accumulation register 112. And write both.

Similarly, in each of the cycles from the seventh cycle to the eleventh cycle, and from the thirteenth cycle to the seventeenth cycle, the first, second, third, and fourth control signals cause the first multiplexer 106 to perform sub-scanning. Select the direction increment data storage device 103 to select the second multiplexer 10
9 selects the addition result of the adder 107, the third multiplexer 110 selects the first accumulation register 111,
The data of the first accumulation register 111 and the sub-scanning direction increment data 1 are added by the adder 107, and the addition result is controlled to be written in the first accumulation register 111.

In the twelfth cycle, the first multiplexer 10 is controlled by the second, third and fourth control signals.
6 selects the main scanning direction incremental data storage device 102, the second multiplexer 109 selects the addition result of the adder 107, the third multiplexer 110 selects the second accumulation register 112, and the second The data of the accumulation register 112 and the increment data 20 in the main scanning direction are added, and the addition result is written in the first accumulation register 111 and the second accumulation register 112.

Then, in each cycle from the 0th cycle to the 17th cycle, the data of the first accumulation register 111 is output. FIG. 4 shows a data flow due to such an operation. In FIG. 4, 12 to 17, 32 to 37, 52 to 57 are actual memory addresses, and (0) to (17) represent the pixel numbers to be accessed. In this case, the sub-scanning direction increment data is 1, and the main scanning direction increment data is 2 lines of data number 2
Set to 0.

In the 0th cycle, 12 is set as the start address, and in each cycle from the 1st to the 5th cycle, the increment data 1 in the sub-scanning direction is sequentially added to 12 and the addresses 13, 14, 15, 16 are added. , 17 are generated.
In the sixth cycle, the main scanning direction increment data 20 is added to the address 12 held in the second accumulation register 112 to generate the address 32. 7th cycle to 1st
In each cycle up to one cycle, the sub scan direction increment data 1 is sequentially added to 32 to add addresses 33, 34, 3
5, 36, 37 are generated. Similarly, in each cycle from the 12th cycle to the 17th cycle, the addresses 52, 53, 54, 55, 56, 57 are sequentially generated, and the rectangular area can be accessed.

According to the address generator of this embodiment, the start address data storage device 101, the main scanning direction incremental data storage device 102, the sub scanning direction incremental data storage device 103, the main scanning direction data number storage device 104, and the sub scanning direction. By pre-storing data in each storage device such as the data number storage device 105 and selecting one data from each storage device, the preparatory operation for accessing the two-dimensional data can be executed in one cycle. It will be possible.

[Embodiment 2] FIGS. 2 and 3 show the construction of an embodiment of the address generating system of the present invention. First,
The configuration of this address generation system will be described with reference to FIG. In FIG. 2, 201 is a first external memory, 202 is a Yth external memory (Y is an integer of 2 or more), 203 is a processor, 204 is a first control circuit, and 205 is an external memory address generator. In the example, the address generator of FIG. 1 is used, but the conventional address generator of FIG. 7 may be used). 206 is a multiplexer,
Reference numeral 207 denotes a second control circuit, and 208 denotes an internal memory address generator (in this embodiment, the address generator of FIG. 1 is used, but the conventional address generator of FIG. 7 may be used). is there. 209 is a computing unit, 210 is an internal memory,
Reference numeral 211 is a first clock signal, 212 is an external memory address, 213 is first external memory data, 214 is Y-th external memory data, 215 is a second clock signal, 216 is a sub-address signal written in a sub-address register,
217 is a multiplexer output, 218 is a third clock signal, 219 is an internal memory address, and 220 is internal memory data.

The configuration of the second control circuit 207 in FIG. 2 is as shown in FIG. 3, for example. In FIG. 3, 301
Is a first counter, 302 is a second counter, 303 is a sub-address register, 304 is a decoder, 305 is a comparator, 306 is a multiplexer, 307 is an OR gate, 308 is a control signal, 211 is a first clock signal, 2
15 is the second clock signal, 216 is the sub-address signal,
218 is a third clock signal.

The operation of the address generator system of FIG. 2 will be described with reference to FIG. FIG. 5 shows how the image data is actually accessed. In FIG. 5, reference numeral 501 denotes an access target rectangular area of 6 × 4 pixels stored in a plurality of, for example, two external memories, 502 is a 0th data string of the access target rectangular area of the external memory, and 503 is access to the external memory. The first data string in the target rectangular area, 504 is the second data string in the rectangular area to be accessed in the external memory, 505
Is stored in a plurality of, for example, two external memories.
The entire image data of × 12 pixels, 506 is a 4 × 4 access target rectangular area stored in the internal memory, and 507.
Is the entire image data of 10 × 6 pixels stored in the internal memory.

0 to 59 are the addresses of the actual memory, (0) to (23) represent the numbers of the pixels to be accessed in the external memory, and (1) to (4), (7) to (10). Up to (13) to (16) and (19) to (22) are data numbers to be written in the internal memory. In this case, on the external memory side, 5 is set as the sub scanning direction increment data and 1 is set as the main scanning direction increment data.

In the 0th cycle, 6 is set as the start address, and in each cycle from the 1st cycle to the 3rd cycle, the increment data 5 in the sub-scanning direction is sequentially added to 6 to set the addresses 11, 16 and 21. To generate. Therefore, data (0) and (1), (6) and (7), (12)
In the order of (13), (18) and (19), two pieces of data are read from the 0th data string of the rectangular area to be accessed in the external memory every cycle.

In the fourth cycle, address 7 is generated by adding increment data 1 in the main scanning direction to address 6. Fifth
In each of the cycles from the 7th cycle to the 7th cycle, the subscanning direction increment data 5 is sequentially added to 7 to add the address 1
2, 17, and 22 are generated. Therefore, the data (2)
And (3), (8) and (9), (14) and (15), (2
In the order of 0) and (21), two pieces of data are read from the first data string of the rectangular area to be accessed in the external memory every cycle.

Similarly, addresses 8, 13, 1
8 and 23 are sequentially generated, and data (4), (5), and (1
0) and (11), (16) and (17), (22) and (2
2) of the rectangular area to be accessed in the external memory in the order of 3)
Two pieces of data are read from the data string every cycle. Also, the address generation of the rectangular area on the internal memory side is
Different from the external memory side, the address generated for each pixel to be transferred is performed on the internal memory side at a speed of Y (= 2) times that on the external memory side. Only part of the data read from the side is written to the internal memory side. Address generation and data writing on the internal memory side are executed in synchronization with the third clock signal 218. The third clock signal 218 is output to the second control circuit 207.
Generated by.

The internal memory access of the address generation system of the present invention will be described with reference to FIG. In FIG. 6, the first clock signal 211, the external memory address 212, the external memory data 601 (213, 214), the multiplexer output 217, the second clock signal 215, the first counter output 301, the second counter output 302, the control signal. Thirty
8, third clock signal 218, internal memory address 21
9 is shown.

First, the data 601 read from the external memory is passed through the multiplexer 206, and 1 to Y at a speed Y (= 2) times the input rate of the multiplexer 206.
The (= 2) th data is output and shown at the multiplexer output 217. The second clock signal 215 is Y (= 2) times faster than the first clock signal 211. The first counter 301 is the access target rectangular area 50 of the external memory.
The second counter 302 indicates the external memory number corresponding to each multiplexer output. The sub-address register 303 can be set to any value from 0 to Y (= 2), which means that data is valid from the 0th data column of the rectangular area 501 to be accessed in the external memory. This means that the data is invalid from the second data column of the access target rectangular area 501 of the external memory, that is, the number of the last column of the access target rectangular area 501 of the external memory.

In this case, the sub address register 303 is set to 1. The comparator 305 outputs a positive logic output that outputs “0” when the value of the second counter 302 is less than “1” and “1” when the value of the second counter 302 is more than “1”, and the value of the second counter 302 is less than “1”. In this case, a negative logic output is provided, which outputs "0" when the value is "1" or "1" or more. The multiplexer 306, when the output of the first counter 301 is “0”, that is, the access target rectangular area 501 of the external memory.
In the first column, the negative logic output of the comparator 305 is selected, and when the output of the first counter 301 is “2”, that is, in the last column of the access target rectangular area 501 of the external memory, the positive logic of the comparator is selected. The output is selected, otherwise "0" is selected and the control signal 308 is generated.

The control signal 308 and the second clock signal 2
15 is input to the OR gate 307, the third clock signal 218 is output, and the multiplexer output 217 is written to the internal memory 210 by the third clock signal 218. The internal memory address 219 is also generated in synchronization with the third clock signal 218, and this operation is similar to that of the circuit of FIG.

Further, the multiplexer output 217 is inputted to the arithmetic unit 209 which is pipelined, and the arithmetic unit 20
It is also possible to output the internal memory data 220 from 9 and perform various processing on the transfer data.

[0053]

According to the address generator of the present invention, conventionally, the start address data, the main scanning direction increment data, the sub scanning direction increment data, the main scanning direction data number, and the sub scanning direction data number are set in a plurality of cycles. However, the preparation operation for accessing the two-dimensional data can be executed in one cycle, and the preparation operation for address generation can be shortened.

According to the address generating system of the present invention, a plurality of data are simultaneously read from a plurality of source memories, and only valid data is received without taking in invalid data which has been a problem when increasing the data transfer speed. It becomes possible to write in the memory, and the practical effect of the present invention is great.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an address generator of the present invention.

FIG. 2 is a block diagram of an embodiment of the address generation system of the present invention.

3 is a configuration diagram of a second control circuit of the address generation system of FIG.

4 is a diagram showing an access target rectangular area of the address generator of FIG. 1. FIG.

5 is a diagram showing a rectangular area to be accessed by the address generation system of FIG.

FIG. 6 is a timing chart showing an operation of the address generation system of FIG.

FIG. 7 is a configuration diagram of a conventional example of an address generator.

FIG. 8 is a configuration diagram of a conventional example of an address generation system.

FIG. 9 is a conceptual diagram of image data.

FIG. 10A is a diagram showing the entire image data, and FIG.
FIG. 4 is a diagram showing mapping on a memory.

11 is a diagram showing an access target rectangular area of the address generation system of FIG. 8;

12 is a timing chart showing the operation of the address generation system of FIG.

[Explanation of symbols]

101 Start Address Data Storage Device 102 Main Scan Direction Incremental Data Storage Device 103 Sub Scanning Direction Incremental Data Storage Device 104 Main Scanning Direction Data Number Storage Device 105 Sub Scanning Direction Data Number Storage Device 106 First Multiplexer 107 Adder 108 Control Circuit 109 Second multiplexer 110 Third multiplexer 111 First accumulation register 112 Second accumulation register 113 First control signal 114 Second control signal 115 Third control signal 116 Fourth control signal 117 Field access target parameter 201th 1 External Memory 202 Yth External Memory 203 Processor 204 First Control Circuit 205 External Memory Address Generator 206 Multiplexer 207 Second Control Circuit 208 Internal Memory Address Generator 209 Arithmetic Unit 210 In Memory 211 First clock signal 212 External memory address 213 First external memory data 214 Yth external memory data 215 Second clock signal 216 Sub-address signal 217 Multiplexer output 218 Third clock signal 219 Internal memory address 220 Internal memory data 301 First counter 302 second counter 303 sub-address register 304 decoder 305 comparator 306 multiplexer 307 OR gate 308 control signal 401 access target rectangular area stored in memory 402 overall image data stored in memory 501 stored in multiple external memories Access target rectangular area 502 0th data string 503 1st data string 504 2nd data string 505 Total of data stored in multiple external memories Entire image data 601 external memory data stored in the access target rectangular area 507 internal memory which is stored in the image data 506 internal memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiyuki Ogi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. An address generator for generating an address of a rectangular area of M × N (where M and N are integers and represents the number of data or the number of memory addresses), the first, second and 3 multiplexer, adder,
First and second accumulation registers, start address data storage device, main scanning direction incremental data storage device, sub scanning direction incremental data storage device, main scanning direction data number storage device, and sub scanning direction data number A storage device and a control circuit are provided, and the start address data storage device, the main scanning direction increment data storage device, the sub-scanning direction increment data storage device, and the main scanning direction data number are controlled by a control signal from the control circuit. The data previously stored in the storage device and the sub-scanning direction data number storage device are selected one by one, and the selected main scanning direction increment data and sub-scanning direction increment data are input to the first multiplexer. Then, the first multiplexer selects either the main scanning direction increment data or the sub scanning direction increment data, and the first accumulation The register data and the data of the second accumulation register are input to the third multiplexer, and the data of the first accumulation register and the data of the second accumulation register are input by the third multiplexer. Any one of them is selected, and the data selected by the first multiplexer and the data selected by the third multiplexer are added by the adder, and the addition result of the adder and the start address data storage The start address data of the device is inputted to the second multiplexer, and the second multiplexer selects either the addition result of the adder or the start address data of the start address data storage device, and the second multiplexer The output of the multiplexer of the first
Of the start address data storage device is selected by the second multiplexer in the 0th cycle, and the start address data of the second multiplexer is selected. Output the first
And the second accumulation register,
From the 1st cycle to the (M-1) th cycle, from the (M + 1) th cycle to the 2ndM-1 cycle, ..., (N-1) M + 1
In each cycle from the cycle to the NM−1th cycle, the third multiplexer selects the data of the first accumulation register, the first multiplexer selects the increment data in the sub-scanning direction, and the addition is performed. The data in the first accumulation register and the increment data in the sub-scanning direction are added by a controller, the result is selected by the second multiplexer and written in the first accumulation register.
Mth cycle, 2nd M cycle, ..., (N-1) th cycle
In each cycle of M cycles, the third multiplexer selects the data of the second accumulation register, the first multiplexer selects the main scanning direction increment data, and the adder adds the second data. The data of the accumulation register and the increment data in the main scanning direction are added, and the result is selected by the second multiplexer and written to both the first accumulation register and the second accumulation register. An address generator for controlling and outputting the data of the first accumulation register in each cycle from the 0th cycle to the NM-1th cycle. 2. Y (where Y is an integer) external memories, an internal memory, an external memory address generator, an internal memory address generator, a first control circuit and a second control circuit.
A control circuit and a Y-input multiplexer are provided, and M × N two-dimensional data array is provided in the Y external memories.
Y data that are continuous in the sub-scanning direction are mapped one by one so as to have the same address in another external memory, and the first control circuit generates a first clock signal so that the Y data is generated. The Y pieces of data which depend on the same address of the external memory are simultaneously read every one cycle of the first clock signal, the read Y pieces of data are inputted to the multiplexer, and the first control circuit is arranged to Generate a second clock signal at a speed Y times that of the first clock signal,
In a cycle of the first clock signal, in synchronization with the second clock signal, Y data inputted to the multiplexer in order from the first external memory to the Yth external memory are selected one by one. , MY × N (MYmod L <X) addresses including the desired L × N (L is an integer) rectangular area are generated by the external memory address generator, and Y addresses corresponding to the addresses are generated. Data is the first
The clock signals are simultaneously read out for each cycle and distributed to Y different data by the multiplexer, and the second clock signal is input to the second control circuit to generate the third clock signal from the second control circuit. Of the MY × N data output from the multiplexer, and the desired M × N data in the data sequence consisting of the Y × N data depending on the first N main scanning direction addresses is selected. Included in the range of the desired M × N rectangular area in the data string consisting of the data included in the rectangular area and the last N pieces of Y × N data depending on the main scanning direction address. Only when the stored data and all the data in the data string consisting of Y × N data depending on the plurality of N addresses in the main scanning direction are input as internal memory data. Standing The second that made the rise effective
A clock signal is generated as a third clock signal from the second control circuit, and is written in an arbitrary L × N rectangular area of the internal memory in synchronization with the third clock signal by the internal memory address generator. An address generation system characterized in that 3. Y (where Y represents an integer) external memories, an internal memory, an external memory address generator having the configuration according to claim 1, and an internal memory having the configuration according to claim 1. An address generator, a first control circuit, a second control circuit, and a Y-input multiplexer are provided, and an M × N two-dimensional data array is provided in the Y external memories.
Y data that are continuous in the sub-scanning direction are mapped one by one so as to have the same address in another external memory, and the first control circuit generates a first clock signal so that the Y data is generated. The Y pieces of data which depend on the same address of the external memory are simultaneously read every one cycle of the first clock signal, the read Y pieces of data are inputted to the multiplexer, and the first control circuit is arranged to Generate a second clock signal at a speed Y times that of the first clock signal,
In a cycle of the first clock signal, in synchronization with the second clock signal, Y data inputted to the multiplexer in order from the first external memory to the Yth external memory are selected one by one. , MY × N (MYmod L <X) addresses including the desired L × N (L is an integer) rectangular area are generated by the external memory address generator, and Y addresses corresponding to the addresses are generated. Data is the first
The clock signals are simultaneously read out for each cycle and distributed to Y different data by the multiplexer, and the second clock signal is input to the second control circuit to generate the third clock signal from the second control circuit. Of the MY × N data output from the multiplexer, and the desired M × N data in the data sequence consisting of the Y × N data depending on the first N main scanning direction addresses is selected. Included in the range of the desired M × N rectangular area in the data string consisting of the data included in the rectangular area and the last N pieces of Y × N data depending on the main scanning direction address. Only when the stored data and all the data in the data string consisting of Y × N data depending on the plurality of N addresses in the main scanning direction are input as internal memory data. Standing The second that made the rise effective
A clock signal is generated as a third clock signal from the second control circuit, and is written in an arbitrary L × N rectangular area of the internal memory in synchronization with the third clock signal by the internal memory address generator. An address generation system characterized in that