JPH06332702A - State register constitution system - Google Patents

Abstract

PURPOSE:To provide a state register constitution system with high information evaluation in which much information can be obtained. CONSTITUTION:This system is equipped with a state register 100 equipped with a storage element which stores and holds set conditions according to the sequence of generation, and outputs them in order of the latest set condition. At the time of inputting a set permission signal 181 showing that one of set condition signals 101-104 is generated, the state register 100 stores and holds the set condition generated at that time. At the time of inputting a control signal for extracting the stored set conditions, the state register 100 outputs the stored and held contents in order of the latest storage content, and restores a state before the outputted set conditions are inputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging a status register for storing a set condition, and more particularly to a method of arranging a status register advantageously applied to a computer system or the like.

[0002]

2. Description of the Related Art FIGS. 2 and 3 show an example of the structure of a status register of a conventional 4-bit structure. In the configuration example of FIG. 2, reference numerals 101 to 104 denote status registers 200.
The set condition signal, reference numerals 211 to 214, are flip-flops that store the set conditions that form the status register 200. Further, reference numeral 121 is a data bus for outputting a set condition, reference numerals 131 to 134 are gates for reading the value (set condition) held by the state register 200 to the data bus 121, and reference numeral 241 is the state register 100.
Is a reset signal for initializing, and reference numeral 151 is a read signal of the status register 100.

After any of the setting conditions 101 to 104 of the status register 200 occurs after initialization by inputting the reset signal 241 by some means, the flip-flops 211 to 214 corresponding to the conditions are set. When the read signal 151 of the status register 200 is input, the content of the status register 200 is changed to the data bus 121.
Is output to. At this time, all the states set up to that point are read out, and if necessary thereafter, the state register 2
00 is set by the reset signal 241.

Next, FIG. 3 shows another example of the configuration of the prior art in the 4-bit configuration status register. In FIG. 3, the set conditions 101 to 104, the data bus 121,
The gates 131 to 134 and the read signal 151 are shown in FIG.
Is the same as.

The prior art of FIG. 3 shows the structure of a status register that stores only the latest set condition.
That is, in this conventional technique, the set timing signal 36
It has four flip-flops 311 to 314 which receive 1 and the set permission signal 381 and store the set conditions input by these signals. The set permission signal 38
1 is output from the OR gate 371 which inputs the set conditions 101 to 104 and takes the logical sum of them.

In FIG. 3, after initialization by inputting the reset signal 241 by some means, the status register 3
When any of the set conditions 101 to 104 of 00 occurs, the set permission signal 381 of the state register 300 is generated and the flip-flops 311 to 314 are settable. Then, when the set timing signal 361 is input, the flip-flops 311 to 311 corresponding to the conditions are input.
“1” is set in 14.

After that, each time a set condition occurs, the state register 300 resets all four bits, and always holds only the state according to the latest set condition. When the read signal 151 of the status register 300 is input, the storage content of the status register 300 is output to the data bus 121. At this time, the last set state is read out,
Then, if necessary, the status register 300 is reset by the reset signal 241.

[0008]

However, in these conventional techniques, the state register 2 is used in the technique shown in FIG.
When reading 00, each flip-flop 2 up to that point
Since all the set conditions stored in 11 to 214 are read out at the same time, there is a disadvantage that the order of occurrence and the occurrence of duplication cannot be known. Further, in the conventional technique shown in FIG. 3, every time a set condition is newly input, the state register 3
Since the flip-flops 311 to 314 of 00 are reset, there is a problem that only the latest set condition can be always known. As described above, the conventional status register has a problem that it is not possible to obtain a lot of information and it is not possible to sufficiently cope with a complicated computer system in recent years.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to provide a state register configuration system having a high information value and capable of obtaining a large amount of information.

[0010]

In order to solve the above-mentioned problems, the present invention has a status register having a storage element for storing and holding set conditions according to the order of occurrence and outputting sequentially from the last stored set condition. . When a set permission signal indicating that one of the set condition signals is generated is input to this status register, the set condition generated at that time is stored and held, and when a control signal for extracting the stored set condition is input, The stored contents are output in order from the latest stored contents, and the state before inputting the output set conditions is returned.

[0011]

According to the present invention, when any of the set condition signals is generated, the contents of the plurality of set condition signals at that time are stored and held in the order of generation. When a read signal to read the stored state stored is input,
The set state last stored and held is output to the data bus. Then, when the reading of the set state output to the data bus is completed, the stored contents of the set state are discarded and the state before storing and holding the set state is restored.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a status register configuration system according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a functional block diagram showing an embodiment in which the status register configuration system according to the present invention is applied to a 4-bit status register. In the present embodiment, the same constituent element as that of the conventional technique, that is, the set condition 10
1 to 104, data bus 121, gates 131 to 134
The same symbols are given to the read signal 151 and the read signal 151, and the duplicated description is omitted here.

In this embodiment, four set condition signals 10
An OR gate 17 that inputs the status register 100 to which 1 to 104 are input and the logical sum of these set condition signals 101 to 104 and outputs a set permission signal 181 to the status register 100
1 and gates 131 to 134 for outputting the set condition stored in the state register 100.

The status register 100 is composed of a storage element having a structure capable of reading the last set data first, for example, a LIFO (Last In First Out). The status register 100 also includes set condition signals 101-10.
4 input terminals DI0 to DI4, and DO0 outputting set conditions to the gates 131 to 134, respectively.
~ DO4, control terminal S for inputting the set permission signal 181
It has an input terminal SETTIM for inputting ETEN and the set timing signal 161.

The status register 100 further includes a control terminal POP for inputting a take-out control signal 191 for returning the storage status (output) of the LIFO to the previous status, and each LIF.
A control terminal RESET for inputting a reset signal 141 for resetting the stored contents of O and an empty display signal output terminal EMPTY for outputting an empty display signal indicating that the stored set condition is not in the register 100 are provided.

The state register 100 has four logically four LIFOs capable of storing a predetermined number of set states in the order of occurrence, and these LIFOs respectively input terminals DI0 to DI4 for inputting a set condition signal and outputs corresponding thereto. Terminal D
It is connected to O0 to DO4.

FIG. 4 shows the concept of each LIFO constituting the status register 100. When each LIFO inputs the set permission signal 181 to the status register 100, the presence or absence of the set condition generated at that time by the set timing signal 161 is input from the input terminals DI0 to DI4, and the set condition 400-1 generated first is the highest. Stored in the back. After that, each time the set permission signal 181 is input, new set conditions are successively picked up.

When the read signal of the status register is output to each of the gates 131 to 134, the most recently stored set condition 400-m + 2 is output to these gates.
When the fetch control signal 191 is input, the most recently input set condition 400-m + 2 is discarded, and when the read signal is output to each of the gates 131 to 134 next, the set condition 400-m + 1 is output to these gates. It

Next, returning to FIG. 1, a series of operations of this embodiment will be described in order. Reset signal 141 by some means
When any of the set conditions 101 to 104 of the status register 100 occurs after the initialization by the input of, the data word (4 bits) is written in the status register 100 with the bit corresponding to the condition set to "1". After that, each time a set condition occurs, a new data word is written to the state register 100, and the states according to the set conditions up to that point are held in the order of occurrence. The bit "0" is stored in the LIFO for which the set condition has not occurred.

Read signal 151 of status register 100
Is input, the last written data of the contents of the status register 100 is read out by the read gates 131 to 1.
It is output to the data bus 121 through 34. The read completion signal generated at the end of data read is the LIF
The O extraction control signal 191 is input to the state register 100, and the state register 100 discards the newest (last written) data currently held and returns to the state in which the previous set condition is held.

In this state, by newly inputting the read signal 151 of the state register 100, it is possible to read the data written immediately before the data read at the previous time. By repeating this until the empty display signal 192 from the status register 100 is detected, the occurrence state of the set condition can be known while tracing back the passage of time.

It should be noted that the embodiments described here are for explaining the present invention, and the present invention is not necessarily limited to this, and those skilled in the art can do it without departing from the spirit of the present invention. Such variations or modifications are included in the scope of the present invention. That is, in the present embodiment, there are logically four LIFOs, but four LIFOs are not necessarily required physically, and the number of LIFOs is not limited to four. Further, as long as it is a storage element having an equivalent function, it is not particularly limited to the LIFO, and the status register 10 may be replaced by another storage element.
It is also possible to configure 0.

[0024]

As described above, according to the present invention, the status register 100 is composed of a plurality of storage elements, and the register to be set can be changed every time a set condition is generated. More information can be obtained from the status register as compared to.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a status register configuration system according to the present invention.

FIG. 2 is a configuration diagram showing a state register configuration method in a conventional technique.

FIG. 3 is a configuration diagram showing a state register configuration method in a conventional technique.

FIG. 4 is a conceptual diagram of a memory element forming a status register in the embodiment shown in FIG.

[Explanation of symbols]

 100 status register 101 to 104 set condition signal 131 to 134 gate 141 reset signal 151 read signal 161 set timing signal 171 OR gate 181 set permission signal 191 extraction control signal 192 empty display signal

Claims (1)

[Claims] 1. In a configuration method of a status register for storing a plurality of set condition signals and outputting the stored set status to a data bus by a read signal, when any one of the set condition signals occurs, a plurality of set condition signals at that time are generated. The content of the set condition signal is stored and held according to the generation order, and when the read signal indicating that the stored and stored set state is read is input, the set state that is finally stored and output is output to the data bus, When the reading of the set state output to the data bus is completed, the stored contents of the set state are discarded and the state before the storage and holding of the set state is returned to.