JPH06339085A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To improve processing speed by providing with each detection means of peak signals on plural photoelectric conversion element groups and detecting various kinds of light. CONSTITUTION:An optical sensor cell Sij is divided into 4 blocks at every adjacent cell, a signal output line is made common within the blocks and the sensor is connected with a horizontal shift registers HSR 1 and HSR 2. By a vertical shift register VSR and the HSR, each block is selected and peak signals are outputted to a terminal out 1 or out 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for an image sensor of a copying machine, a facsimile, a video camera recorder or the like, an AE sensor of a camera, an optical sensor represented by an AF sensor, a sensor for detecting the position of an object, etc. The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device suitable for detecting light such as minute spot light.

[0002]

2. Description of the Background Art FIG. 1 shows an example of a conventional photoelectric conversion device (sensor). In FIG. 1A, there are four sensor cells as photoelectric conversion elements, one for each row and four for each column. 16 two-dimensional sensors arranged side by side are shown.

In this sensor, the vertical shift register VSR
Are sequentially selected row by row from the top in the figure, and the horizontal shift register HSR outputs four individual signals per row to the output terminal out in time series.

In this way, the signal of each cell is sequentially output by the combination of row scanning and column scanning.

In an actual sensor, the number of cells is 10
There are 0 to 100,000 cells, and there is a limit to the reduction of the reading time or scanning time from one cell.

On the other hand, the signal from the cell is often a visible image, but in such an image, a bright signal is present only in a very small area of one frame like the fire of a match in the dark, and the rest is left. May be occupied by all dark signals.

Even in such a case, in the conventional sensor, necessary image signal processing is performed after the signals of all cells are output in time series and stored in the external random access memory.

On the other hand, in the AE sensor (optical sensor for automatic exposure control), the size of each cell is increased, the number of divisions is reduced, and the scanning time is shortened.

FIG. 1B shows such a sensor. Each cell (SS ₁₁ ... S ₂₂ ) has a larger light receiving area than the cell of (a), and the number of divisions is four.

However, in the sensor shown in FIG. 1B, when weak light is uniformly applied to all the light-receiving surfaces of the cell (ma).
It is not possible to distinguish between 1) and the case where strong light is radiated only on a part of the light-receiving surface of the cell (ma2), and it is difficult to apply it to detection of spot light in a small area.

[0011]

As described above, the detection of the light (ma2) in FIG. 1C is either a sensor with a long processing time or a sensor that malfunctions. Was there.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above technical problems and to provide a photoelectric conversion device capable of detecting various kinds of light and improving the processing speed.

The above-mentioned object is to provide a photoelectric conversion device in which a plurality of groups of a plurality of adjacent photoelectric conversion elements are arranged, and each of the plurality of groups comprises means for detecting a peak signal of each group. This is achieved by a photoelectric conversion device characterized by the above.

[0014]

According to the present invention, the sensor array composed of a plurality of cells is divided into a plurality of groups (blocks), and the peak signal in each group is detected, whereby the signals can be processed in real time.

[0015]

FIG. 2 is a circuit diagram showing an embodiment of the present invention. Sij (i = 1, 2, 3, 4, j = 1,
2, 3, 4) indicate optical sensor cells.

Each cell is divided into four blocks for every four adjacent cells, and the signal output lines are shared within the block and connected to the horizontal shift registers (HSR1, HSR2).

Each block is selected by the vertical shift register VSR and the horizontal shift register, and the peak signal is output to the terminal out1 or the terminal out2. Of course, the horizontal shift registers may be combined into one and one output terminal may be provided, or the peak signals of four blocks may be output in parallel from the four output terminals.

The cell used in the present invention may be any cell as long as the signal of the cell having the largest amount of received light is generated on the output line when the output line is shared, and the light is transmitted to the control electrode region such as the base or the gate. Phototransistors that store carriers are preferably used.

The cells may be in the form of line sensors arranged in a one-dimensional array or in the form of area sensors arranged in a two-dimensional array. The size of the light receiving surface of each cell and the number of cells in each block are appropriately selected and designed according to the application of the sensor. Furthermore, it is made into one chip as a semiconductor integrated circuit. The signal output from this sensor chip is subjected to various image signal processing by an external circuit.

(Embodiment 1) Next, a first embodiment of the present invention will be described with reference to FIG. Bij (i, j = 1, 4)
Is a bipolar transistor as an optical sensor cell, P
ij (i = 1, 4) is a P-type MOS switch Mij provided between the base regions of the bipolar transistors.
(I, j = 1, 4) is a MOS switch, and M ₁ j (j
= 1 to 4) is for resetting the sensor output line, M ₂ j
(J = 1 to 4) is a switch for signal transfer from the output line to the capacitor, and M ₃ j (j = 1 to 4) is a signal read capacitor Cj.
(J = 1 to 4) for resetting potential, M ₄ j (j = 1 to 4)
4) are clocks φ ₁ , φ ₂ , φ from the shift register
A switch for selectively outputting each output signal to the output line 1 by ₃ , φ _{4 and} a switch M ₅ for resetting the output line 1. Further, 2 is a shift register and 3 is an output amplifier.

The operation method of this sensor will be described with reference to the timing chart shown in FIG.

First, the N-type MOS switch M ₁ j (j = 1
Up to 4) a high level pulse φ _VR and a high level pulse φ _CR to the N-type MOS switch M ₃ j (j = 1 to 4) to apply the vertical output line VLi (i = 1 to 4) to V _{The VC} voltage and the read capacity Cj (j = 1 to 4) are reset to the _JCR voltage.

Next, the pulse φ _BR of the P-type MOS gate is set to the low level to turn on the P-type MOS, and Pij (ij =
1 to 4) the base potential of the bipolar transistor to V _BR
And In this case, the voltage of V _BR is set higher than V _VC by at least about 1V. After the pulse φ _BR to the P-type MOS gate is set to high level to turn off the P-type MOS,
_{Set the VR} pulse to high level again and set the vertical line level to V
_When it is set to _VC , the bipolar transistor is biased to the forward bias, and the emitter potential converges to the base potential as much as V _VC . As shown in FIG. 3, in this case, the vertical line VL
The ₁ P _11, P _12, the emitter of the P _21, P ₂₂ are commonly connected, thus the four bipolar base is reset by the vertical line VL ₁ potential. The same applies to B ₁₃ , B ₁₄ , B ₂₃ , and B ₂₄ block bipolar transistors, B ₃₁ , B ₃₂ , B ₄₁ , and B ₄₂ block bipolar transistors B ₃₃ , B ₃₄ , B ₄₃ , and B ₄₄ block bipolar transistors. Is similarly executed.

Next, when the pulse of φ _VR is set to low level,
The vertical lines of VL _{1 to} VL ₄ become floating,
The optical signal storage period of each cell (4 in FIG. 4) is entered.

Next, the pulse φ _{T is set} to the high level in order to transfer the signal to the signal read capacitor Cj (j = 1 to 4).
In this case, the potential V _CR for resetting the read capacity is set lower than the vertical line reset potential V _VC . By setting the voltage relationship in this way, when the N-type MOS switch M ₂ j (j = 1 to 4) is turned on by the φ _T pulse, the potential of the vertical line becomes lower than that in the previous period, and the bipolar transistor Bij is again set. (Ij = 1 to 4) is transferred to the forward bias. In this case, the bipolar base-emitter bias of the cell having the highest optical signal level among the cells in each block becomes the highest, and the emitter potential becomes a value corresponding to the peak optical signal in the block.

When the φ _T pulse is set to low level, B ₁₁ ,
The peak signal in the B ₁₂ , B ₂₁ , and B ₂₂ blocks is the capacitance C ₁ ,
The peak signals in the B ₁₃ , B ₁₄ , B ₂₃ , and B ₂₄ blocks are capacitors C ₃ , B ₃₁ , B ₃₂ , B ₄₁ , and the peak signals in the B ₄₂ block are capacitors C ₂ , B ₃₃ , B ₃₄ , and B _43. , B ₄₄ are read to the capacitor C ₄ , respectively.

The scan pulse φ ₁ by the shift register 2,
The signals accumulated in the capacitors from φ ₂ , φ ₃ , and φ ₄ are output from the amplifier 3 via the output line 1.

In all the sensors, the two-dimensional light information is compressed into a peak signal of a desired block area and read out serially. Therefore, it is possible to detect a certain object light on the sensor in a wide area. It is also extremely effective as a means for discriminating an image at high speed.

Specifically, when a user uses a camera, a microscope, or the like, the LED light blinking from the outside hits the user's eye and the reflected light is detected by the sensor of the present invention. The presence / absence of the user can be determined by capturing the reflected light of the LED light at high speed and with high accuracy. It goes without saying that this makes it possible to easily activate the device.

As another application, it is also very useful for detecting the opening / closing of the eyes of a driver of a vehicle.
By the above method, the LED light is externally applied to the driver's eye and the reflected light is received by the sensor of the present invention. If the reflected light is a normal reflection from the cornea, a strong signal is detected, but if the driver becomes sluggish and the eyelid period is shortened, the reflected light intensity decreases. When the sensor output falls below the average strength, the driver beeps.
A sneak prevention device can also be realized by issuing a warning such as chair vibration.

The block peak information is also useful for detecting product labels on the factory line.

Second Embodiment Next, a second embodiment of the present invention will be described with an equivalent circuit diagram shown in FIG. 5 and a timing chart shown in FIG. Further, the same portions as those in the first embodiment are designated by the same symbols or numbers, and the description thereof will be omitted.

The second embodiment is different from the first embodiment in that each sensor cell has a base potential control capacitor Cij (ij).
= 1 to 4) are provided and the reverse bias accumulation operation is performed. With such a configuration, a switch for resetting the read capacity is unnecessary.

The operation will be described below. The pulses of φ _VC and φ _T are set to the high level to reset the vertical lines VL1 to VL4 and the capacitors Ci (i = 1 to 4) to the V _VC potential.

Next, the φ _BR pulse is changed from the intermediate level to the low level, the P-type MOS is turned on, and the base potential is changed to V _BR.
Reset to. After reset, the φ _BR pulse is returned to the intermediate level. In this state, the V _BR level may be selected so that the bipolar is turned off.

Next, the φ _VC pulse is again set to the high level to bring the vertical lines VL1 to VL4 to the V _VC level, and then φ _BR
Change the pulse from intermediate level to high level. This causes the base potential of each bipolar via the capacitance Cij (ij = 1 to 4).

[0037]

[Outer 1] Only rises. At this time, the reset voltages V _VC and V _B12 may be set to the bias amount in which the bipolar current flows in the forward direction.

Similar to the first embodiment, B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂
Since the bipolar emitters of the block are connected to the common VL1 line, a current flows from there and the base potential corresponding to the emitter potential V _VC is reset. The same applies to other bipolar blocks. After the current is converged, the φ _BR pulse is returned to the intermediate level and the reset MOS pulse φ _VC is also set to the low level to start the accumulation. Each cell is separated by P-type MOSPij (ij = 1 to 4). When the φ _BR pulse is set to the high level and the φ _T pulse is set to the high level after the accumulation is completed, the peak signal of each block is read to each of the capacitors C _{1 to} C ₄ . The subsequent reading is the same as in the first embodiment.

(Embodiment 3) A third embodiment will be described with reference to FIG. The same parts are denoted by the same symbols and numerals, and the description is omitted. This embodiment is the vertical line VL of the first embodiment.
1 to VL4 have been improved to have the same symmetry.

The vertical line VL1 is connected to the bipolar B32, B
33, B41, and B42 are also extended as shown at 50 so as to have a symmetrical shape with VL2, and vertical lines VL3 are also extended as shown at 51 on bipolar B33, B34, B43, and B44 blocks. Symmetry with VL4. This makes it possible to align the parasitic capacitance of the vertical line and the read gain of each block, and reduce the variation between blocks.

(Fourth Embodiment) A fourth embodiment will be described with reference to FIG. The fourth embodiment is different from the first to third embodiments in that the outputs of the peak output detection blocks BL1 to BL4 are not read in one direction but are read vertically in parallel, thereby improving the read speed. is there. 61 and 72 are shift registers, 62, 63, 68 and 69 are block B
Readout circuits 64, 65, 66 and 67 for reading out the L1, BL2, BL3 and BL4 signals are vertical output lines of each block, 7
Reference numerals 0 and 71 are horizontal output lines.

(Fifth Embodiment) A fifth embodiment will be described with reference to FIG. In this embodiment, the number of blocks is increased by using two kinds of vertical output lines, for example, the first Al wiring and the second Al wiring. 8 for BL11
One output line, 83 for BL12, 85 for BL21, and 87 for BL22 are used, for example, Al1 wiring, 82 output lines for BL31 block, and BL32 for BL32. 84 output lines, BL4
86 for 1 and 88 for BL42,
Al2 wiring was used. The signal reading circuits 90 to 97 from these output lines are read in parallel to the shift register 98.
Is scanned and output to 99. It goes without saying that the number of divided blocks can be increased by combining the embodiments described above.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to FIG.
It will be described using 0. In the sixth embodiment, in addition to the peak signal of the desired block area of the sensor, normal reading of each bit is also realized at the same time. Reference numeral 100 is a vertical shift register for driving a drive line for reading each bit.
In order to generate the peak signals of the pixels in the two columns from the left and the peak signals of the pixels in the two columns from the right, a MOS switch M ₅ j (j =
1-4) are provided. With the pulse φ _P , the former peak signal is 101 and the latter peak signal is 102. That is, the comparator 10 is used for comparison with the reference level VREF.
3, 104 are input. In this embodiment, the peak signals of each block are simultaneously output without being serially converted, and a determination signal as to whether or not the peak value exceeds a certain desired value is output. It becomes possible to judge quickly.

On the other hand, the data accumulated in each pixel is the first
The signal of each row is output in synchronization with the scanning of the vertical shift register 100 by the device operation described in the embodiment.

As described above, since the peak signal of a desired block and each pixel signal of the screen are simultaneously output, each pixel signal is read out only when rough image information is obtained by the peak signal of the block. Operation is also possible.

(Embodiment 7) Next, a seventh embodiment of the present invention will be described with reference to FIG.

In the case of the sixth embodiment, a certain reference level VRE
Although F and the peak signal are compared, the difference is that the reference level is the dark level of the sensor in the seventh embodiment. The MOS switch of M ₆ j (j = 1 to 4) switches the output before and after the accumulation, and the switch is controlled by the pulses φ _S and φ _N. Before the accumulation, the φ _N pulse is set to the high level, and its output is accumulated in the capacitors C ₆ C ₈ via the MOS switches M ₆₂ and M ₆₄ , respectively. After accumulating the optical signal, the φ _S pulse is set to the high level, and the output is accumulated in the capacitors C ₅ and C ₇ via the MOS switches M ₆₁ and M ₆₃ . Comparing the respective values with the comparators 103, 104
By inputting to, the peak signal of the block with reference to the dark time can be detected.

By using the configuration of this embodiment, it is possible not only to easily determine whether or not light is incident on the sensor, but also the hourly output and the output at the time of light irradiation even if temperature fluctuations occur. Also has the advantage that stable results can be obtained against environmental changes.

(Embodiment 8) Next, an eighth embodiment of the present invention will be described with reference to FIG. In this embodiment, the sensor bipolar B'ij (ij = 1 to 4) is provided with two emitters, one emitter is dedicated to reading each pixel signal, and the other emitter is provided for peak signal detection. We adopted a configuration that connects to the gate of the amplifier.

MOS by M ₇ i (i = 1 to 4) and M ₇₅
An amplifier is configured, and the peak output of each block is M ₇ i
It is input to the gate of (i = 1 to 4). Further, in order to reset the vertical line for peak detection, a reset switch M ₈ j (j = 1 to 4) and a reset pulse φ _{RS EM} was set up. With such a configuration, the addition output of the peak output of each column is output from the amplifier 106. The addition here is not the usual linear addition but the addition of the square root of each output, but there is no particular problem in applications where the peak output itself does not require linearity.

Further, in this embodiment, the peak values of all the columns are added, but it is also possible to easily divide and output the peak values in each block.

In the present embodiment, the spot light is applied to the sensor section at a plurality of points, the peak signal is used to calculate the number of the spot lights, and the positional relationship of each spot light is to use each bit output. It can be realized by the above image processing at high speed.

[0053]

According to the present invention, it is possible to provide a photoelectric conversion device capable of detecting a minute spot light and having a high processing speed.

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining a conventional photoelectric conversion device.

FIG. 2 is a circuit configuration diagram of a photoelectric conversion device according to an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a photoelectric conversion device according to a first embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the photoelectric conversion device according to the first embodiment.

FIG. 5 is a circuit configuration diagram of a photoelectric conversion device according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the photoelectric conversion device according to the second embodiment.

FIG. 7 is a circuit configuration diagram of a photoelectric conversion device according to a third embodiment of the present invention.

FIG. 8 is a circuit configuration diagram of a photoelectric conversion device according to a fourth embodiment of the present invention.

FIG. 9 is a circuit configuration diagram of a photoelectric conversion device according to a fifth embodiment of the present invention.

FIG. 10 is a circuit configuration diagram of a photoelectric conversion device according to a sixth embodiment of the present invention.

FIG. 11 is a circuit configuration diagram of a photoelectric conversion device according to a seventh embodiment of the present invention.

FIG. 12 is a circuit configuration diagram of a photoelectric conversion device according to an eighth embodiment of the present invention.

Claims (5)

[Claims] 1. A photoelectric conversion device in which a plurality of groups of a plurality of adjacent photoelectric conversion elements are arranged, each of the plurality of groups includes means for detecting a peak signal of each group. And a photoelectric conversion device. 2. The photoelectric conversion device according to claim 1, wherein each of the plurality of photoelectric conversion elements is provided with means for outputting a signal of each photoelectric conversion element. 3. An image processing device comprising the photoelectric conversion device according to claim 2 and a circuit for processing an output signal from the photoelectric conversion device. 4. The image processing device according to claim 3, wherein the photoelectric conversion device is a single semiconductor integrated circuit. 5. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion element is a bipolar transistor that stores photocarriers in a base.