JPH06339120A - Video signal processing circuit for vtr - Google Patents

Abstract

PURPOSE:To obtain continuously a horizontal synchronizing signal with a correct phase at special reproduction of a VTR. CONSTITUTION:This processing circuit is provided with a VCO 6 oscillated at a frequency being a multiple of (n) ((n) is an integer) of a horizontal synchronizing signal frequency, a variable frequency divider circuit 19 frequency-dividing an oscillated output signal from the VCO 6 as two frequency division ratios, a phase comparator circuit 23 comparing the phase of a horizontal synchronizing signal in the reproduction video signal of the VTR and a frequency division output signal from the variable frequency divider circuit 19, a switch 7 connected between the VCO 6 and the variable frequency divider circuit 19 and switched in response to the output signal of the phase comparator circuit 23 and a dropout detection circuit 17 detecting omission of the reproduced video signal of the VTR.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VTR video signal processing circuit for continuously generating a horizontal synchronizing signal from a VTR reproduced video signal.

[0002]

2. Description of the Related Art In a VTR reproducing circuit, a horizontal synchronizing signal is separated from a reproducing luminance signal, and the horizontal synchronizing signal is converted into a phase shift circuit at the time of reproducing a color signal or an NTSC video signal is converted into a P signal.
Converted to AL format video signal (NT with PAL format VTR
Plays back SC signals. ) Is used as a trigger signal. At that time, since the simply separated horizontal synchronizing signal is not stable against loss or the like, the PLL circuit is locked to the horizontal synchronizing signal and the output signal of the PLL circuit is used as the horizontal synchronizing signal.

FIG. 2 is a block diagram showing such a PLL circuit. The reproduced luminance signal from the terminal (1) is separated into a composite sync signal by a sync separation circuit (2). The equalized pulse removing circuit (3) removes unnecessary components such as the equalized pulse from the separated composite synchronizing signal, and the continuous signal of the horizontal synchronizing signal frequency (f _H = 15.734 KHz) is waveform-shaped. Applied to the circuit (4). The waveform shaping circuit (4) performs waveform shaping so that the pulse width of the input signal becomes constant. As a result, a horizontal synchronizing signal having a constant pulse width is applied to the AND gate (5) which operates as a phase comparator. On the other hand, VC oscillating at a frequency of 320 f _H
The oscillation output signal of O (6) is divided by the dividing circuit (8) by 1/300 via the switch (7), and the divided signal is applied to the AND gate (5). In addition, the frequency dividing circuit (8)
Automatically returns to the initial value after counting up.

Now, the output signal of the waveform shaping circuit (4) is shown in FIG.
(A), the output signal of the frequency dividing circuit (8) is shown in FIG.
It is assumed that the phases of both signals are the same. Then Ande
The signal of FIG. 3C is generated at the output end of the gate (5),
The switch (7) is opened during the "H" level of the signal. Do
And a clock signal from the VCO (6) to the frequency dividing circuit (8)
Supply is stopped, the frequency divider circuit (8) keeps (20)
(Clock period) stop the operation. Thus the frequency divider circuit
(8) has a count operation stop time, and changes the time.
Lock the phase of the horizontal sync signal by
It For example, in the initial state, the output of the frequency dividing circuit (8)
The signal is in the state as shown in FIG. ₁smell
And it was going forward 30 minutes from the locked state.
To do. Then, the frequency dividing circuit (8) is 30 clocks from the initial value.
After counting, the AND gate (5) output in Fig. 3 (e)
The count is stopped due to₂From cow again
Restarted at time t₃Count 300 clocks
To return to the initial value. Therefore, the operation of the frequency divider circuit (8) is stopped
The period becomes 20 clocks longer than when locked, and
Time t of signal (d)₃Later phase advance amount is 10 clock
Lowers. Then, the frequency dividing circuit (8) next outputs 290
The clock returns to the initial value, and the amount of phase advance becomes smaller.
It Then, the phase will be locked during the next phase comparison.
It

Therefore, the output signal phase of the frequency dividing circuit (8) is locked to the horizontal synchronizing signal phase, and a horizontal synchronizing signal having a desired pulse width is obtained from the terminal (9).

[0006]

In the circuit of FIG. 2,
When the horizontal synchronizing signal applied to the AND gate (5) from the waveform shaping circuit (4) is missing, the output signal of the AND gate (5) is not generated and the switch (7) remains closed.
This is not a problem if the signal is lost only about several times, but there is a problem that the picture quality of the reproduced video signal deteriorates for a long time such as a noise bar period during VTR search reproduction. . If the switch (7) remains closed, the output signal phase of the frequency dividing circuit (8) will shift by 20 clocks every horizontal period. In this state, there occurs a problem that the switching timing of the phase rotation of the phase shift circuit is deviated and the reproduced color signal cannot be correctly restored.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a VCO that oscillates at a frequency n times the horizontal synchronizing signal frequency (n is an integer) and an oscillation output signal of the VCO. A variable frequency divider circuit that divides by two frequency division ratios, and VT
A phase comparison circuit for performing phase comparison between the horizontal synchronizing signal in the reproduced video signal of R and the frequency division output signal of the variable frequency division circuit;
A switch connected between the VCO and the variable frequency divider circuit to open and close according to an output signal of the phase comparator circuit;
A dropout detection circuit for detecting that the reproduced video signal of TR is missing, and switching the frequency division ratio of the variable frequency division circuit according to the detection output signal of the dropout detection circuit. And

[0008]

According to the present invention, when the dropout of the video signal is detected, the frequency division number of the variable frequency dividing circuit is switched according to the detected output signal to change the signal of the original horizontal synchronizing signal frequency to the variable frequency dividing signal. It is generated from the circuit.

[0009]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(10) is a reproducing head for a VTR video signal, (11) is a luminance signal processing circuit for processing the luminance signal extracted by the HPF (12) such as demodulation, and (13) is a color extracted by the LPF (14). A main converter that converts the signal to the original frequency (3.58 MHz for the NTSC system),
(15) mixes the demodulated luminance signal and chrominance signal,
A mixing circuit for generating a video signal at the terminal (16), (17)
Is a dropout detection circuit that detects that the video signal from the reproducing head (10) is missing, (18) is an integration circuit that integrates the output signal of the dropout detection circuit (17), and (19) is 1 / 300 frequency divider (20), 1/32
A variable frequency divider circuit (23) having a 0 frequency divider (21) and a switch (22) receives a horizontal synchronizing signal from the waveform shaping circuit (4) and a frequency division output signal of the variable frequency divider circuit (19). The AND gate forcibly closing the switch (7) in accordance with the output signal of the integrating circuit (18) while performing the phase comparison of (1).

In FIG. 1, the same circuit elements as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, a luminance signal is extracted by a HPF (12) from a video signal from a reproducing head (10) during reproduction of a VTR, and the luminance signal is processed by a luminance signal processing circuit (11) to a sync separation circuit (2). Is applied.

On the other hand, the color signal having a frequency of about 629 KHz extracted by the LPF (14) is supplied to the main converter (13).
The frequency is converted to 3.58 MHz. Oscillator (2
4) is a reference of the color signal phase at the time of reproduction, and NT
If it is the SC system, it oscillates at a frequency of about 3.58 MHz,
The APC (automatic phase control) circuit (25) compares the phase with the reproduced burst signal. Then, the APC circuit (2
The phase comparison error voltage generated from 5) is VCO (6)
Control the oscillation frequency of. The signal of the frequency 320f _H which is the oscillation output signal of the VCO (6) is transferred to the phase shift circuit
In 6), the frequency is divided into ⅛, and at the same time, the phase is changed by 90 degrees for each 1H (H is one horizontal synchronizing signal period) for phase restoration. As a result, the frequency 40f _H (about 62
The signal of 9 KHz) is applied to the sub-converter (27), multiplied by the signal of frequency 3.58 MHz from the oscillator (24), and the signal of the sum frequency of about 4.21 MHz is applied to the main converter (13). Therefore, from the main converter (13), the frequency converted 3.58MH
The z color signal is generated, mixed with the luminance signal in the mixing circuit (15), and the reproduced video signal is generated at the terminal (16).

In FIG. 1, when the reproduced video signal is not lost, the output of the dropout detection circuit (17) is "L".
The level is maintained and the output of the integrating circuit (18) is also maintained at "L". Then, the switch (2
2) is switched as shown. In addition, the integration circuit (1
8) is in a state where it does not affect the phase comparison operation of the AND gate (23).

Therefore, in this state, the circuit of FIG. 1 operates as shown in the waveform diagram of FIG. Next, the case where the reproduced video signal is continuously missing will be described with reference to FIG. As an output signal of the equalization pulse removal circuit (3), FIG.
As shown in (a), if a signal is missing from the second shot, the waveform shaping circuit (4) outputs the signal shown in FIG. 4 (b). In response to noise generated at the times t ₁₀ and t ₁₁ of the signal of FIG.
, An erroneous sync signal is generated. Figure 4 (c)
Shows the output signal of the variable frequency dividing circuit (19), which is locked to the signal of FIG. 4 (b). FIG. 4D shows the output signal of the AND gate (23), and the switch (7) is opened by the output of "H" level. Figure 4 (e)
Shows the output signal of the dropout detection circuit (17), and detects the dropout that causes the loss of the horizontal synchronization signal of FIG. 4A at time t ₁₂ . Then, Fig. 4
The signal of (e) is an integrating circuit (18) with a short charging time constant.
Are integrated by the above, and the result is as shown in FIG. Then, Fig. 4
The switch (22) is switched in accordance with the signal of (f) and the output signal of the VCO (6) is divided by 1/320 by the 1/320 frequency divider circuit (21), and the frequency is f _H. Becomes On the other hand, in response to the signal of FIG. 4 (f), the output of the AND gate (23) becomes the “L” level regardless of the phase comparison result, and the switch (7) is closed. Therefore, Fig. 4 (a)
The AND gate (23) does not output the phase comparison result by the pulse caused by the noise generated at time t ₁₁ . When the horizontal synchronizing signal is continuously lost, noise is often mixed. Therefore, the switch (7) is closed so that the variable frequency dividing circuit (19) can stably generate the signal of the frequency f _H.

Therefore, according to the circuit of FIG. 1, even if the reproduced video signal is dropped out, a signal of frequency f _H as shown in FIG. 4 (g) can be obtained, and the signal can be obtained from the terminal (9). It can be applied to the phase shift circuit (26). The signal of FIG. 4 (g) has a phase 20 clocks earlier than that of the signal of FIG. 4 (c), and the 1/300 frequency divider circuit (20) and 1/32
It can be easily obtained from any of the divide-by-zero circuits (21).

[0015]

As described above, according to the present invention, V
Even if dropout occurs during TR reproduction, it is possible to continuously generate horizontal sync signals with the correct phase.
A video signal processing circuit for TR can be provided. Therefore, VTR
It is possible to reduce the deterioration of image quality even when the search reproduction of is performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a video signal processing circuit of a VTR of the present invention.

FIG. 2 is a block diagram showing a video signal processing circuit of a conventional VTR.

FIG. 3 is a waveform diagram for use in explaining FIG.

FIG. 4 is a waveform diagram for use in explaining FIG.

[Explanation of symbols]

 (6) VCO (7) Switch (17) Dropout detection circuit (19) Variable frequency divider circuit (23) AND gate

Claims (3)

[Claims] 1. A horizontal synchronization signal frequency n times (n is an integer)
VCO that oscillates at the frequency, a variable frequency divider circuit that divides the oscillation output signal of the VCO by two frequency division ratios, a horizontal synchronizing signal in the reproduced video signal of the VTR, and a frequency division output of the variable frequency divider circuit. A phase comparison circuit for performing phase comparison with a signal, a switch connected between the VCO and the variable frequency divider circuit to open / close according to an output signal of the phase comparison circuit, and a reproduced video signal of the VTR are missing. And a dropout detection circuit for detecting the presence of the variable frequency division circuit according to the detection output signal of the dropout detection circuit. 2. A video signal processing circuit for a VTR according to claim 1, further comprising means for forcibly switching the switch in accordance with a detection output signal of the dropout detection circuit. 3. An integration circuit for integrating the detection output signal of the dropout detection circuit, wherein the frequency division ratio of the variable frequency division circuit is switched according to the output signal of the integration circuit. The video signal processing circuit of the described VTR.