JPH06342595A - Decoder and semiconductor memory - Google Patents

Abstract

(57) [Summary] [Objective] In an SRAM composed of one address decoder and a plurality of banks, by inputting a bank selection signal to the address decoder, the read operation of the banks other than the selected bank is stopped and low power consumption is achieved. Make a change. [Structure] An address decoding circuit 3 for inputting an address signal 1 and selecting one word from a plurality of words.
And bank selection signals 18 and 30 connected in parallel for the number of banks to the respective outputs of the address decoding circuit 3 to select one bank from the plurality of banks 20 and 32. , 47, and selects the word selected by the address decode circuit 3 only in the bank selected by the bank selection circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address decoder and a semiconductor memory device, and more particularly to an address decoder applied to a semiconductor memory having a bank structure and a semiconductor memory device having a bank structure.

[0002]

2. Description of the Related Art In order to speed up access in a semiconductor memory such as a static random access memory or a cache memory, there is a method for realizing a high speed operation by adopting a bank structure in an address range etc. and reducing a load capacity of bit lines. Commonly used.

The conventional static random access memory described above (hereinafter referred to as SRAM) will be described with reference to the drawings.
An example will be described. FIG. 3 shows a conventional SRA having a two-bank configuration including a bank A20 and a bank B32.
3 shows a configuration of M. Reference numeral 1 is a 4-bit width address signal line, and 2 is an address decoder activation signal. Reference numeral 3 denotes an address decoder circuit for one row, which includes transistors 37 to 41. The address decoder activation signal 2 is connected to the gate of the transistor 37, and the source is grounded. Also, the transistor 3
The address signal line 1 is connected to the gates of 8 to 41. The address decode circuit 3 is shared by the banks A and B. Reference numeral 4 is an output signal line of the address decode circuit 3, and 5 is an address decode precharge circuit for holding the address decode circuit output signal line 4 at a high level. 6 and 21 are address decoding circuit output signal lines 4
Is a word line drive circuit, and 7 and 22 are word lines which are output lines of the word line drive circuits 6 and 21.
Reference numerals 8, 9, 23 and 24 are bit lines, and 10 and 25 are bit line precharge circuits that hold the bit lines 8, 9, 23 and 24 at a high level when the address decode circuit 3 is not in the activated state. . Reference numerals 11 and 26 are memory cells.
Reference numeral 33 shows the structure of bank A and bank B for one word. Reference numeral 12 is an address decoder output signal detection circuit for detecting the address decode circuit output signal line 4, and 13 is an output line of the address decode output signal detection circuit 12, which is an address decode output detection signal line. An address decode output detection signal line precharge circuit 14 holds the address decode output detection signal line 13 at a high level when the address decode circuit 3 is not in the activated state. Reference numeral 15 is a sense amplifier control circuit having the address decode output detection signal line 13 as an input, 16 and 27 are sense amplifier activation signals having the sense amplifier control circuit 15 as an output, and 17 and 28 are sense amplifiers. Reference numeral 18 is a bank selection signal for selecting the bank A20, and 19 is an I / O circuit operated by the bank selection signal A18. 31
Is an I / O circuit operated by the bank selection signal B30. Reference numerals 35 and 36 are input / output of the I / O circuit, and 34 is read data.

The read operation of the SRAM configured as described above will be described below. Before the address signal line 1 is input, the address decoder activation signal 2 is set to low level, and the address decode precharge circuit 5 precharges the address decode circuit output signal line 4 to high level. Similarly, the address decode output detection signal line precharge circuit 14 causes the address decode output detection signal line 13 to move to the bit line precharge circuits 10 and 25, and the bit lines 8, 9, 23, 2, 2.
Precharge 4 to a high level. Then, the address signal line 1 is input and the address decoder activation signal 2 is set to a high level, and the read operation is simultaneously started in the banks A20 and B32. First, the address decode circuit 3 sets the address decode circuit output signal line 4 of the selected word to the low level. Then, the word lines 7 and 22 become high level via the word line drive circuits 6 and 21, and the information stored in the memory cells 11 and 26 is transmitted to the bit lines 8, 9, 23 and 24. On the other hand, the decode circuit output signal line is input to the address decoder circuit output signal detection circuit 12, and the address decode output detection signal line 13 becomes low level. Further, the sense amplifier control circuit 15 sets the sense amplifier activation signal lines 16 and 27 to a high level, and the data on the bit lines 8, 9, 24 and 23 is transferred to the I / O circuits 19 and 31 via the sense amplifiers 17 and 28. Entered in. Then, for example, when the bank A20 is selected, the bank selection signal A18 is at the high level and the bank selection signal B30 is at the low level, and the data of the bank A is read out through the I / O circuit 19 and the read data 34. Is output to. Further, when the bank B32 is selected, the bank selection signal A18 is at a low level and the bank selection signal B30 is at a high level, and the data of the bank B32 becomes the read data 34 via the I / O circuit 36. Is output.

[0005]

However, in the configuration as in the above-mentioned conventional example, one word is selected in all banks, the data stored in the memory cell is read to the bit line, and the sense amplifier operates. Therefore, there is a problem that the power consumption increases. Further, since the increase in power consumption becomes more remarkable as the number of banks is increased, it has been a major obstacle in increasing the speed and increasing the capacity by increasing the number of banks.

Therefore, in view of the above problems, the present invention has a structure having a plurality of banks in one address decoder, and stops the read operation of the banks other than those necessary, which enables low power consumption and high speed operation. A static random access memory and a cache memory are provided.

[0007]

In order to solve the above problems, an address decoder according to the present invention includes an address decoding circuit which inputs an address signal and selects one word from a plurality of words, and the address decoding circuit. A bank selection circuit connected to the output of the circuit and selecting one bank from a plurality of banks by inputting a bank selection signal.

[0008]

The semiconductor memory device of the present invention has a structure including the above-mentioned decoder and a plurality of banks, so that the read operation of the banks other than the necessary ones is stopped, and low power consumption and high speed operation are possible.

[0009]

【Example】

(Embodiment 1) An SRAM according to an embodiment of the present invention will be described below.
A description will be given with reference to the drawings.

FIG. 1 shows the SR in the first embodiment of the present invention.
It is a block diagram of AM. Reference numeral 1 is a 4-bit width address signal line, and 2 is an address decoder activation signal. 3 is an address decoding circuit for one row, which is a transistor 37
~ 41. The address decoder activation signal 2 is connected to the gate of the transistor 37, and the source is grounded. Also, the transistors 38-41
An address signal line 1 is connected to the gate of the. Reference numeral 4 is an output signal line of the address decoding circuit 3. Reference numeral 18 is a bank selection signal A indicating that data is read or written in the bank A20, 30 is a bank selection signal B indicating that data is read or written in the bank B32, and 46 is indicated. The bank selection circuit is composed of a transistor A having a drain connected to the output signal line 4 and having a bank selection signal A18 at its gate. Four
Reference numeral 7 denotes a bank selection circuit including a transistor B having a drain connected to the output signal line 4 and having a bank selection signal B30 at its gate. A bank A word selection signal 44 is connected to the source (or drain) of the transistor 46. Reference numeral 45 is a bank B word selection signal line, which is connected to the source (or drain) of the transistor 47. Reference numerals 5 and 39 are address decode precharge circuits for holding the bank A word selection signal line 44 and the bank B word selection signal line 45 at a high level.
Reference numerals 6 and 21 are word line drive circuits to which the address decode circuit output signal line 4 is input. Reference numerals 7 and 22 are word lines that are output lines of the word line drive circuits 6 and 21. 8, 9,
23 and 24 are bit lines. 10 and 25 are bit lines 8, 9 and 2 when the address decoder 3 is not activated.
This is a bit line precharge circuit that holds 3, 24 at a high level. Reference numerals 11 and 26 are memory cells. Reference numeral 33 shows the structure of bank A and bank B for one word.
12, 40 are bank A word selection signal line 44, bank B
An address decode output signal detection circuit for detecting the word selection signal line 45. Output lines 13 and 41 of the address decode output signal detection circuits 12 and 40 are address decode output detection signal lines. Reference numerals 14 and 42 are address decode output detection signal line precharge circuits for holding the address decode output detection signal lines 13 and 41 at a high level when the address decode 3 is not in the activated state. 15,
Reference numeral 43 is a sense amplifier control circuit to which the address decode output detection signal lines 13 and 41 are input. Numerals 16 and 27 are sense amplifier activation signals that output the sense amplifier control circuits 15 and 43, and numerals 17 and 28 are sense amplifiers. 19 is an I / O operated by a bank selection signal A20
Circuit. Reference numeral 31 is an I / O circuit operated by the bank selection signal B30. Reference numerals 35 and 36 are outputs of the I / O circuit, and 34 is read data.

The read operation of the SRAM configured as described above will be described below. First,
Before the address signal line 1, the bank selection signal A18, and the bank selection signal B30 are input, the address decoder activation signal 2 is set to a low level, and the address decode precharge circuits 5 and 39 cause the bank A word selection signal line 44,
The bank B word selection signal line 45 is precharged to a high level. Similarly, the address decode output detection signal line precharge circuits 14 and 42 raise the address decode output detection signal lines 13 and 41, and the bit line precharge circuits 10 and 25 raise the bit lines 8, 9, 23, and 24. Precharge to a level. And the address signal line 1
And the address decode activation signal 2 is set to a high level. Then, the address decode circuit output signal 4 of the word selected by the address decode circuit 3 becomes low level and is transmitted to the transistors 46 and 47.
Here, when reading data from the bank A20,
Bank selection signal A18 is high level, bank selection signal B3
0 is at a low level, and the address decode circuit output signal 4 is transmitted only to the bank A word selection signal line 44. Therefore, the bank A word selection signal line 44 becomes low level, and the bank B word selection signal line 45 holds high level. When reading data from the bank B, similarly, the bank A word selection signal line 44 holds the high level,
The bank B word selection signal line 45 becomes low level.

The operation when the bank A20 is selected will be described below. Since the bank A word selection signal line 44 is at the low level, the word line drive circuit 6
Via, the word line 7 of bank A20 goes high,
The data stored in the memory cell 11 is output to the bit lines 8 and 9. On the other hand, the bank A word selection signal line 44 is input to the address decode circuit output detection circuit 12 to set the address decode output detection signal line 13 to a low level. Then, the sense amplifier control circuit 15 sets the sense amplifier activation signal line 16 to a high level, and the data on the bit lines 8 and 9 is input to the I / O circuit 19 via the sense amplifier 17. Then, the I / O circuit 19 outputs the read data 34 by the bank selection signal A18. On the other hand, since the bank B word selection signal line 45 is still at the high level, the word line 22 of the bank B 32 is at the low level and no data is read from the memory cell 36. Further, since the bank B word selection signal line 45 remains at the high level, the address decode output detection signal line 41 holds the high level and the sense amplifier activation signal line 27 becomes the low level, so that the sense amplifier 28 operates. do not do.

As described above, according to this embodiment, the bank A
A transistor 46 having a selection signal 18 at its gate, a transistor 47 having a bank B selection signal 30 at its gate, and an address decoding circuit 3 and a bank A word selection signal line 4 are provided.
4. By providing between the bank B word selection signal line 45, the read operation from the memory cell to the bit line can be generated only in the selected bank, and only the sense amplifier of the selected bank can be operated. It is possible to significantly reduce the power consumption.

In this embodiment, the case of the two-bank configuration has been described, but in the case of the two-bank configuration or more, only one selected bank performs the read operation and it is not selected. Since the read operation does not occur in the remaining banks, the effect of reducing power consumption further increases as the number of banks increases.

(Second Embodiment) A cache memory according to a second embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram of a cache memory of the 2-way set associative system in the second embodiment of the present invention. In FIG. 2, 201 indicates the configuration of set 0, and 202 indicates the configuration of set 1. Reference numerals 203 and 205 are tag portions for storing tag addresses, and reference numerals 204 and 206 are data portions for storing data. Here, the tag units 203 and 20
5 and the data sections 204 and 206 are composed of the 2-bank SRAM shown in FIG. 2 is a tag section 203, 2
05 and the data decoder 204, 206 are address decoder activation signals. Reference numeral 207 is an address for accessing the cache memory.
7 is further divided into three, a bank selection address 208, a word selection address 1, and a tag comparison address 209.
Reference numeral 217 is a bank selection signal generation circuit which receives the bank selection address 208, 18 is a bank A selection signal for selecting the bank A shown in FIG. 1 from the two banks in the tag units 203 and 205 and the data units 204 and 206, 30 Is bank B
Is a bank B selection signal for selecting. And 210,
Reference numeral 212 is a tag address read from the tag units 203 and 205, and 211 and 213 are data read from the data units 204 and 206. Further, 214 and 218 are comparators 215 and 2 for comparing the tag addresses 210 and 212 read from the tags with the tag comparison address 209.
Reference numeral 19 is a coincidence detection signal which becomes high level when the comparators 214 and 218 detect coincidence. An output circuit 216 outputs the data 211 read from the data section to the output data line when the match detection signal 215 is at a high level, and 220 is read from the data section when the match detection signal 219 is at a high level. An output circuit 222 for outputting the generated data 213 to the output data line is a cache memory output data line.

The operation of the cache memory having the above structure will be described below. First, the tag section 20
3, 205 and the data section 204, 206 have the address 20
Before 7 is input, the address decoder activation signal 2 is set to low level, and the address decoder precharge circuit 5,
39, bank A word selection signal line 44, bank B
The word selection signal line 45 is precharged to a high level.
Similarly, the address decode output detection signal line precharge circuits 14, 42 connect the address decode output detection signal lines 13, 41 to the bit line precharge circuit 10,
25 precharges the bit lines 8, 9, 23, 24 to a high level. When the address signal line 1 is input, the address decoder activation signal 2 is set to high level. Then, the address decode circuit output signal 4 of the word selected by the address decode circuit 3 becomes low level and is transmitted to the transistors 46 and 47. here,
When reading data from the bank A20, the bank selection signal A18 is at a high level and the bank selection signal B30 is at a low level, and the address decode circuit output signal 4 is transmitted only to the bank A word selection signal line 44. Therefore, the bank A word selection signal line 44 becomes low level,
The bank B word selection signal line 45 holds the high level.
When the data is read from the bank B, the bank A word selection signal line 44 similarly holds the high level, and the bank B word selection signal line 44 holds the high level.
The word selection signal line 45 becomes low level. The operation will be described below when the bank A20 is selected. Since the bank A word selection signal line 44 is at the low level, the word line 7 of the bank A 20 goes to the high level via the word line drive circuit 6, and the data stored in the memory cell 11 is the bit line 8 , 9 are output. On the other hand, the bank A word selection signal line 44 is input to the address decode circuit output detection circuit 12 to set the address decode output detection signal line 13 to a low level. Then, the sense amplifier control circuit 15 causes the sense amplifier activation signal line 16
Becomes high level, and the data of the bit lines 8 and 9 is input to the I / O circuit 19 via the sense amplifier 17. Then, the I / O circuit 19 outputs the read data 34 by the bank selection signal A18. On the other hand, since the bank B word selection signal line 45 remains at the high level, the word line 22 of the bank B32 becomes the low level and the memory cell 3
No data reading from 6 will occur. Further, since the bank B word selection signal line 45 remains at the high level,
The address decode output detection signal line 41 holds the high level and the sense amplifier activation signal line 27 becomes the low level, so that the sense amplifier 28 does not operate. Here, the data section 2
04, 206, the read data 34 of the tag units 203, 205 are the data 211, 213, the tag address 210,
212. Then, the data 211 and 213 are input to the output circuits 216 and 220, respectively. The read tag addresses 211 and 213 are tag addresses 21
0 and 212 are compared with the comparators 214 and 218. For example, if the tag addresses 211 and 210 match and the tag addresses 213 and 212 do not match, the comparator 214 outputs a high-level match detection signal to the match detection signal 215, which is input to the output circuit 216. The data 211 is output by the output circuit 216 to the cache memory output data line 2
22 is output. On the other hand, the data 213 is output to the output circuit 2
Since the match detection signal is not input to 20, the output is not output to the cache memory output data line 222. If the tag addresses 211 and 210 do not match and the tag addresses 213 and 212 match, the comparator 218 outputs a high-level match detection signal to the match detection signal 219 and the output circuit 220. The data 213 is output to the cache memory output data line 222 by the output circuit 220. On the other hand, the data 211 is not output to the cache memory output data line 222 because the match detection signal is not input to the output circuit 216.

As described above, according to this embodiment, the bank A
A transistor 46 having a selection signal 18 at its gate, a transistor 47 having a bank B selection signal 30 at its gate, and an address decoding circuit 3 and a bank A word selection signal line 4 are provided.
4. By providing between the bank B word selection signal line 45, the read operation from the memory cell to the bit line can be generated only in the selected bank, and only the sense amplifier of the selected bank can be operated. It is possible to significantly reduce the power consumption.

In the present embodiment, the case of the two-bank configuration has been described, but even in the case of the bank configuration having two or more tag sections and data sections, the read operation is performed only for the selected bank. Therefore, since the read operation does not occur in the remaining unselected banks, the effect of reducing the power consumption further increases as the number of banks increases.

In the present embodiment, the case of 2-way set associative type cache has been described, but a direct map type or set associative type cash of 2 or more ways can be easily realized with the same configuration.

Although the decoder of the present invention is applied to the SRAM and the cache memory in each of the first and second embodiments, it goes without saying that it can be applied to a semiconductor memory device such as a DRAM.

[0021]

As described above, the present invention is connected to the address decode circuit for inputting an address signal and selecting one word from a plurality of words and the output of the address decode circuit for inputting a bank select signal. A bank selecting circuit for selecting one bank from a plurality of banks, and selecting a word selected by the address decoding circuit only in the bank selected by the bank selecting circuit. By providing a decoder and a plurality of banks, it is possible to stop the read operation of the banks other than the necessary banks and to operate at high speed with low power consumption.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an SRAM according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a cache memory according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional SRAM

[Explanation of symbols]

1 Address signal line 2 Address decoder activation signal 3 Address decode circuit 4 Output signal line 5, 39 Address decode precharge circuit 6, 21 Word line drive circuit 7, 22 Word line 8, 9, 23, 24 Bit line 10, 25 Bit line precharge circuit 11,26 Memory cell 12,40 Address decode output signal detection circuit 13,41 Address decode output detection signal line 14,42 Address decode output detection signal line precharge circuit 15,43 Sense amplifier control circuit 16,27 Sense amplifier activation signal 17,28 Sense amplifier 18,30 Bank selection signal 19,31 I / O circuit 20,32 Bank 33 Configuration of 1 word of bank A and bank B 34 Read data 35, 36 I / O Circuit output 37-41, 46, 47 transitions Data 44 and 45 word selection signal line

Claims (5)

[Claims] 1. An address decoding circuit for inputting an address signal and selecting one word from a plurality of words,
A decoder comprising: a bank selection circuit which is connected to the output of the address decoding circuit and which selects one bank from a plurality of banks by inputting a bank selection signal. 2. The address decode circuit and the bank selection circuit are dynamic circuits, and the circuit for precharging the selection result signal of the address decode circuit and the circuit for precharging the selection result signal of the bank selection circuit are common. The decoder according to claim 1, wherein the decoder is embodied. 3. The address decoding circuit comprises: a first transistor whose gate receives an address activation signal and whose source is grounded; and a gate which receives an address signal and whose source receives the drain of the first transistor. A second transistor connected to the bank selection circuit, wherein the bank selection circuit includes a third transistor having a gate to which a bank selection signal is input and a source (or drain) connected to the drain of the second transistor. The decoder according to claim 1, wherein the decoder is provided. 4. A word drive circuit in which each bank receives an output of each of the decoders according to claim 1, a plurality of memory cells connected to a word line which is an output of the word drive circuit, and A bit line connected to the memory cell for inputting / outputting data stored in the memory cell, a precharge circuit for precharging the bit line to a high level, and a signal connected to the bit line for amplifying a signal on the bit line. A sense amplifier, a sense amplifier control circuit that activates the sense amplifier when at least one of the outputs of the decoder becomes high level, and a bank select signal that is connected to the sense amplifier and outputs the input / output signal of the sense amplifier. And a data input / output circuit that determines data input / output according to the semiconductor memory device. 5. A tag memory for storing a tag address, a data memory for storing data corresponding to the tag address, and a comparator for comparing the tag address read from the tag memory with a part of the address. 5. A tag memory or a data memory comprising the semiconductor memory device according to claim 4, further comprising an output circuit for outputting the data read from the data memory when a match is detected by the comparator. A characteristic semiconductor memory device.