JPH06349983A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06349983A
JPH06349983A JP5141048A JP14104893A JPH06349983A JP H06349983 A JPH06349983 A JP H06349983A JP 5141048 A JP5141048 A JP 5141048A JP 14104893 A JP14104893 A JP 14104893A JP H06349983 A JPH06349983 A JP H06349983A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
heat dissipation
semiconductor
dicing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5141048A
Other languages
Japanese (ja)
Inventor
Kenichi Takebe
堅一 建部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP5141048A priority Critical patent/JPH06349983A/en
Publication of JPH06349983A publication Critical patent/JPH06349983A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To incorporate a heat dissipating member in a package even when a resin material is used for the package. CONSTITUTION:A semiconductor device uses a resin material as a package material, and the method for manufacturing the device comprises the steps of adhering a heat dissipating plate 10 through an adhesive material 9 to a rear surface of one semiconductor wafer 8 on which an integrated circuit is formed and before dicing is conducted, and packaging a semiconductor chip obtained by dicing it.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はICなどの半導体装置の
製造技術、特に、プラスチックなどの樹脂材を用いたパ
ッケージの内部に放熱板を配設した構造の半導体装置に
用いて効果のある技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is effective in manufacturing a semiconductor device such as an IC, and more particularly in a semiconductor device having a structure in which a heat dissipation plate is arranged inside a package made of a resin material such as plastic. It is about.

【0002】[0002]

【従来の技術】例えば、DIP(デュアル・インライン
・パッケージ)型の半導体装置では、リードフレームと
半導体チップのバンプ電極とをワイヤボンディングした
のち、半導体チップ及びその周辺部を樹脂材でモールド
してパッケージングを行っている。
2. Description of the Related Art For example, in a DIP (dual in-line package) type semiconductor device, a lead frame and bump electrodes of a semiconductor chip are wire-bonded, and then the semiconductor chip and its peripheral portion are molded with a resin material to form a package. I'm playing.

【0003】[0003]

【発明が解決しようとする課題】本発明者の検討によれ
ば、プラスチックパッケージによる従来のパッケージ技
術は、半導体チップ全体が放熱性に劣る絶縁物で覆われ
た構造であるため、半導体チップの消費電力が大きくな
ると放熱対策が難しいという問題がある。
According to a study made by the present inventor, the conventional packaging technology using a plastic package has a structure in which the entire semiconductor chip is covered with an insulating material having a poor heat dissipation property. There is a problem in that it is difficult to take heat dissipation measures as the electric power increases.

【0004】最近では、QFP(クァッド・フラット・
パッケージ)型の半導体装置においても放熱構造を備え
ることが要求される傾向にある。しかし、この場合も従
来のパワーICに採用されていたような放熱構造は採用
できない状況にある。
Recently, QFP (Quad Flat
The package) type semiconductor device also tends to be required to have a heat dissipation structure. However, even in this case, the heat dissipation structure used in the conventional power IC cannot be adopted.

【0005】そこで、本発明の目的は、パッケージに樹
脂材を用いた場合でも放熱構造を取り入れることが可能
な技術を提供することにある。
Therefore, an object of the present invention is to provide a technique capable of incorporating a heat dissipation structure even when a resin material is used for the package.

【0006】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0007】[0007]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。
Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

【0008】すなわち、パッケージ材に樹脂材を用いた
半導体装置であって、集積回路の形成が終了し且つダイ
シング前の1枚の半導体ウェハの裏面に放熱板を貼付
し、この後ダイシングを行って形成した半導体チップに
対しパッケージングを行うようにしている。
That is, in a semiconductor device in which a resin material is used as a packaging material, a heat dissipation plate is attached to the back surface of one semiconductor wafer before the formation of integrated circuits and before dicing, and then dicing is performed. The formed semiconductor chip is packaged.

【0009】[0009]

【作用】上記した手段によれば、ウェハ状態のときに放
熱板が貼付され、これを半導体チップにダイシングした
ものに対し、ボンディングをし、さらにパッケージング
が行われる。従って、通常の組立ラインを用いて放熱板
を内蔵した状態のパッケージが行え、要求される放熱が
可能な半導体装置をローコストに製造することができる
ようになる。
According to the above-mentioned means, the heat radiating plate is attached in the wafer state, the semiconductor chip is diced, and then bonded, and further packaged. Therefore, it is possible to manufacture a package with a built-in heat sink using a normal assembly line, and to manufacture a semiconductor device capable of required heat dissipation at low cost.

【0010】[0010]

【実施例】図1及び図2は本発明による半導体装置の製
造過程の一部を示す正面図であり、図1はウェハ状態に
おける正面図、図2はダイシング直後の状態を示す正面
図である。また、図3は組み立て完了後の半導体装置を
示す断面図である。
1 and 2 are front views showing a part of a manufacturing process of a semiconductor device according to the present invention, FIG. 1 is a front view in a wafer state, and FIG. 2 is a front view showing a state immediately after dicing. . 3 is a cross-sectional view showing the semiconductor device after completion of assembly.

【0011】図3に示すように、半導体チップ1の片面
(バンプ電極の設けられていない面)に接着材2を用い
て放熱板3が取り付けられている。接着材2には、耐熱
性の接着テープや接着剤を用いることができる。また、
放熱板3には、熱伝導性に優れる材料、例えば銅系合
金、アルミ合金、アルミナ基板等を用いることができ
る。このような半導体チップ1を組み立てる場合、ま
ず、タブ4上に放熱板3が固定され、ついで、ワイヤボ
ンダーを用いて半導体チップ1のバンプ電極(不図示)
とリード5とがワイヤ6によって接続される。
As shown in FIG. 3, a heat radiating plate 3 is attached to one surface of the semiconductor chip 1 (the surface where the bump electrodes are not provided) using an adhesive material 2. As the adhesive material 2, a heat-resistant adhesive tape or adhesive can be used. Also,
For the heat dissipation plate 3, a material having excellent thermal conductivity, such as a copper alloy, an aluminum alloy, or an alumina substrate, can be used. When assembling such a semiconductor chip 1, first, the heat dissipation plate 3 is fixed on the tab 4, and then a bump electrode (not shown) of the semiconductor chip 1 is formed using a wire bonder.
And the lead 5 are connected by the wire 6.

【0012】この後、モールド金型のキャビティ内に、
リード5の端部を含む半導体チップ1、放熱板3及びタ
ブ4の各部分が配設され、前記キャビティ内に溶融した
レジン7(例えばエポキシ樹脂)が圧入され、半導体チ
ップ1の封止が行われる。さらに、レジン7が固化した
後、パッケージから露出しているリード5を所定の形状
に曲げ加工すれば、半導体装置の組み立てが完了する。
After that, in the cavity of the molding die,
The semiconductor chip 1 including the ends of the leads 5, the heat sink 3 and the tab 4 are arranged, and the molten resin 7 (eg epoxy resin) is press-fitted into the cavity to seal the semiconductor chip 1. Be seen. Further, after the resin 7 is solidified, the leads 5 exposed from the package are bent into a predetermined shape to complete the assembly of the semiconductor device.

【0013】装置に組み込まれ、動作状態に入ると、消
費電力の大きい半導体チップ1の場合、その発熱による
熱は接着材2を介して放熱板3に伝導する結果、過渡熱
抵抗が改善され、半導体チップ1が熱破壊を招くことは
ない。
When the semiconductor chip 1 is installed in the apparatus and enters the operating state, in the case of the semiconductor chip 1 which consumes a large amount of power, the heat generated by the semiconductor chip 1 is conducted to the radiator plate 3 through the adhesive material 2, resulting in improvement of the transient thermal resistance. The semiconductor chip 1 does not cause thermal destruction.

【0014】次に、半導体チップに放熱板を取り付ける
方法について、図1及び図2を参照して説明する。
Next, a method of attaching the heat sink to the semiconductor chip will be described with reference to FIGS.

【0015】まず、図1に示すように、集積回路の形成
が終了し、かつダイシング前の1枚の半導体ウェハ8
(例えば、5インチ、8インチ径)に対し、その裏面の
全面に接着材9を塗布する。そして、この接着材9を介
して半導体ウェハ8と同サイズの放熱板10を貼着す
る。
First, as shown in FIG. 1, one semiconductor wafer 8 on which integrated circuit formation has been completed and before dicing has been completed.
The adhesive 9 is applied to the entire back surface of the adhesive (for example, diameter of 5 inches and 8 inches). Then, a heat radiating plate 10 having the same size as the semiconductor wafer 8 is attached via the adhesive material 9.

【0016】次に、図2に示すように、ダイシングライ
ン11(集積回路相互間を分断するようにX−Y方向に
設定されている)に沿ってダイシングソー(不図示)で
ダイシングし、1個づつの半導体チップに分離する。そ
の1個が図3に示す半導体チップ1である。
Next, as shown in FIG. 2, a dicing saw (not shown) is diced along the dicing line 11 (set in the XY directions so as to divide the integrated circuits from each other). Separate into individual semiconductor chips. One of them is the semiconductor chip 1 shown in FIG.

【0017】図1のように、放熱板10を貼着した半導
体ウェハは、通常の1枚の半導体ウェハとして扱うこと
ができるため、通常の組み立てラインを用いて行うこと
ができる。また、ダイシングした後で半導体チップに放
熱板を取り付ける場合に比べ、貼付工程を簡略化するこ
とができ、製品コストを下げることができる。
As shown in FIG. 1, since the semiconductor wafer to which the heat dissipation plate 10 is attached can be handled as a normal single semiconductor wafer, it can be performed using a normal assembly line. Further, as compared with the case where the heat dissipation plate is attached to the semiconductor chip after dicing, the attaching process can be simplified and the product cost can be reduced.

【0018】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the gist thereof. Needless to say.

【0019】例えば、上記実施例ではSOP型の半導体
装置について示したが、これに限定されるものではな
く、半導体チップに樹脂系の材料を用いた全ての半導体
装置に本発明を適用することができる。
For example, although the SOP type semiconductor device is shown in the above embodiment, the present invention is not limited to this, and the present invention can be applied to all semiconductor devices using a resin-based material for a semiconductor chip. it can.

【0020】[0020]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記の通りである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

【0021】すなわち、パッケージ材に樹脂材を用いた
半導体装置であって、集積回路の形成が終了し且つダイ
シング前の1枚の半導体ウェハの裏面に放熱板を貼付
し、この後ダイシングを行って形成した半導体チップに
対しパッケージングを行うようにしたので、通常の組立
ラインを用いて放熱板を内蔵した状態のパッケージが行
え、要求される放熱が可能な半導体装置をローコストに
製造することができるようになる。
That is, in a semiconductor device in which a resin material is used as a packaging material, a heat dissipation plate is attached to the back surface of one semiconductor wafer after the formation of integrated circuits and before dicing, and then dicing is performed. Since the formed semiconductor chip is packaged, a package with a built-in heat sink can be packaged using a normal assembly line, and a required semiconductor device capable of releasing heat can be manufactured at low cost. Like

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製造方法における1工程
を示す正面図である。
FIG. 1 is a front view showing one step in a method for manufacturing a semiconductor device of the present invention.

【図2】図1の状態からダイシングを行った状態を示す
正面図である。
FIG. 2 is a front view showing a state in which dicing is performed from the state of FIG.

【図3】組み立て完了後の半導体装置を示す断面図であ
る。
FIG. 3 is a cross-sectional view showing the semiconductor device after completion of assembly.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 接着材 3 放熱板 4 タブ 5 リード 6 ワイヤ 7 レジン 8 半導体ウェハ 9 接着材 10 放熱板 11 ダイシングライン 1 Semiconductor Chip 2 Adhesive Material 3 Heat Sink 4 Tab 5 Lead 6 Wire 7 Resin 8 Semiconductor Wafer 9 Adhesive 10 Heat Sink 11 Dicing Line

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 パッケージ材に樹脂材を用いた半導体装
置であって、集積回路の形成が終了し且つダイシング前
の1枚の半導体ウェハの裏面に放熱板を貼付し、この後
ダイシングを行って得られた半導体チップに対しパッケ
ージングを行うことを特徴とする半導体装置の製造方
法。
1. A semiconductor device using a resin material as a packaging material, wherein a heat dissipation plate is attached to the back surface of one semiconductor wafer after the formation of integrated circuits and before dicing, and then dicing is performed. A method of manufacturing a semiconductor device, which comprises packaging the obtained semiconductor chip.
【請求項2】 前記放熱板は、高熱伝導率の金属板また
はアルミナ基板であることを特徴とする請求項1記載の
半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the heat dissipation plate is a metal plate having a high thermal conductivity or an alumina substrate.
【請求項3】 前記放熱板の貼着は、接着テープまたは
接着剤を用いて行うことを特徴とする請求項1記載の半
導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the heat dissipation plate is attached using an adhesive tape or an adhesive.
JP5141048A 1993-06-14 1993-06-14 Manufacture of semiconductor device Pending JPH06349983A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5141048A JPH06349983A (en) 1993-06-14 1993-06-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5141048A JPH06349983A (en) 1993-06-14 1993-06-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06349983A true JPH06349983A (en) 1994-12-22

Family

ID=15283044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5141048A Pending JPH06349983A (en) 1993-06-14 1993-06-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06349983A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383895B1 (en) 1999-10-04 2002-05-07 Nec Corporation Method of forming a plurality of semiconductor devices
EP1246243A2 (en) * 2001-03-29 2002-10-02 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
CN117517394A (en) * 2023-10-17 2024-02-06 中国电子技术标准化研究院 A semiconductor discrete device chip bonding qualification testing method and device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6383895B1 (en) 1999-10-04 2002-05-07 Nec Corporation Method of forming a plurality of semiconductor devices
EP1246243A2 (en) * 2001-03-29 2002-10-02 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
CN117517394A (en) * 2023-10-17 2024-02-06 中国电子技术标准化研究院 A semiconductor discrete device chip bonding qualification testing method and device

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