JPH0636594A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent reducing of a relief factor and a substitution factor caused by defective redundant memory cells and to detect a defective factor of redundant memory cells, when cells. CONSTITUTION:Writing and reading operation of data for a redundant memory cell 9 is performed by setting a test mode by an input clock or combination of input clocks to an external test pin (test signal input terminal 30). A redundant fuse 5 is cut only for the redundant memory cell 9 except defective redundant memory cells, and defective memory cells are switched to the redundant memory cell 9. Therefore, relief factor and substitution factor are improved and defective factor of the redundant memory cell 9 is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device including redundant memory cells for relieving defective memory cells in addition to the main memory cells.

[0002]

2. Description of the Related Art Conventionally, when a redundant memory cell for repairing a defective memory cell in a main memory cell is provided, when the main memory cell is defective, the defective memory cell is processed through fuse cutting or the like. FIG. 2 shows a semiconductor memory device having a circuit for switching to a redundant memory cell. In FIG. 2, first, a data write / read test is performed on the main memory cell 3, and if there is a defective memory cell, the redundant fuse 5 is cut by a laser or the like to switch the defective memory cell 9 (redundant memory cell). Data 2 of main memory cell 3 is deactivated while cell 9 is selected). If the redundant memory cell 9 is a non-defective product, this operation makes the chip, which originally had the defective memory cell, a non-defective product.

In FIG. 2, there is a decoder 2 and a selection decoder 4 connected to the address bus 1.
The redundant decoder selection signal 6 is input to the decoder 2 and the redundant fuse 5 decode signal 7 of the redundant memory cell selection decoder is input to the redundant memory cell 9. The main memory cell 3 receives the decode signal 8 of the main memory cell selection decoder from the decoder 2. The data input / output bus 20 is
It is connected to the main memory cell 3 and the redundant memory cell 9.
There is also a control circuit 10.

[0004]

In the conventional semiconductor memory device, since data cannot be written in or read from the redundant memory cell 9 before the redundant fuse 5 is cut, the defective memory cell in the redundant memory cell 9 cannot be written. However, there is a problem that the defective memory cell cannot be detected.

In particular, with the recent increase in memory capacity, the redundant memory cell 9 has been correspondingly increased in capacity, and the probability of defective memory cells existing in the redundant memory cell 9 is increasing. In such a situation, even if the redundant memory cell 9 is switched to relieve the defective memory cell, if the defective memory cell exists in the redundant memory cell 9, the chip can be regarded as a good product. There was a problem that it did not exist.

An object of the present invention is to solve the above problems and provide a semiconductor memory device capable of detecting a defective memory in a redundant memory cell.

[0007]

According to the structure of the present invention, a redundant memory cell is provided in addition to the main memory cell, and when a defective memory exists in the main memory cell, the defective memory cell is set as the redundant memory cell. A semiconductor memory device having a control circuit for switching is provided with means for determining whether or not the redundant memory cell is the defective memory cell by setting a test mode.

[0008]

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, the present embodiment has an address bus 1, a main memory cell selection decoder 2 and a main memory cell 3.
A redundant memory cell selection decoder 4, a redundant fuse 5 for deactivating the redundant selection decoder, and a redundant memory 9.
A data write / read control circuit 10, a redundant memory cell selection pointer 14, and a data input / output bus 20.
And an OR gate 31.

Furthermore, the decode signal 7 of the redundant memory cell selection decoder, the decode signal 8 of the main memory cell selection decoder, the signal 11 which serves as both the redundant memory cell test mode signal and the pointer control signal, the selection decoder deactivation signal 12, The decode signal 13 of the redundant memory cell selection pointer 14 is shown.

After laser trimming the fuse 5,
The redundant decoder selection signal 6 can be generated. Traffic light 12
Performs the deactivation at high level. Terminal 30
Is a test signal input terminal.

Next, the redundant memory cell 9 in the present embodiment.
The test will be described. First, by inputting a pulse signal as a test signal from the terminal 30, the decoder 2 for selecting the main memory cell 7 is inactivated, and the pointer 14 for selecting the redundant memory cell 9 is initialized.
The redundant memory cells 9 are sequentially selected. Further, by inputting a write signal from the outside, data is sequentially written in the memory cells 9.

Next, by inputting a read signal instead of the write signal, the data written in the redundant memory cell 9 can be read. Therefore, according to this embodiment, the redundant memory cell 9 can be tested before the redundant fuse 5 is cut.

[0014]

As described above, according to the present invention,
In a semiconductor memory device having a redundant memory cell for repairing a defective memory cell of a main memory cell and a circuit for switching a defective memory in the main memory cell, a test mode by clock input to an external test pin or a combination of input clocks Depending on the setting, since the redundant memory cell has means for writing or reading, it is possible to test the redundant memory cell before disconnecting the redundant fuse. Therefore, the defective memory included in the redundant memory cell can be tested. Since the redundant fuse can be cut so that the cell is found and the memory cell is not selected, the chip rescue rate,
The replacement rate can be significantly improved, and the defective rate of the redundant memory cells can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional semiconductor memory device.

[Description of Codes] 1 address bus 2 main memory cell selection decoder 3 main memory cell 4 redundant memory cell selection decoder 5 redundant fuse 6 redundant decoder selection signal 7 redundant memory cell selection decoder decode signal 8 main memory cell selection decoder decode signal 9 redundant memory cell 10 read / write control circuit 11 redundant memory cell test mode signal / pointer control signal 12 selective decoder deactivation signal 13 redundant memory cell select pointer decode signal 14 redundant memory cell select pointer 20 data input / output bus 30 Test signal input terminal 31 OR gate

Claims (2)

[Claims] 1. A semiconductor memory device having a redundant memory cell other than the main memory cell, and having a control circuit for switching the defective memory cell to the redundant memory cell when a defective memory exists in the main memory cell, A semiconductor memory device comprising means for determining whether or not the redundant memory cell is the defective memory cell by setting a test mode. 2. The semiconductor memory device according to claim 1, wherein the test mode is a mode in which a clock is input to an external test pin or a combination of input clocks is used.