JPH0637042A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a semiconductor integrated circuit device having a high melting point metal film which has excellent adhesion to an insulating film, good step coverage, a flat film surface, and excellent fine workability. To provide. [Structure] A diameter of 0.5 μm provided on a semiconductor substrate
In the following, the W film 22 provided on the micropores having a depth / diameter ratio of 1 or more (a narrow groove having a minimum width of 0.5 μm or less and a depth / minimum width ratio of 1 or more) , 24. A semiconductor integrated circuit device having: The lowermost portion of the W film is composed of a layer containing silicon of 10 atomic% or more and 85 atomic% or less.
The step coverage with respect to the micropores of the W film is 0.7 or more, and the surface unevenness / average film thickness is 0.2 or less. The W film can be formed by the CVD method in which the halide of W is reduced by SiH ₂ F ₂ .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having wiring made of refractory metal and a method for manufacturing the same.

[0002]

2. Description of the Related Art Aluminum or aluminum alloys (hereinafter, both are abbreviated as Al) have been used as wiring materials for semiconductor integrated circuits. However, with Al wiring, disconnection occurs due to phenomena such as stress migration and electromigration, and sufficient reliability cannot be ensured, which is a problem. Therefore, wiring is formed of a refractory metal such as tungsten (hereinafter abbreviated as W). The refractory metal used for wiring of these semiconductor integrated circuits is conventionally a sputtering method or a chemical vapor deposition method in which a halide of a refractory metal is reduced by hydrogen (hereinafter abbreviated as H ₂ ) or monosilane (hereinafter abbreviated as SiH ₄ ). (Hereinafter, abbreviated as H ₂ reduction method and SiH ₄ reduction method). For example, the H ₂ reduction method is described in US Pat. No. 3,697,343. Also,
The SiH ₄ reduction method is described in JP-A-59-72132.

[0003]

Although the size of the connection hole has been reduced along with the high integration of the semiconductor integrated circuit, the surface of the interlayer insulating film needs to be flattened.
The film thickness has hardly decreased. As a result, the aspect ratio of the connection hole (connection hole depth / connection hole diameter) is significantly high. In order to form a wiring with low resistance and high reliability in a structure having a hole with a high aspect ratio, in addition to embedding a metal with excellent adhesiveness with an interlayer insulating film in the connection hole with sufficient step coverage, It is necessary that the surface of the embedded metal film is flat. This is because if the metal film surface has large irregularities, a local overhang shape is formed in the convex portions, and a problem arises in that the insulating film is not deposited at this portion during subsequent deposition of the insulating film. Furthermore, when a metal film is processed by photolithography and dry etching techniques to form wiring, if the surface of the metal film is not flat, the irregular reflection of light lowers the resolution, which makes fine processing difficult. At this time, considering the reliability and the fine workability of the wiring, the step coverage (ratio of the film thickness of the thinnest part such as the lower part of the step in the thin film formed on the substrate having the step to the film thickness of the flat part) Is 0.7 or more, and in terms of flatness, surface irregularities / average film thickness is preferably 0.2 or less.

However, among the above-mentioned conventional techniques, the sputtering method and the SiH ₄ reduction method have a good flatness of the formed film, but have a low step coverage and are not suitable for burying a connection hole. On the other hand, the H ₂ reduction method has good step coverage of the formed film, but has a problem that the film surface is not flat. Further, when the refractory metal film is formed by the SiH ₄ and H ₂ reduction method, the refractory metal film has poor adhesion to the base insulating film,
It is necessary to form an adhesive layer between them. However, when the adhesive layer is formed by the sputtering method, since the step coverage is low, the adhesive layer having a sufficient thickness cannot be formed at the bottom of the connection hole. On the other hand, a method of using a titanium nitride (hereinafter abbreviated as TiN) film formed by a chemical vapor deposition method (hereinafter abbreviated as CVD method) as an adhesive layer has also been studied, but in this case, the step coverage is high and the connection hole is formed. Although an adhesive layer having a sufficient thickness can be formed at the bottom of the, there is a problem that the surface of the refractory metal film formed thereon is not flat. This is because when forming the refractory metal film, nucleation is unlikely to occur on the TiN film, and uniform film growth is unlikely to occur.

As described above, none of the above-mentioned prior arts can simultaneously satisfy the three requirements of adhesiveness, high step coverage and flatness of the film surface, and therefore low resistance and reliability in the connection hole. There was a problem that it was not possible to form high wiring. Further, there is a problem that the refractory metal film cannot be processed into fine wiring. Further, in order to improve the reliability of Al or copper (hereinafter abbreviated as Cu) wiring, a laminated structure of a refractory metal and Al or Cu has been widely studied.
When an Al or Cu film is formed on a refractory metal film whose surface is not flat, grain growth of the Al or Cu film is suppressed. As a result, Al and Cu are easily broken, and the reliability of the wiring is reduced. Further, if the refractory metal film surface has irregularities, irregularities corresponding to the irregularities of the refractory metal film surface also occur on the Al or Cu film surface formed thereon, so that when the wiring is formed, the high melting point metal There is a problem that it becomes difficult to perform fine processing of a laminated film of metal and Al or Cu.

An object of the present invention is to provide a semiconductor integrated circuit device having a refractory metal film which has excellent adhesion to an insulating film, good step coverage, a flat film surface, and excellent fine workability. It is to provide the manufacturing method.

[0007]

In order to achieve the above object, a semiconductor integrated circuit device of the present invention comprises a semiconductor substrate, a diameter of 0.5 μm or less and a depth / diameter of the semiconductor substrate. A fine hole having a ratio of 1 or more or a minimum width of 0.5 μm or less, and a fine groove having a depth / minimum width ratio of 1 or more, and a high melting point metal film provided on the fine hole or the fine groove; The lowermost part of the refractory metal film is composed of a layer containing silicon of 10 atomic% or more and 85 atomic% or less, the step coverage with respect to fine holes or fine grooves is 0.7 or more, and the surface unevenness / average film thickness is 0.1. Two
It is as follows.

The thickness of the layer containing silicon is preferably 3 nm or more and 50 nm or less on the main plane. The total thickness of the refractory metal film is 1 on the main plane.
It is preferably from 00 nm to 500 nm,
It is more preferably 100 nm or more and 200 nm or less. It is preferable that the step coverage is 1 or less, and the surface unevenness / average film thickness exceeds 0. Further, as the material of the refractory metal film, tungsten, molybdenum or the like is used. Further, a wiring thin film made of a material different from that of the refractory metal may be laminated and used on the refractory metal film. As a material of such a wiring thin film, aluminum or a group IV element such as germanium in the aluminum, copper,
An aluminum alloy containing one or more elements selected from precious metal elements such as palladium and refractory metal elements such as titanium and tantalum is used. Further, copper or a copper alloy in which one or more elements selected from corrosion-resistant metal elements such as nickel, precious metal elements such as palladium, and refractory metal elements such as titanium and tantalum are added to copper are also used.

This refractory metal film is a halide of a refractory metal element such as tungsten hexafluoride (WF ₆ ).
And difluorosilane (SiH ₂ F ₂ ) can be used for the chemical vapor deposition method. In that case, first, a layer containing Si is formed, and then the ratio of the halide of the refractory metal element and difluorosilane used is changed to form a refractory metal layer containing almost no Si. Since two layers can be continuously formed with the same source gas and the same temperature, a film with high throughput can be formed. Therefore, the cost can be suppressed, and there is no natural oxide film at the interface between the layer containing Si and the refractory metal layer,
The resistivity of the refractory metal film can be lowered.

[0010]

The high melting point metal layer containing Si has excellent adhesion to the insulating film, and moreover, nucleation is likely to occur when the high melting point metal film is formed thereon. Therefore, by making the lower part of the refractory metal film a refractory metal layer containing Si, peeling of the refractory metal film can be prevented, uniform film growth is performed, and the surface becomes flat. Also,
In the method of manufacturing the refractory metal film, SiH ₂ F ₂ is used as SiH ₄
Since the reactivity with WF ₆ is lower than that of the method described above, the film formation can be performed under the condition that the surface reaction is rate-determining, so that a film with high step coverage can be obtained. Further, since the temperature at which the film is formed can be lowered from 200 ° C. to 400 ° C., surface migration of refractory metal atoms during the film formation is suppressed. Therefore, the crystal grain size does not become coarse and the surface of the film becomes flat.

[0011]

【Example】

Example 1 W was used as a refractory metal, and the relationship between step coverage, surface unevenness / average film thickness, wiring reliability, and fine workability when W was embedded in a hole of 0.5 μm was investigated. . The method and the result will be described below.

First, as shown in FIG. 1, p-type 10 Ωcm
After the field oxide film 2 is formed on the (100) Si substrate 1 by the LOCOS process, As ions are implanted by an ion implantation method under the condition of a dose amount of 1 × 10 ¹⁵ cm ² and then a predetermined heat treatment (hereinafter Called anneal)
The mold diffusion layer 3 was formed. After that, PS with a thickness of 500 nm
A G (phosphorus glass) film 4 is formed by the CVD method, and then N ₂
Annealing was performed in the atmosphere to densify the PSG film 4. After that, a vertical contact hole having a diameter of 0.5 μm was opened by using a normal photolithography technique. Then, as shown in FIG. 2, a W layer 5 containing Si having a thickness of 30 nm in a flat portion outside the contact hole was formed by a CVD method. The conditions for forming the W layer 5 containing Si are: substrate temperature = 450 ° C., WF ₆ flow rate = 5 sccm, S
iH ₂ F ₂ flow rate = 2000 sccm, argon (hereinafter Ar
Flow rate = 300 sccm, total pressure = 0.5 Torr
Met. When the Si content in the film was examined by Auger electron spectroscopy, it was 80 at%.

Next, as shown in FIG. 3, WF ₆ and Si
Low pressure CVD method using H ₂ F ₂ as a source gas (SiH ₂ F ₂
The W layer 6 was formed by the reduction W-CVD method. The W layer 6 and the W layer 5 containing Si form a refractory metal film. The step coverage and surface irregularities / average film thickness were examined. CV
D condition is substrate temperature = 200 to 400 ° C., WF ₆ flow rate =
100 sccm, SiH ₂ F ₂ flow rate = 50 to 400 scc
m, Ar flow rate = 300 sccm, total pressure = 0.5 Torr
Met. Experiments were also conducted by the H ₂ reduction method and the SiH ₄ reduction method. The CVD conditions in the H ₂ reduction method are: substrate temperature =
450-475 ° C., WF ₆ flow rate = 80 sccm, H ₂ flow rate = 4000 sccm, Ar flow rate = 140 sccm, total pressure = 0.65 Torr, CVD by SiH ₄ reduction method
The conditions are: substrate temperature = 250 to 300 ° C., WF ₆ flow rate = 8
0 sccm, SiH ₄ flow rate = 65 sccm, Ar flow rate =
250 sccm, total pressure = 0.35 Torr. Note that the step coverage is as shown in FIG.
Is defined as the ratio a / t of the film thickness a of the thinnest part of the above and the average film thickness t of the W layer 6 formed in the flat part outside the hole. Also,
The surface unevenness is the maximum film thickness tmax and the minimum film thickness t when examined with a scanning electron microscope over a region having a width of 10 μm.
The difference was min.

Returning to FIG. 3 again, after that, the W layer 6 and the W layer 5 containing Si are processed by the usual photolithography technique to form the wiring of the refractory metal film. At this time, the processed shape of the wiring having a width of 0.3 μm was observed by SEM to examine the fine workability of the W film. After that, an SiO film (hereinafter abbreviated as plasma SiO) formed by the plasma CVD method is used, and plasma SiO / SOG (coating glass) / plasma SiO laminated film 7 (thickness: 150 nm / 200 nm / 150 nm, respectively, 500 n in total).
After m) was deposited, an opening for electrode connection was formed by using a normal photolithography technique, and an element for electrical property evaluation was prepared. In all the samples, there was no problem of peeling of the W film, and it was found that the W layer 5 containing Si was effective as the adhesive layer.

The resistance of the contact portion, which is the sum of the contact resistance between the n-type diffusion layer and the W film and the wiring resistance of W inside the contact hole, was measured. Then, considering that the resistance of the contact portion is 100Ω or less as a non-defective product, if the non-defective product ratio is 99% or more, it is evaluated as ○, and if less than 99%, it is evaluated as ×. It is shown in Table 1 together with the step coverage. In addition, the fine workability is 0.
Table 1 shows ◯ when fine processing of 3 μm is possible and x when difficult.

[0016]

[Table 1]

In all the samples subjected to SiH ₂ F ₂ reduction, the step coverage is 0.7 or more and the surface unevenness / average film thickness is 0.2 or less, and the reliability of the contact resistance is also good. was gotten. On the other hand, when H ₂ reduction or SiH ₄ reduction was performed, there were samples with high resistance at the contact portion and samples with no conduction, and the reliability was low. In the case of H ₂ reduction, since the surface unevenness is large, a portion where the plasma SiO film is not formed occurs behind the convex portion of the W film.
The SOG comes into contact with the W film at that portion, and the W layer 6 and the W layer 5 containing Si are corroded by the water or the like emitted from the SOG and become non-conductive, which is a cause of low reliability. Since SiH ₄ reduction has low step coverage, the W layer 6 is thin at the bottom of the hole, and the W film at the bottom of the hole is completely oxidized when the plasma SiO film is formed. Therefore, only the W layer 5 containing high-resistance Si is in a state of maintaining electrical continuity, and the resistance of the contact portion increases, resulting in a defect.

From the above results, in order to obtain low contact resistance and the like with high reliability, it is necessary to form a W film having a step coverage of 0.7 or more and a surface unevenness / average film thickness of 0.2. I found out. For holes with a diameter smaller than 0.5 μm and an aspect ratio of 1 or more, it is more difficult to secure the reliability of wiring than the holes investigated this time.
It is clear that the conditions of step coverage and flatness must be satisfied. Next, regarding the fine workability, in the case of SiH ₂ F ₂ reduction and SiH ₄ reduction, 0.3
It has been found that fine processing of μm is possible, but in the case of H ₂ reduction, a problem of resolution occurs in the photolithography process and it is difficult to perform fine processing. This result is compared with the value of surface unevenness / average film thickness, and in order to realize fine processing of 0.3 μm, a flat W film having a surface unevenness / average film thickness of 0.2 or less must be formed. I knew it wouldn't happen. From the above, in order to secure reliability at the contact portion and enable fine processing, the step coverage of the W film is set to 0.7 or more and the surface unevenness / average film thickness is set to 0.2 or less. It is necessary.

Further, instead of a hole having a diameter of 0.5 μm, a groove width of 0.
The same embedding was carried out for a sample provided with a groove having a depth of 5 μm and a depth of 500 nm, and the same effect as described above was obtained. Furthermore, a WF is formed on the contact hole or groove.
_{In the same} manner as above except that MoF ₆ was used instead of ₆ ,
A film was formed to make a similar device. The properties of the Mo film and the device were the same as above.

Example 2 In this example, a conductor film formed by various methods was used as an adhesive layer to fill a 0.5 μm hole in the same manner as in Example 1 above to obtain a step coverage, surface unevenness / The results of investigating the relationship between the average film thickness and the wiring reliability will be described. By the same steps as those in the first embodiment, as shown in FIG.
A field oxide film 2, an n-type diffusion layer 3 and a PSG film 4 are formed on a mold 10 Ωcm (100) Si substrate 1 and have a diameter of 0.
A vertical contact hole of 5 μm was opened.

Next, as shown in FIG. 2, a W layer 5 containing Si was formed. The W layer 5 containing Si is SiH
Reacting ₂ F ₂ , SiH ₄ and SiH ₂ Cl ₂ with WF ₆
The various CVD methods were used for comparison. The CVD conditions when SiH ₂ F ₂ is used are: substrate temperature = 300 to 450 ° C.,
WF ₆ flow rate = _{2 to} 10 sccm, SiH ₂ F ₂ flow rate = 15
The flow rate was 0 to 1000 sccm, the Ar flow rate was 300 sccm, and the total pressure was 0.5 Torr. The CVD conditions when SiH ₄ is used are: substrate temperature = 350 ° C., WF ₆ flow rate = 10
sccm, SiH ₄ flow rate = 1000 sccm, total pressure =
It was 0.2 Torr. The CVD conditions when SiH ₂ Cl ₂ is used are: substrate temperature = 600 ° C., WF ₆ flow rate = 15
sccm, SiH ₂ Cl ₂ flow rate = 1000 sccm, total pressure = 0.5 Torr.

The Si content of the layer formed under each condition was determined by Auger electron spectroscopy. If the W layer contains Si, the resistivity becomes high. Therefore, if the W film containing Si becomes thicker, the wiring resistance of W embedded in the contact hole increases. Therefore, the thickness of the W layer containing Si needs to be 1/10 or less of the diameter of the contact hole, and is preferably as thin as possible within the range of functioning as an adhesive layer. In this example, the diameter of the contact hole was 0.5 μm, so that the thickness of the W layer 5 containing Si was 2 to 50 nm.
Was changed in the range. Further, instead of the W layer 5 containing Si, a W layer was formed by a sputtering method or a TiN layer was formed by a CVD method.

Next, a W layer 6 was formed on the substrate on which these various adhesive layers were formed by the SiH ₂ F ₂ reduction W-CVD method, and the step coverage and the surface unevenness / average film thickness were examined. C
VD conditions are: substrate temperature = 300 ° C., WF ₆ flow rate = 100
sccm, SiH ₂ F ₂ flow rate = 400 sccm, Ar flow rate = 300 sccm, total pressure = 0.5 Torr. Here, the definition of the step coverage and the surface unevenness is as defined in Example 1 above.
Is the same as.

Thereafter, the W layer 5 and the W layer 6 containing Si are processed into a wiring shape by the same process as in the first embodiment, and the plasma SiO / SOG / plasma SiO laminated film 7 is formed.
Was deposited, an opening for electrode connection was formed, and an element for electrical characteristic evaluation as shown in FIG. 3 was prepared. The results of reliability evaluation of the W wiring using the sample as described above are shown in Table 2 together with the step coverage and the like.

[0025]

[Table 2]

When the W layer 5 containing Si is used for the adhesive layer, SiH ₂ F ₂ , SiH ₄ or Si is used for forming the adhesive layer.
No matter which gas of H ₂ Cl ₂ is used, the film thickness is 3 nm or more and 50 nm or less, and the Si content is 10 nm or less.
If it is at% or more and 85 at% or less, a low resistance value can be obtained in the contact portion with high reliability. Si
When the thickness of the W layer 5 including the element is 2 nm (Sample No. 1)
Does not have sufficient adhesive strength, and the film is
Since it was peeled off from the SG film 4, resistance measurement became impossible. Also, when the Si content was 8 at% or less (Sample No. 8), the adhesiveness was poor and peeling occurred, so that resistance measurement became impossible. In addition, when the Si content was 88 at% or more (Sample No. 11), the contact resistance between the n-type diffusion layer and the W film was high, and it became defective. On the other hand, W formed by the sputtering method
When the layer was used as the adhesive layer (Sample No. 14), W was not formed at the bottom of the hole, a large number of contact holes became non-conductive, and the reliability of the W wiring was low. Also, TiN
When (A) was used for the adhesive layer (Sample No. 15), the surface irregularities / average film thickness was as large as 0.4, so that there was a portion where the plasma SiO film was not formed behind the convex portion of the W film.
At that portion, the SOG contacted the W film, and the W layer 6 and the W layer 5 containing Si were corroded by the moisture or the like emitted from the SOG, so that many samples became non-conductive and the reliability was low. Further, since the surface of the W layer 6 has large irregularities, the resolution of photolithography is low, and a wiring having a width of 0.3 μm cannot be formed.

From the above results, in order to obtain a low resistance value in the contact portion with high reliability, Si should be 10-8.
It was found that it was necessary to form a W layer containing 5 at% by the CVD method and use it as an adhesive layer. 0.5μ diameter
For holes smaller than m and having an aspect ratio of 1 or more,
Since it is more difficult to secure the reliability of the wiring than the hole examined this time, it is clear that the refractory metal film formation according to the present invention becomes more and more advantageous.

In the present embodiment, even when the W layer 5 containing Si is formed by using SiH ₂ F ₂ as the reducing gas, the W layer 5 containing Si and the W layer 6 mainly contain the difference in the formation temperature.
Were formed in separate CVD steps. However, when forming the W layer 5 containing Si at the same 350 ° C. as the formation of the W layer 6 (Sample No. 7), it is possible to change the gas flow rate midway and
It is also possible to continuously form the W layer 5 and the W layer 6 containing i in the same process. In this case, the W layer 5 and the W layer 6 containing Si are not exposed to the air during the process.
A natural oxide film was not formed during this period, and the resistance of the contact portion became lower than the above result. Moreover, since the number of steps can be reduced, there is an effect of suppressing the cost.

In this embodiment, after the W layer 5 containing Si is formed, the W layer 6 is subsequently formed without annealing. However, it is also possible to form the W layer 6 after forming the W layer 5 containing Si and annealing to crystallize the W layer 5 containing Si. In this case, since the resistivity of the W layer 5 containing Si is lowered, there is an effect that the resistance of the contact portion is lowered.

Embodiment 3 FIGS. 5 to 10 are views showing a manufacturing process of a MOS-FET integrated circuit device produced by using a refractory metal W as a wiring material. First, as shown in FIG.
00) Field oxide film 2, thickness 8n on Si substrate 1
m after the gate oxide film 8 is formed, the polycrystalline silicon film 9 is formed.
(Thickness: 300 nm) is deposited by a low pressure CVD method, an impurity is added to reduce the resistance, and then patterned into a predetermined shape by using a normal photolithography technique.
And Next, using this gate electrode 9 as a mask, A
After implanted s ions at a dose of 1 × 10 ¹⁵ cm ~ ^2, annealing is performed to form the source and drain regions 10. After that, CV by HLD (high temperature low pressure decomposition method)
After depositing the SiO ₂ film 11 by the D method, a so-called LDD (lightly doped drain) structure was formed by dry etching the entire surface, leaving the SiO ₂ film 11 only in the peripheral portion of the gate.

After that, as shown in FIG.
m BPSG (boron-doped PSG) film 12 by CV
After deposition by the D method, annealing was performed in an N ₂ atmosphere to densify the BPSG film 12, and then a contact hole 13 having a diameter of 0.3 μm was formed by using a normal photolithography technique. Next, as shown in FIG. 7, SiH ₂
A W film 14 having a thickness of 500 nm was deposited by the F ₂ reduction CVD method. The CVD conditions are WF ₆ , SiH _{2 for} the first minute.
The flow rates of F ₂ and Ar are 5, 1000 and 300 s, respectively.
ccm, total pressure was 0.5 Torr, and temperature was 350 ° C. After that, the flow rates of WF ₆ , SiH ₂ F ₂ and Ar were set to 100, 400 and 300 sccm, respectively.

When the formed W film 14 was analyzed by Auger electron spectroscopy, it was found that the W film 14 was the underlying BPSG film 1.
20 nm from the interface with 2 contains 68 at% of Si, and at 480 nm from that surface to the surface, Si has a detection limit of 1
It was at% or less. The W film 14 is the underlying BPSG film 12
And the step coverage in the contact hole 13 was 0.7. According to this example, since the layer containing Si and the layer not containing Si can be continuously formed by one step, the manufacturing process can be simplified and the cost can be suppressed. Moreover, since it is formed continuously, a natural oxide film is not formed between the layer containing Si and the layer not containing Si, which has the effect of reducing the resistance of the W film.

Subsequently, the W film 14 was processed into a wiring shape by using a normal photolithography technique. At this time, the W film 1
Since the surface of No. 4 was flat, a wiring having a width of 0.3 μm could be formed. After that, plasma SiO / SOG /
Plasma SiO laminated film 7 (thickness: 300 nm / each)
400 nm / 300 nm, total 1 μm),
The W film is formed on the laminated film 7 by using a normal photolithography technique.
A connection hole 15 having a diameter of 0.4 μm reaching the film 14 was formed.

Then, as shown in FIG. 8, a W layer 16 containing Si having a thickness of 30 nm was deposited as a bonding layer by a CVD method. The CVD conditions are as follows: substrate temperature is 300 ° C., WF ₆
And SiH ₂ F ₂ flow rates of 5 and 1000 scc, respectively.
m, total pressure was 0.5 Torr, and formation time was 3 minutes. After that, a W layer 17 having a thickness of 500 nm was deposited on the entire surface of the substrate by the SiH ₂ F ₂ reduction W-CVD method. The CVD conditions are such that the flow rates of WF ₆ , SiH ₂ F ₂ and Ar are 1 each.
00, 400, 300 sccm, total pressure 0.5 Torr
And the temperature was 400 ° C. After that, the W layers 16 and W containing Si are entirely etched so that the W layers 16 and W containing Si only in the contact holes 15 as shown in FIG.
Layer 17 was left. Then, as shown in FIG.
Film 18 (thickness 150 nm), Al film 19 (thickness 800 n)
m) were sequentially deposited by a sputtering method, and a second layer of Al wiring was formed by using a normal photolithography technique.

In this embodiment, since the contact hole 13 and the connection hole 15 between the wirings are filled with the W film 14, the W layer 16 and the W layer 17 containing Si, a flat multilayer wiring structure is obtained, Problems such as step breakage of Al wiring have been greatly improved. Further, the contact resistance with the source / drain and the contact resistance between the layers of the W wiring and the Al wiring are
This is reduced compared to the case where insufficient embedding was performed by the conventional method. In this embodiment, as the interlayer insulating film, the BPSG film 12 is used as the first layer and plasma SiO / is used as the second layer.
Although the laminated film 7 of SOG / plasma SiO was used, the same effect was obtained by using PSG, a polyimide-based heat-resistant organic polymer insulating film, or the like instead. Further, instead of the Al film 19, Al-Cu-Si (Cu 1.5 wt%, Si
0.5% by weight), Al-Cu (Cu 1% by weight) aluminum alloy is also used, but is also one of group IV elements such as germanium, precious metal elements such as palladium, and refractory metal elements such as titanium and tantalum. Similar effects were obtained using an aluminum alloy containing the above elements.

Example 4 FIGS. 11 to 13 show a MOS-FE made by using W for a gate electrode and using a laminated structure of W and Al as a wiring material.
It is a figure which shows the manufacturing process of a T integrated circuit device. First, Fig. 1
As shown in FIG. 1, after forming the field oxide film 2 and the gate oxide film 8 having a thickness of 8 nm on the p-type (100) Si substrate 1, the W film 20 having a thickness of 100 nm was formed. The CVD conditions were such that the flow rates of WF ₆ , SiH ₂ F ₂ and Ar were 5, 1000 and 300 sccm, the total pressure was 0.5 Torr, and the temperature was 350 ° C. for the first 1 minute. afterwards,
The flow rates of WF ₆ , SiH ₂ F ₂ and Ar are 100,
It was set to 400 and 300 sccm. When the formed W film 20 was analyzed by Auger electron spectroscopy, the W film was
Si is 68 at% at 20 nm from the interface with the underlying oxide film
At 80 nm from the content to the surface, Si was below the detection limit of 1 at%. The W film 20 had good adhesion to the underlying oxide film and did not peel off.

Then, after forming a PSG film 21 having a thickness of 30 nm, P is formed by using a normal photolithography technique.
The SG film 21 and the W film 20 were patterned into a gate electrode shape. At this time, since the surface of the W film 20 is flat, 0.1
A μm gate electrode could be formed. Then P
Using the SG film 21 and the gate electrode as a mask, As ions are implanted under the conditions of an energy of 80 keV and a dose amount of 1 × 10 ¹⁵ cm to ² , and then heat treatment is performed at 900 ° C. for 10 minutes,
The source / drain region 10 was formed. Then HLD
After the SiO ₂ film 11 is deposited by the CVD method using SiO ₂ , the entire surface is dry-etched to form SiO ₂ only on the peripheral portion of the gate.
With the film 11 left, an LDD structure as shown in FIG. 11 was formed.

Then, by the same steps as in Example 3, B
A PSG film 12 was formed and a contact hole having a diameter of 0.3 μm was opened. Then, as shown in FIG. 12, SiH ₂ F ₂
A 250 nm W film 22 was formed by the reduction W-CVD method. The CVD conditions are that the substrate temperature is 300 ° C., and the WF ₆ and SiH ₂ F ₂ flow rates are 5 and 1000 respectively for the first 2 minutes.
sccm, total pressure 0.5 Torr, then W
The flow rates of F ₆ , SiH ₂ F ₂ and Ar are 100 and 4, respectively.
The pressure was set to 00, 300 sccm, and the total pressure was set to 0.5 Torr.
When the formed W film 22 was analyzed by Auger electron spectroscopy, the W film 22 contained 64 at% of Si at 20 nm from the interface with the underlying BPSG film 12, and Si was detected at 230 nm from the interface to the surface. It was below the limit.

After that, a thickness of 400 n is obtained by the sputtering method.
m Al film 23 is deposited, and the Al film 23 and the W film 22 are processed by an ordinary photolithography technique to form Al /
A W laminated wiring was formed. Although the Al film 23 is not deposited inside the contact hole, it has a low contact resistance because it is electrically connected to the source / drain region 10 through the W film 22. The average crystal grain size of the Al film 23 was about 2 μm.
This is about 1 μm larger than the average crystal grain size of the Al film formed on the W film deposited by the H ₂ reduction W-CVD method, and about 2 μm when formed on the W film deposited by the sputtering method. Is the same as. Further, when a reliability test of the wiring was conducted, the Al / W laminated wiring formed by this example showed the same degree of reliability as the Al / W laminated wiring formed by the sputtering method.

After that, as shown in FIG. 13, plasma S
iO / SOG / plasma SiO layered film 7 (thickness: 300 nm / 400 nm / 300 nm, total 1 μm)
After depositing, the plasma SiO / SOG / plasma SiO laminated film 7 is formed by using a normal photolithography technique.
A connection hole having a diameter of 0.4 μm reaching the Al film 23 was formed on the substrate. Then, SiH ₂ F ₂ reduction W-CVD method
A W film 24 of nm thickness was formed. CVD conditions are substrate temperature 3
At 00 ° C., WF ₆ and SiH ₂ F ₂ flow rates are 5 and 1000 sccm, respectively, and total pressure is 0.5 Torr for the first 2 minutes.
After that, the flow rates of WF ₆ , SiH ₂ F ₂ and Ar are 100, 400 and 300 sccm, respectively, and the total pressure is 0.5.
Torr. When the formed W film 24 was analyzed by Auger electron spectroscopy, it was confirmed that the W film 24 was
20 nm from the interface with the film 23 contained 64 at% of Si, and at 280 nm from that interface to the surface, Si was below the detection limit. After that, 500 nm by sputtering method
The Al film 25 was formed, and the Al film 25 and the W film 24 were processed by using a normal photolithography technique to form the wiring of the second layer.

In the H ₂ reduction W-CVD method, the formation temperature is 45.
Since it is as high as 0 ° C, if a W film is formed on the Al film, Al / W
There was a reliability problem such as a reaction at the interface. In the present invention, since the formation temperature is low, such a problem does not occur, and it is possible to form a W film having high step coverage on the Al film without impairing the reliability of the Al film. In this embodiment, since the resistance of the integrated circuit can be reduced by forming the gate electrode with W, the operating speed of the integrated circuit can be increased. Further, although the Al film is formed by the sputtering method in this embodiment, the Al film may be formed by the CVD method. Alternatively, a Cu film may be used instead of the Al film to form the laminated wiring.

[0042]

According to the present invention, a refractory metal film having good adhesion to an insulating film, high step coverage, a flat surface and a high aspect ratio embedded in a connection hole or a narrow groove. A semiconductor integrated circuit device having is obtained. Further, in the present invention, since the Si compound is used as the reducing gas, the layer containing Si and the refractory metal layer can be continuously formed at the same source gas and at the same temperature, so that a film with high throughput can be formed. Therefore, the cost can be suppressed, and the Si
Since there is no natural oxide film at the interface between the layer containing Pt and the refractory metal layer, the refractory metal film has a low resistivity. Further, according to the present invention, it is possible to obtain a wiring in which a highly reliable Al, Cu film or the like is laminated on the refractory metal film. Further, according to the present invention, a fine refractory metal wiring or a wiring in which Al, Cu or the like is laminated can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram for explaining the definition of a step coverage factor and surface unevenness in the semiconductor device of Example 1 of the present invention.

FIG. 5 is a schematic view showing a manufacturing process of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 6 is a schematic diagram showing a manufacturing process of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 7 is a schematic diagram showing a manufacturing process of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 8 is a schematic view showing the manufacturing process of the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 9 is a schematic view showing the manufacturing process of the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 10 is a schematic view showing the manufacturing process of the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 11 is a schematic view showing the manufacturing process of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

FIG. 12 is a schematic view showing the manufacturing process of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

FIG. 13 is a schematic view showing the manufacturing process of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

[Explanation of symbols]

1 Si substrate 2 field oxide film 3 n-type diffusion layer 4 PSG film 5, 16 Si-containing W layer 6, 17 W layer 7 plasma SiO / SOG / plasma SiO laminated film 8 gate oxide film 9 gate electrode 10 source / drain Region 11 SiO ₂ film 12 BPSG film 13 Contact hole 14, 20, 22, 24 W film 15 Connection hole 18 Ti-W film 19, 23, 25 Al film 21 PSG film

Claims (9)

[Claims] 1. A semiconductor substrate, micropores having a diameter of 0.5 μm or less and a depth / diameter ratio of 1 or more, or a minimum width of 0.5 μm or less and a depth / diameter provided on the semiconductor substrate. A fine groove having a minimum width ratio of 1 or more and a high melting point metal film provided on the fine hole or the fine groove, and the lowermost part of the high melting point metal film is 10 atomic% or more and 85 atomic% or less. A semiconductor integrated circuit device comprising a layer containing silicon and having a step coverage of 0.7 or more and a surface irregularity / average film thickness of 0.2 or less with respect to the fine holes or fine grooves. 2. The semiconductor integrated circuit device according to claim 1, wherein the layer containing silicon has a thickness of 3 on the main plane.
A semiconductor integrated circuit device having a thickness of not less than 50 nm and not more than 50 nm. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the refractory metal film is made of tungsten or molybdenum. 4. The semiconductor integrated circuit device according to claim 1, wherein the refractory metal film has a wiring thin film made of a material different from that of the refractory metal laminated thereon. A characteristic semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1 or 2, wherein the wiring thin film is selected from the group consisting of aluminum or a group IV element, copper, a noble metal element and a refractory metal element in aluminum. A semiconductor integrated circuit device comprising an aluminum alloy to which at least one element is added. 6. A diameter of 0.5 provided on a semiconductor substrate.
Halogenated refractory metal element on micropores having a depth / diameter ratio of 1 or more and fine grooves having a minimum width of 0.5 μm or less and a depth / minimum ratio of 1 or more 2. The high melting point of the semiconductor integrated circuit device according to claim 1, wherein the chemical vapor deposition method using silane and difluorosilane is used and the ratio of the halide of the refractory metal element and difluorosilane used during the growth is changed. A method of manufacturing a semiconductor integrated circuit device, comprising forming a metal film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the halide of the refractory metal element is:
A method of manufacturing a semiconductor integrated circuit device, which is a halide of tungsten or molybdenum. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6 or 7, wherein the chemical vapor deposition method is performed within a substrate temperature range of 200 ° C to 400 ° C. Manufacturing method. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the refractory metal film formed on the main surface is dry-etched after the refractory metal film is formed. Then, the method of manufacturing a semiconductor integrated circuit device, characterized in that the refractory metal film is left only in the fine holes or the fine grooves.