JPH0637618A - Solid-state element relay - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a solid-state element relay that improves switching delay when turned off and is not affected by switching noise generated by turning on and off a MOS transistor. [Configuration] M for turning on / off by an electromotive force generated in a photodiode array (PDA) to generate an output signal
In a solid-state element relay including an OS transistor (20), a collector is connected to a gate of the MOS transistor (20) and an anode side of the photodiode array (PDA), and an emitter is the MOS transistor (20). And an NPN transistor (31) connected to the cathode side of the photodiode array (PDA) via a diode (30).
1) is integrated with the above photodiode array (PDA) into a chip.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state element relay operated by an optical signal, and more particularly to a solid-state element relay having improved switching delay caused by the gate-source capacitance of a MOS transistor.

[0002]

2. Description of the Related Art Conventionally, a circuit shown in FIG. 5 is known as a solid-state element relay operated by an optical signal. This solid-state element relay receives a switching signal Ii at an input terminal T1.
1, the light emitting diode LED is made to emit light by adding to T12, and the light signal from this light emitting diode LED is received by the photodiode array PDA constituted by connecting a plurality of photodiodes in series, and is generated in this photodiode array PDA. By applying an electromotive force to the MOS transistor 20, the MOS transistor 20 is turned on and the output signal IO is output from the output terminals T21 and T22. Here, a part surrounded by a dotted line shows a part integrated into one chip.

However, in this solid-state element relay, due to the gate-source capacitance of the MOS transistor 20, a switching delay occurs when the solid-state element relay changes from on to off.

Therefore, in order to solve this problem, a circuit as disclosed in, for example, JP-A-60-170322 has been proposed. In this circuit, as shown in FIG. 6, a circuit including a diode 10, a PNP transistor 11 and a resistor 12 is inserted between a photodiode array PDA and a MOS transistor 20 to form a MOS transistor 20.
By increasing the discharge speed of the gate-source capacitance of, the switching delay when the solid-state relay changes from on to off is improved.

[0005]

However, in the conventional solid-state relay shown in FIG. 6, the diode 10 and the PNP transistor 11 are integrated into a chip with the MOS transistor 20 as surrounded by the dotted line in FIG. Because MO
There is a drawback that the operation becomes unstable due to the influence of switching noise generated by turning on and off the S transistor 20.

Therefore, an object of the present invention is to provide a solid-state element relay that improves switching delay when off and is not affected by switching noise generated by turning on and off a MOS transistor.

[0007]

In order to achieve the above object, the present invention provides a light emitting element driven by a switching signal, a photodiode array arranged to face the light emitting element, and the photodiode array. In a solid-state element relay comprising: a MOS transistor that is turned on / off by an electromotive force generated in the output transistor to generate an output signal; and a collector connected to the gate of the MOS transistor and connected to an anode side of the photodiode array. And an emitter connected to the source of the MOS transistor and connected to the cathode side of the photodiode array through a diode.
A transistor is provided, and the NPN transistor is integrated with the photodiode array into a chip.

[0008]

Function: Between the gate and source of the MOS transistor, h
By inserting an NPN transistor with a high parameter hFE, the discharge speed of the gate-source capacitance of the MOS transistor is increased, and by integrating this NPN transistor with the photodiode array into a chip, M
Avoid the influence of switching noise of OS transistors.

[0009]

Embodiments of the solid-state relay according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an embodiment of a solid-state element relay according to the present invention. In addition, in FIG.
For convenience of explanation, the same reference numerals are given to portions common to the conventional circuits shown in FIGS.

In the embodiment shown in FIG. 1, an NPN transistor 31 having a high h parameter hFE is used.
The collector of the N transistor 31 is connected to the MOS transistor 2
0 is connected to the gate of the photodiode array PDA on the anode side, the emitter is connected to the source of the MOS transistor 20, and the diode 30 is connected.
Is connected to the cathode side of the photodiode array PDA. The base of the NPN transistor 31 is connected to the cathode side of the photodiode array PDA, and the bias resistor 32 is provided between the collector and the base of the NPN transistor 31.

Further, as surrounded by a dotted line in FIG.
The transistor 31 is integrated with the photodiode 30 and the bias resistor 32 into a chip with the photodiode array PDA.

When the solid-state element relay having such a structure is turned on, that is, when the photodiode array PDA is irradiated with an optical signal, and when it is turned off, that is, when the photodiode array PDA is not irradiated with an optical signal, respectively. The operation of the circuit shown in FIG. 1 in FIG. 2 is shown in FIG. 2 and FIG.

That is, FIG. 2 shows an equalizing circuit of the circuit shown in FIG. 1 when the photodiode array PDA is irradiated with an optical signal. In this case, as shown in FIG. The PDA has a certain electromotive force,
For example, if the electromotive force of each photodiode constituting the photodiode array PDA is 0.5 (V) and the number of photodiodes is n, Vn = 0.5 × n
An electromotive force of (V) is generated. Therefore, this photodiode array PDA can be represented by a constant current source SI. The capacitor C1 represents the gate-source capacitance of the MOS transistor 20.

In this case, assuming that the current generated from the constant current source SI is IF and the current flowing through the resistor 32 is I1, the current I2 flowing into the capacitor C1 is I2 = IF-I1, and the diode 30 is forwarded. Since the current flows in the direction, the base-emitter voltage of the NPN transistor 31 is in the opposite direction, and the NPN transistor 31 does not operate. Therefore, in this case, the gate-source capacitance of the MOS transistor 20, that is, the capacitor C1 is charged by the current I2. The state of charging the capacitor C1 in this case is shown in a graph of FIG. That is, the capacitor C
1 is charged by the current I2, is saturated soon, and is in a parallel state with an electromotive force generated in the photodiode array PDA, that is, Vn = 0.5.times.n (V).

Further, FIG. 3 shows a photodiode array P.
1 shows an equalization circuit of the circuit shown in FIG. 1 when an optical signal is not applied to DA. In this case, the base of NPN transistor 31 is charged through capacitor C1 via resistor 31. The current I3 is supplied, the NPN transistor 31 enters the operating state, and the current I4 flows through the collector of the NPN transistor 31.

That is, the gate-source capacitance of the MOS transistor 20, that is, the discharge current I of the capacitor C1.
5 becomes I5 = I3 + I4 = I3 + hFE.multidot.I3 = (1 + hFE) .multidot.I3, and it can be seen that the h parameter hFE has a great influence on the discharge current of the gate-source capacitance of the MOS transistor 20.

Here, in this embodiment, since the NPN transistor 31 having a high h parameter hFE is used, the gate-source capacitance of the MOS transistor 20 is significantly larger than that of the conventional circuit using the PNP transistor. Can be discharged at high speed, and the switching delay when the solid-state element relay is off can be greatly improved.

Further, in this embodiment, the NPN transistor 31 includes a diode 30 and a bias resistor 3.
In addition, since it is integrated with the photodiode array PDA into a chip and is formed separately from the MOS transistor 20, it is not affected by switching noise generated when the MOS transistor 20 is turned on and off.

[0020]

As described above, according to the present invention,
An NPN transistor with a high h parameter hFE is used in the discharge circuit that discharges the gate-source capacitance of the MOS transistor, and this NPN transistor is integrated with the photodiode array into a chip. 1) Switching delay when the solid-state relay is off Can be greatly improved.

2) It is possible to prevent the influence of switching noise generated by turning on and off the MOS transistor. And so on.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a solid-state element relay according to the present invention.

FIG. 2 is an equalization circuit for explaining the operation of the solid-state element relay according to the present invention when it is turned on.

FIG. 3 is an equalization circuit for explaining the operation of the solid-state element relay according to the present invention when it is off.

FIG. 4 is a graph showing charge characteristics of gate-source capacitance of a MOS transistor.

FIG. 5 is a circuit diagram showing a conventional example of a solid-state element relay.

FIG. 6 is a circuit diagram showing another conventional example of a solid-state element relay.

[Explanation of symbols]

LED light emitting diode PDA photodiode array 10 diode 11 PNP transistor 12 bias resistor 20 MOS transistor 30 diode 31 NPN transistor 32 bias resistor SI constant current source C1 capacitor (gate-source capacitance of MOS transistor) T11, T12 input terminal T21, T22 Output terminal

Claims (1)

[Claims] 1. A light emitting element driven by a switching signal, a photodiode array arranged to face the light emitting element, and an output signal which is turned on and off by an electromotive force generated in the photodiode array. A solid-state element relay comprising: a MOS transistor for generating; a collector connected to a gate of the MOS transistor and an anode side of the photodiode array; an emitter connected to a source of the MOS transistor and a diode; A solid-state relay in which an NPN transistor connected to the cathode side of the photodiode array via the above is provided, and the NPN transistor is integrated with the photodiode array into a chip.