JPH0644241B2 - Single-chip micro computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention generally relates to a single-chip microcomputer (hereinafter referred to as a microcomputer) having a built-in read-only memory (hereinafter referred to as ROM) which can be arbitrarily programmed by a user.
The present invention relates to a test circuit for reading the ROM.

[Conventional technology]

Generally, a microcomputer having a built-in ROM has various test modes for detecting defects that occur during the manufacturing process and the assembling process, and all functions inside the microcomputer are tested. One of the test modes is a ROM verify mode for testing the built-in ROM. FIG. 3 is an example of a conventional functional block in this mode. The signal RD given from the outside serves as a signal for reading the ROM and also as an increment signal for the program counter 10. This signal RD from the external terminal by LSI tester etc.
Each time you enter, the program counter 10 in the built-in ROM
Are sequentially incremented. The output signal of the program counter 10 is input to the address decoder 20, and the output data of the ROM 30 selected by the address decoder 20 is RO.
Output port latch defined through M output register 40
It is output to 50 and is output to the external terminal P. RO in Figure 4
9 shows a timing chart in the M-verify mode. Reference numeral 10 is an address of the built-in ROM pointed to by the program counter, which is sequentially incremented by a built-in ROM read signal RD given from the outside. 40 is a read signal RD
Shows the data latched by the ROM output register. TP is an expected value prepared in the LSI tester, and the internal ROM data P read to the port by the read signal RD and the expected value TP output from the tester are compared at the position of the determination strobe signal ST. PTN represents the number of patterns required by the LSI tester during the program memory read test.

[Problems to be solved by the invention]

In the conventional method described above, it is necessary to prepare an expected output pattern of the LSI tester for each address in order to compare with the ROM output data output from the output port in synchronization with the ROM read signal given by the LSI tester. ,
There is a drawback that the capacity of the pattern memory of the LSI tester and the test time increase as the capacity of the ROM increases.

[Means for solving problems]

A microcomputer according to the present invention stores a program memory, a program counter, a decoder for decoding the contents of the program counter to specify a predetermined address of the program memory, and an address of the program memory specified by the decoder. Means for outputting information on the bus, and a plurality of output ports for receiving and outputting the information on the bus in response to the corresponding read signals, and the verify designation signal. In response to, sequentially updating the contents of the program counter, and in response to a part of the decode output of the decoder, sequentially generates a read signal to the plurality of output ports,
As a result, the information output from the program memory at the time of program verification is sequentially captured and output to the plurality of output ports.

〔Example〕

 Next, the present invention will be described with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing an embodiment according to the present invention, which includes a program counter 10, an X decoder 21 and a Y selector.
22, Z selector 23, built-in ROM 30, MOSFET groups 61, 62, MO
SFET 63, 64, ROM output register 40, data bus 80, output port A latch 51 consisting of terminals P _{A0 to} P _A7 , terminal P
_{It is} composed of an output port B latch 52 composed of _{B0 to} P _B7 and AND gate circuits 71 and 72. The configurations of blocks 101 to 107 are similar to the configuration of block 100. First, by supplying power and input signal to the external terminal of the microcomputer by the LSI tester and setting the microcomputer to the internal ROM verify mode,
The built-in ROM verify mode signal M is set, the program counter 10 is reset, and the built-in ROM 30
Indicates the address 0 of. After that, R input from the outside
The value of the program counter is incremented by the OM read signal RD, and the address of the built-in ROM 30 is sequentially increased. Assuming that the capacity of the built-in ROM 30 is 8 k bits, 13 bits (A _{12 to} A ₀ ) are required as a ROM address. Of these, the upper 8 bits (A _{12 to} A ₅ ) are decoded by the X decoder 21 and one of the 256 word lines is selected. One of the 32 output lines (bit lines) of the ROM 30 receives the lower 5 bits (A _{4 to} A ₀ ) of the address as an input, the Y selector 22 and the Z selector 23.
Is selected by the decode signal of. In this way
The ROM output accessed by the 13-bit address is stored in the ROM output register 40. Block 101
.About.107 also perform the same operation, and 8-bit data is output onto the data bus 80 by the read signal RD. The operation up to this point is the same as the operation in the ROM verify mode in the conventional microcomputer, but in the microcomputer having the function of selecting the output port according to the present invention, the ROM output data stored in the ROM output register 40 is the Z selector.
23 output signals, that is, the least significant bit A _{0 of the} ROM address
Latch of output port A by decode outputs Z ₁ and Z ₀ of
51 or the latch 52 of the output port B. Figure 2 shows
The timing chart in the ROM verify mode in FIG. 1 shows the block 100.
When the built-in ROM verify mode signal M is set and the program counter 10 is reset to point to address 0, R
The ROM data output at address 0 read to the ROM output register 40 by the OM read signal RD is the Z selector 23.
Since the output Z ₁ thereof is active, it is transferred to the output port A latch 51 by the read signal _RA of the port A latch and output to the output terminal P _A0 . Next, when the output Z ₀ of the Z selector will ROM address 1 address a ROM read signal RD is activated, ROM data of one address which is read is output port B by reading signals R _B of the port latch B latch 52 To the output terminal P _B0
Is output to. These operations are performed by other blocks (101-10
The same is done for 7), and the ROM with even addresses
Data (8 bits) goes to the P _{A7 to} P _A0 terminals of port A, and ROM data (8 bits) at odd addresses goes to the port B P
It is distributed and output to the _{B7 to} P _B0 terminals. At this time, the LSI tester outputs the ROM output data P _A0 and P _B0 (the least significant 1-bit data is shown in FIG. 2) distributed to each output port at the position of the determination strobe ST in the figure, and By comparing the judgment expected values (expected value TP _A of port _A and expected value TP _{B of} port B) in the memory, it is possible to realize a test pattern that used to require two patterns with one pattern, which is necessary for a tester. It only takes half the memory address.

In this example, the ROM output is distributed to the two output ports by using the decode signal of the least significant 1 bit of the address, but by decoding the arbitrary multiple bits of the address and using that signal, the output built into the microcomputer is output. It is obvious that the ROM output can be distributed according to the number of ports.

〔The invention's effect〕

As described above, according to the present invention, it is possible to significantly reduce the number of test patterns of the LSI tester used for the verify check of the ROM incorporated in the microcomputer.
It has the effect of improving the tester usage efficiency and reducing the test time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a ROM read circuit incorporated in a microcomputer according to the present invention, FIG. 2 is a timing chart for explaining the functional blocks of FIG. 1, and FIG. 3 is a ROM incorporated in a conventional microcomputer. A functional block diagram of the read circuit, and FIG. 4 is a timing chart for explaining FIG. (Explanation of symbols) 10 ... Program counter, 20 ... ROM address decoder, 21 ... X decoder, 22 ... Y selector, 23 ... Z
Selector, 30 …… ROM, 40 …… ROM output register,
50 ... Output port latch, 51 ... Output port A latch, 52 ... Output port B latch, 61, 62 ... MOSF
ET group, 63, 64 ... MOSFET, 71, 72 ... AND gate circuit, 80 ... Data bus, RD ... ROM read signal, M ... Built-in ROM verify mode signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-57-60447 (JP, A) JP-A-58-35661 (JP, A) JP-A-60-211561 (JP, A) JP-A-60- 189047 (JP, A) JP 58-220298 (JP, A) JP 54-98546 (JP, A) JP 62-145438 (JP, A)

Claims (1)

[Claims] 1. A program memory, a program counter, a decoder which decodes the contents of the program counter to specify a predetermined address of the program memory, and a decoder which is stored at an address of the program memory specified by the decoder. In a single-chip microcomputer provided with means for outputting information to a bus and a plurality of output ports for receiving and outputting information on the bus in response to respective corresponding read signals, a verify designation signal Means for sequentially updating the contents of the program counter in response to, and means for sequentially generating read signals to the plurality of output ports in response to a part of the decode output of the decoder. The information output from the program memory is Single-chip microcomputer for causing sequentially read to output a plurality of output ports.