JPH0645613A - Semiconductor element and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor element wherein the area occupied by the element inside the plane of a substrate is small and to provide its manufacturing method. CONSTITUTION:In a semiconductor element and its manufacturing method, a drain electrode 8 and a source electrode 9 are formed respectively of conductor layers 3, 7 at the tip part and the root part of a pillar-shaped crystal 2 formed in a semiconductor substrate 1 and, in addition, a gate electrode 10 is formed, by using the layerlike structure of a semiconductor layer 5 and of insulator layers 4, 6, between the conductor layers 3, 7 and in a prescribed region on the side face of the pillar-shaped crystal 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element, particularly a semiconductor element in a fine structure element, and a method for manufacturing the same.

[0002]

2. Description of the Related Art LSIs have been highly integrated by introducing planar IC technology, photolithography technology, ion implantation technology, etc. since the invention of the transistor and further developing them. The conventional methods of highly integrating LSIs have been realized mainly by proportionally reducing the size of the elements formed on the semiconductor surface.

[0003]

However, the above method has a problem in further increasing the degree of integration in the future. For example, in the manufacture of MOSFET,
When miniaturized using the proportional reduction rule, the contact resistance and voltage drop between the device and each electrode are 2
Since it is inversely proportional to the power of 1 and the power of 1, the size of the electrode on the semiconductor surface is limited by miniaturization, and the size of the element on the plane of the substrate is determined by the electrode size. Further, since the source, gate and drain regions are provided in the semiconductor substrate surface, there is a problem that the area occupied by the MOSFET is large. Such a problem is a junction type FET, MESF
The same is true for ET.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device having a small area occupied by the device in the plane of the substrate and a method of manufacturing the same.

[0005]

According to a first aspect of the present invention, there is provided at least a first semiconductor made of columnar crystals provided on the surface of a semiconductor substrate and a predetermined side surface between a tip portion and a root portion of the first semiconductor. A first semiconductor provided in contact with or embedded in the region and a second semiconductor having a different conductivity type,
The second semiconductor is a semiconductor element in which a gate electrode is provided, and a source electrode and a drain electrode or a drain electrode and a source electrode are provided at a tip portion and a root portion of the first semiconductor.

According to a second aspect of the present invention, there is provided a first semiconductor comprising a columnar crystal provided on the surface of a semiconductor substrate, and a first semiconductor.
An insulator layer provided in contact with or embedded in a predetermined region on the side surface between the tip portion and the root portion of the semiconductor, and a conductor portion formed on the insulator layer. This is a semiconductor element in which a source electrode and a drain electrode or a drain electrode and a source electrode are provided at the tip portion and the root portion of the gate electrode and the first semiconductor.

According to a third aspect of the present invention, there is provided a first semiconductor, which is a columnar crystal provided at least on the surface of a semiconductor substrate, and a first semiconductor.
The semiconductor device includes a first semiconductor and a metal portion that forms a Schottky barrier and is provided in contact with or embedded in a predetermined region on the side surface between the tip portion and the root portion of the semiconductor. This is a semiconductor element in which a source electrode and a drain electrode or a drain electrode and a source electrode are provided at the tip and the root of the semiconductor.

According to the present invention of claim 5, the metal is locally deposited on the surface of the semiconductor substrate, and then the temperature of the surface of the semiconductor substrate is set to be equal to or higher than the eutectic point temperature of the metal and the substrate material and lower than the respective melting points. Of the semiconductor device in which a columnar crystal is locally grown on the surface of the semiconductor substrate by forming a local alloy droplet region at a metal deposition site on the surface of the semiconductor substrate and using a gas-liquid-solid reaction. It is a manufacturing method.

According to a twelfth aspect of the present invention, a multi-layer film comprising a first conductive layer, an insulating layer, a second semiconductor, an insulating layer and a second conductive layer is further formed on the surface of the semiconductor substrate, the first conductive layer, 6. The method of manufacturing a semiconductor element according to claim 5, wherein the two conductive layers are deposited such that they are electrically connected to the root portion and the tip portion of the columnar crystal, respectively, and the semiconductor layer is in contact with a predetermined region of the columnar crystal to be electrically conductive. .

Further, for example, a columnar crystal is locally grown on the surface of a semiconductor substrate, and thereafter, a semiconductor or a columnar crystal having a conductivity type different from that of the columnar crystal is brought into contact with a predetermined region on the side surface of the columnar crystal by a predetermined method. And forming a metal that forms a Schottky barrier, or embedding a semiconductor having a conductivity type different from that of the columnar crystal, or forming an insulator layer and a conductor on the insulator layer, and further forming a columnar crystal. This is a method of manufacturing a semiconductor element, in which electrodes are formed on the tip portion and the root portion by a conductor.

[0011]

According to the present invention, a semiconductor having a conductivity type different from that of the columnar crystal is formed so as to be in contact with or embedded in a predetermined region on the side surface between the tip portion and the root portion of the fine semiconductor columnar crystal provided on the substrate. The gate electrode is the semiconductor portion, and the source electrode and the drain electrode or the drain electrode and the source electrode are provided at the tip portion and the root portion, so that the source-gate-drain region is arranged in the height direction with respect to the substrate. Further, a semiconductor element can be realized in which electrodes can be formed and the occupied area is small. Here, for example, a depletion layer is formed immediately below the gate electrode, and the width of the depletion layer changes depending on the voltage applied to the gate electrode. Therefore, the current flowing between the source and drain is controlled by the voltage applied to this gate electrode. It is possible.

Further, the insulating layer and the insulating layer are formed so as to be in contact with or embedded in a predetermined region on the side surface between the tip portion and the root portion of the fine semiconductor columnar crystal provided on the substrate. The conductor portion is used as a gate electrode, and the tip portion and the root portion are provided with a source electrode and a drain electrode or a drain electrode and a source electrode. A gate-drain region and an electrode can be formed, and a semiconductor element having a small occupied area can be realized. Here, for example, in the interface between the columnar crystal immediately below the gate electrode and the insulator layer, a channel region that changes depending on the voltage applied to the gate electrode is formed, and the current flowing between the source and the drain is the voltage applied to this gate electrode. It is possible to control by.

Further, the semiconductor forming the columnar crystal and the Schottky so as to be in contact with or embedded in a predetermined region on the side surface between the tip portion and the root portion of the fine semiconductor columnar crystal provided on the substrate. The metal part that forms the barrier is formed, and the metal part is used as the gate electrode, and the source electrode and the drain electrode or the drain electrode and the source electrode are provided at the tip part and the root part. -A gate-drain region and an electrode can be formed, and a semiconductor element having a small occupied area can be realized. Here, for example, a depletion layer is formed due to the Schottky barrier at the interface of the columnar crystals just below the gate electrode. Since the width of the depletion layer changes depending on the voltage applied to the gate electrode, the current flowing between the source and the drain can be controlled by the voltage applied to the gate electrode.

Further, the metal is a material exhibiting eutectic phase equilibrium with the substrate material, and its eutectic point temperature is lower than the melting points of the metal and the semiconductor substrate material. By heating below, the substrate material and the metal are locally alloyed and melted only at the place where the metal is deposited, that is, an alloy droplet region is formed.

Next, a so-called gas phase-liquid phase-solid phase reaction is caused to occur on the substrate on which the alloy droplet regions have been formed. Specifically, for example, the following actions occur. That is, a gas of a predetermined pressure composed of a halide, an organometallic compound, or a hydride containing at least the constituent element of the substrate or a predetermined element on the substrate is decomposed directly or by using heat or electromagnetic waves or other energy. And then exposed to the substrate surface. The gas atoms are taken into the droplets, and then the atoms diffuse in the droplets and reach the interface with the base substrate to be deposited. That is, columnar crystals can be epitaxially grown in a local region on the semiconductor substrate.

Further, a multi-layered film composed of a first conductive layer, an insulating layer, a second semiconductor, an insulating layer, and a second conductive layer is further formed on the surface of the semiconductor substrate, and the first conductive layer and the second conductive layer are respectively columnar. By depositing so as to conduct to the root portion and the tip portion of the crystal so that the semiconductor layer is in contact with a predetermined region of the columnar crystal and conducts, the second semiconductor layer causes the gate electrode to further form the first conductive layer and the gate electrode on the columnar crystal. With the second conductive layer, the source electrode and the drain electrode or the drain electrode and the source electrode can be formed into columnar crystals.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.

Example 1 A semiconductor device of Example 1 of the present invention is shown below. FIG. 1 is a sectional view of the semiconductor device of this embodiment. (11 of the P-type silicon single crystal semiconductor substrate 1 having a resistivity of about 1 kΩcm or less doped with boron
1) A columnar crystal 2 of P-type silicon having a diameter of 100 nm and a length of 3 μm is formed on the surface, a conductive layer 3 of P-type silicon having a thickness of 200 nm, an insulating layer 4 of SiO _{2 having} a thickness of 50 nm, a thickness of 1 μm thick N-type silicon semiconductor layer 5, thickness 50
An SiO ₂ insulator layer 6 having a thickness of 200 nm and a P-type silicon conductor layer 7 having a thickness of 200 nm are formed on the insulator layer 6 and in contact with the side surfaces of the columnar crystals 2. Then, the thin gold wire was brought into contact with the conductor layers 3 and 7 and the semiconductor layer 5 to take out the drain electrode 8, the source electrode 9, and the gate electrode 10. It was possible to obtain good characteristics of a junction FET in which a voltage is applied between the source and drain of this semiconductor element and the drain current is controlled by the voltage applied to the gate electrode 10.
Further, the occupied area of the substrate can be made very small as compared with the conventional junction type FET manufactured by using the planar technique on the surface of the semiconductor substrate. Further, a semiconductor having the same conductivity type as the columnar crystal 2 and having a higher impurity concentration than that of the columnar crystal 2 is used for the conductor layers 3 and 7 forming the source and drain, and the columnar crystal 2 and the conductive layer are formed in the semiconductor layer 5 forming the gate. The characteristics of the device were improved by using a semiconductor having a different type and an impurity concentration higher than that of the columnar crystal 2.

In the first embodiment, the semiconductor layer 5 is formed so as to be in contact with the side surface of the columnar crystal 2, but the contact position,
The shape and size are not limited.

The same effect was obtained by embedding the N-type region in the columnar crystal 2.

Although SiO ₂ is used as the insulating layers 4 and 6, the material is not limited.

Further, although the electrodes are taken out by using a fine gold wire, it is possible to use a conductor capable of forming a good ohmic contact with the conductor layers 3 and 7 forming the source and drain and the semiconductor layer 5 forming the gate. I wish I had it.

Although P-type silicon is used for the conductor layers 3 and 7, any conductor may be used as long as it does not form a Schottky barrier with the columnar crystal 2. (Second Embodiment) A semiconductor device according to the second embodiment of the present invention will be described below. FIG. 2 is a sectional view of the semiconductor device of this embodiment.
On the (111) plane of the N-type silicon single crystal semiconductor substrate 11 having a resistivity of about 1 kΩcm or less doped with phosphorus,
A columnar crystal 12 of N-type silicon having a diameter of 100 nm and a length of 3 μm is formed, and a conductor layer 13 of P-type silicon having a thickness of 200 nm and an insulator layer 14 of SiO _{2 having} a thickness of 50 nm are formed on the semiconductor substrate 11 and the columnar crystal. It is formed so as to be in contact with the side surface of 12. The columnar crystal 12 exposed above the insulator layer 14
An insulating layer 15 of SiO _{2 having} a thickness of 50 nm is formed on the side surface of the substrate by thermal oxidation. Furthermore, on the insulator layer 14, a thickness of 1
A μm polysilicon conductor layer 16 is formed. An insulator layer 17 of SiO ₂ is formed to a thickness of 200 nm on the conductor layer 16, the insulator layer 15 exposed above the insulator layer 17 is removed by reactive ion etching, and then a conductor of P-type silicon is formed. Layer 18 on insulator layer 17
The thickness of 200 nm is formed so as to be in contact with the side surface of 2.

Subsequently, the thin gold wires are connected to the conductor layers 13, 16 and
18 in contact with the drain electrode 19, the gate electrode 20,
The source electrode 21 was taken out. A MISFET in which a voltage is applied between the source and the drain of this semiconductor element, and the drain current is controlled by the voltage applied to the gate electrode 20.
It was possible to obtain good characteristics of. In addition, a MISF formed on the surface of a conventional semiconductor substrate by using a planar technique.
The area occupied by the substrate can be made very small as compared with ET.

Further, by using a semiconductor having a conductivity type different from that of the columnar crystal 12 for the conductor layers 13 and 18 forming the source and drain and having an impurity concentration higher than that of the columnar crystal 12, the device characteristics are improved.

In the second embodiment, the insulator layer 15 and the conductor layer 16 are formed in the columnar crystal 12 in the shape of a band having a width of 1 μm, but the contact position, shape and size are not limited.

Further, S is used as the insulator layers 14, 15 and 17.
Although iO ₂ is used and polysilicon is used as the conductor layer 16, the material is not limited.

Further, although the electrodes are taken out by using the fine gold wire, any conductor can be used as long as it can form a good ohmic contact with the conductor layers 13, 16 and 18 forming the source, drain and gate.

Although P-type silicon is used for the conductor layers 13 and 18, a metal which does not form the Schottky barrier with the columnar crystal 12 may be used. (Embodiment 3) A semiconductor device according to a third embodiment of the present invention will be described below. FIG. 3 is a cross-sectional view of the semiconductor device of this example.
P-type G doped with zinc and having a specific resistance of about 1 kΩcm or less
On the (111) surface of the aAs single crystal semiconductor substrate 22,
A P-type GaAs columnar crystal 23 having a diameter of 100 nm and a length of 3 μm is formed, a P-type GaAs conductor layer 24 having a thickness of 200 nm, a SiO ₂ insulating layer 25 having a thickness of 50 nm, and a columnar crystal 23 having a thickness of 1 μm. And an Al metal layer 26 forming a Schottky barrier, a 50 nm thick SiO ₂ insulator layer 27,
A P-type GaAs conductor layer 28 having a thickness of 200 nm is formed on the semiconductor substrate 22 and in contact with the side surfaces of the columnar crystals 23. Then, the thin gold wire is brought into contact with the conductor layers 24 and 28 and the metal layer 26 to make the drain electrode 29 and the source electrode 3
0, the gate electrode 31 was taken out. A MESFE that applies a voltage between the source and drain of this semiconductor element and controls the drain current by the voltage applied to the gate electrode 31.
Good characteristics of T could be obtained. In addition, a conventional MES formed on the surface of a semiconductor substrate by using a planar technology.
The occupied area of the substrate can be made very small as compared with the FET.

Further, the use of a semiconductor having the same conductivity type as that of the columnar crystals and having a higher impurity concentration than that of the columnar crystals for the conductor layer forming the source and drain improves the device characteristics.

In the third embodiment, the metal layer 26 is formed so as to be in contact with the side surface of the columnar crystal 23, but the contact position, shape and size are not limited.

Although Al is used for the metal layer 26, any metal may be used as long as it forms a good Schottky barrier with the semiconductor forming the columnar crystal 23.

Further, SiO _{2 is used} as the insulating layers 25 and 27.
Was used, but the substance is not limited.

Further, although the electrodes are taken out by using a fine wire of gold, the conductor layers 24 and 2 forming the source and the drain are formed.
8 may be any conductor that can form a good ohmic contact with the conductor.

The conductive layers 24 and 28 are made of P-type GaA.
Although s is used, any conductor that does not form the columnar crystal 23 and the Schottky barrier may be used.

Further, in the above-mentioned Examples 1, 2 and 3, the columnar crystals are columnar, but the minimum width is 100 nm or less and the length is 10 nm.
The same effect was confirmed for columnar crystals of 0 nm or more. Further, in Examples 1, 2, and 3, the semiconductor substrate and the columnar crystal are formed of P-type silicon, N-type silicon, and P-type G, respectively.
Although the semiconductor substrate and the columnar crystals are made of aAs, the conductivity type is P,
Similar effects were obtained with either N.

Further, by making the semiconductor substrate and the columnar crystal have the same conductivity type, the electrode formed at the root of the columnar crystal could be moved to an arbitrary position on the substrate.

Further, the source and drain electrodes operated in the same manner even if the roles of the electrodes were reversed. (Embodiment 4) A method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described below. In a high vacuum chamber, a gold needle having a tip curvature of several 100 nm or less is arranged facing the surface of the substrate. The needle was prepared by electrolytically polishing a gold wire having a diameter of 0.1 to 1 mm in hydrochloric acid. It can also be obtained by mechanical cutting or polishing. Boron-doped resistivity is 1 kΩc
A (111) plane P-type silicon semiconductor substrate having a smooth surface of about m or less was used. It suffices that the specific resistance be equal to or lower than a level at which a tunnel current for observation or processing with a scanning tunneling microscope (hereinafter referred to as STM) flows. First,
The place where gold was desired to be deposited was observed in the STM observation mode, and it was confirmed that the surface was smooth. Then it stops the plane scanning needles, typically applied to V _t = 3~10V about, pulse voltage application time Delta] t = the number 100～50Msec. After that, when this area was observed again,
As shown in (a), a gold protrusion 3 having a diameter of several 100 nm and a height of about 5 nm is provided at a predetermined position in the region of the semiconductor substrate 32.
It was confirmed that 3 was formed. In this embodiment, a pulse voltage with a positive bias on the needle side was applied, but similar results were obtained even if the polarity was changed. Also, similar results were obtained when the work was performed in the atmosphere. This protrusion 33
Is a needle with a distance of nm order depending on the pulse voltage
A high electric field of 10 ⁷ to 10 ⁸ V / cm or more induced between the substrates causes the gold atoms at the tip of the needle to ionize and evaporate, or the temperature at the tip of the needle locally rises and evaporates to confront the substrate. It is thought that it is due to the cause such as being accumulated in. The threshold voltage V _th exists in the pulse voltage applied to form the protrusion 33. In this example, V _th was about 3 to 5V. The applied voltage V _t for processing is suitable within the range in which gold evaporates from the needle side and silicon hardly evaporates from the semiconductor substrate 32 side. Next, a gas phase-liquid phase-solid phase reaction was caused to occur on the semiconductor substrate 32. Specifically, the following work was performed. That is, the semiconductor substrate 32 having the gold protrusions 33 formed thereon was placed in a CVD apparatus, and the substrate temperature was heated to the eutectic point temperature or higher and the melting point of gold or lower in this system. Typically, the temperature is set to about 50 ° C. or higher and 370 ° C. or lower. In this state, as shown in FIG. 4B, the gold protrusion 33 is a droplet 34 in which the silicon substrate and gold are alloyed and melted.

Here, purified hydrogen and S in a predetermined molar ratio are added.
A mixed gas consisting of iCl ₄ and a trace amount of BBr ₃ was introduced.
Then, a reduction reaction supplies silicon and a small amount of boron, and the P-type columnar crystal 3 of the P-type silicon is provided only at the location of the droplet 34.
5 grew in a direction perpendicular to the substrate. Moreover, columnar crystals 35
A droplet 34 remained at the tip of the. Figure 4
It shows in (c).

These growth mechanisms are as follows. That is, the gas of SiCl ₄ and BBr ₃ on the semiconductor substrate 32 is decomposed and exposed to the substrate surface. At that time, the gas atoms collide with the surface of the semiconductor substrate 32 and the droplets 34 in the same number per unit area and unit time, but the proportion of the atoms that agglomerate and contribute to the crystal growth (hereinafter referred to as the matching coefficient) is the same. There are overwhelmingly different growth conditions. That is, on the surface of the solid substrate, if the degree of supersaturation of the exposed gas is low, the temperature of the system is low, or there are few steps or adsorbates that trigger shell formation on the substrate surface, and the crystal surface is highly perfect, The matching coefficient is very small, whereas the liquid surface has microscopically very unevenness and has a high ability to capture atoms, and the matching coefficient is close to 1. Therefore, when this system is placed under the conditions as described above, gas atoms are preferentially taken into the alloy droplet region. Therefore, on the semiconductor substrate 32, silicon and boron are scarcely deposited from the gas phase, whereas the compatibility coefficient of the liquid is close to 1, so that the gold droplet 34 contains silicon and boron from the air. The element was taken in efficiently. The captured atoms diffused in the droplet 34, reached the interface with the underlying semiconductor substrate 32, and were deposited. That is, the silicon crystal was epitaxially grown only in the local region of the base substrate. Here, the segregation coefficient of silicon crystal of the gold and 10 ^-4 or less, the gold in the columnar crystal 35 to be grown is not taken little. Therefore, even if the growth proceeds, the droplet 3
No. 4 remains above the constantly growing columnar crystal 35, and the main growth mechanism is maintained for a long time.

Subsequently, the conductor layer 3 is formed on the semiconductor substrate 32.
A multi-layer film consisting of 6, the insulator layer 37, the semiconductor layer 38, the insulator layer 39, and the conductor layer 40 was prepared. The fourth embodiment
In order to easily take out the electrodes after depositing the multilayer film, tungsten was deposited on each of the conductor layers 36, the semiconductor layers 38, and the conductor layers 40 by an electron beam evaporation method using a mask. The shape of the mask used is shown in FIG.
These masks 41, 42 and 43 were designed so that the range in which tungsten is deposited can be selected, and tungsten is not deposited around the columnar crystal 35. As described above, by depositing tungsten, the electrode could be easily taken out by the reactive ion etching performed after the deposition of the multilayer film.

Specifically, the substrate temperature is 700 ° C. and the thickness is 20 by the CVD method of SiCl ₄ containing a trace amount of BBr _3.
After depositing the 0-nm-thick P-type silicon conductor layer 36, a 200-nm-thick tungsten layer 44 was formed by an electron beam evaporation method using a mask 41.

Next, the substrate temperature is set to 420 by the low temperature CVD method.
PGS (Phosphosilicate glass containing about 10% P ₂ O ₅ in 70 nm thick SiO ₂ at ℃)
cateGlass)) insulator layer 37 is deposited to form insulator layer 3
In order to make 7 dense, the substrate temperature is set to 900 in a nitrogen atmosphere.
Annealing was performed at ℃. Further, after depositing a semiconductor layer 38 of N-type silicon having a thickness of 1 μm by a CVD method of SiCl ₄ containing a small amount of PCl ₃ , a tungsten layer 45 having a thickness of 200 nm is formed by an electron beam evaporation method using a mask 42.
Was formed. Furthermore, the substrate temperature of 42
An insulator layer 39 of PGS having a thickness of 100 nm was deposited at 0 ° C., and annealing was performed at a substrate temperature of 900 ° C. in a nitrogen atmosphere in order to make the insulator layer 39 dense. Further, a 200 nm-thick P-type silicon conductor layer 40 is deposited by a CVD method of SiCl ₄ containing a small amount of BBr _3, and then a 200 nm-thickness is obtained by an electron beam evaporation method using a mask 43.
The tungsten layer 46 was formed. Since the silicon columnar crystal 35 grows perpendicularly to the semiconductor substrate 32, it was deposited from the base and did not adhere to the side surface of the columnar crystal 35 in the deposition process using the CVD method. The state after the completion of this deposition process is shown in FIG. Figure 4 (d)
FIG. 4 is a sectional view including columnar crystals 35.

Next, unnecessary portions were etched by reactive ion etching using a mixed gas of HBr and HCl to expose the tungsten layers 44, 45 and 46 on the surface. A thin wire of gold was welded to the tungsten layers 44, 45 and 46 to take out the drain electrode 47, the gate electrode 48 and the source electrode 49. A schematic diagram of this state is shown in FIG. The completed semiconductor device showed good characteristics of the junction type FET. Further, the occupied area of the substrate can be made very small as compared with the conventional junction type FET manufactured by using the planar technique on the surface of the semiconductor substrate.

Further, a semiconductor having the same conductivity type as the columnar crystal 35 and a higher impurity concentration than that of the columnar crystal 35 is used for the conductor layers 36 and 40 constituting the source and drain, and the columnar crystal is used for the semiconductor layer 38 constituting the gate. The characteristics of the device were improved by using a semiconductor having a conductivity type different from that of No. 35 and having an impurity concentration higher than that of the columnar crystal.

In Example 4, gold was used for the needle, but instead of this, an attempt was made by using a similar manufacturing method using silver. When gold was used, similarly good results were obtained. It was When a predetermined voltage V _t of about several V was applied for a predetermined time Δt, fine silver protrusions could be formed on the silicon substrate. Next, the substrate on which the protrusion is formed is placed in an open-tube CVD apparatus, and the substrate temperature is typically about 50 ° C. or higher and 900 ° C.
When the temperature was set to the following temperature and a mixed gas of purified hydrogen and SiCl ₄ and a small amount of BBr _{3 in} a predetermined molar ratio was introduced thereinto, columnar crystals of P-type silicon were similarly formed when gold droplets were used. It grew in the direction perpendicular to the substrate. In addition to gold and silver, a columnar crystal can be obtained by using a needle such as copper, nickel, and iron to evaporate the constituent metal from the tip to form a protrusion and grow silicon from the local droplet. did it.

Although a small amount of BBr ₃ or PCl ₃ was used as a dopant for SiCl ₄ as a source of silicon for forming columnar crystals, a conductor layer and a semiconductor layer, SiH ₄ and SiHCl ₃ were used as a source of silicon. , SiH ₃
Cl is used, and BCl ₃ , B ₂ H ₆ , and P are used as dopants.
It may be carried out by a hydrogen reduction method using OCl ₃ and PH ₃ .
Further, plasma or ECR may be used to decompose the gas.

Although PSG is used as the insulating layer,
It does not limit the substance.

Although the semiconductor layer 38 is formed so as to be in contact with the side surface of the columnar crystal 35, the contact position, shape and size are not limited.

The same effect was obtained even when the N-type region was buried by annealing the columnar crystal 35.

Further, although the electrodes are taken out by using the tungsten layer, good ohmic contact can be formed with the conductor layer forming the source and drain and the semiconductor layer forming the gate, and in the step of depositing the multilayer film. ,
Any conductor may be used as long as it is a conductor that diffuses into columnar crystals and other semiconductors and has no adverse effect.

Although P-type silicon is used for the conductor layer, metal or polysilicon that does not form a columnar crystal and a Schottky barrier may be used. (Embodiment 5) A method of manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described below. As shown in FIG. 6A, the boron-doped specific resistance was 1 using the same method as in the fourth embodiment.
A columnar crystal 51 was formed on a (111) plane P-type silicon semiconductor substrate 50 having a smooth surface of about kΩcm or less.

Subsequently, FIGS. 6B to 6D and FIG.
As shown in (a) and (b), a multi-layered film composed of a conductor layer 52, an insulator layer 53, a conductor layer 54, an insulator layer 55, and a conductor layer 56 is formed on the surface of the semiconductor substrate 50 by conducting. Body layer 54
A step of producing an insulating layer 57 was performed between the columnar crystals 51. In Example 5, in order to easily take out the electrode after the above steps, the electron beam evaporation method using a mask was performed after depositing the conductor layers 52, 54, 56 and after depositing the insulator layer 55. Tungsten was deposited on each layer by. The mask used is the same as that used in Example 4.

Specifically, a mask 41 was used after depositing a 200 nm-thick P-type silicon conductor layer 52 by a pyrolysis CVD method of SiH ₄ containing a slight amount of BBr ₃ at a substrate temperature of 700 ° C. 200 nm thick by electron beam evaporation method
A tungsten layer 58 was formed. Next, an insulator layer 53 of PGS containing about 10% P ₂ O ₅ in SiO ₂ having a thickness of 70 nm is deposited at a substrate temperature of 420 ° C. by a low temperature CVD method, and the insulator layer 53 is placed in a nitrogen atmosphere. , Substrate temperature 900 ℃
Was annealed. This state is shown in FIG. Subsequently, the columnar crystals 5 were formed at a substrate temperature of 1000 ° C. in dry oxygen.
An insulating layer 57 of SiO ₂ having a thickness of 50 nm was formed on the surface of No. 1. This state is shown in FIG. Further, using a mask 42, an electron beam evaporation method was performed to form an A film having a thickness of 1 μm.
After depositing 1 l of the conductor layer 54, a tungsten layer 59 having a thickness of 200 nm was further formed. Next, the mask 42 is removed, and an insulator layer 55 of PGS containing about 10% P ₂ O ₅ in SiO ₂ having a thickness of 50 nm is deposited at a substrate temperature of 420 ° C. by a low temperature CVD method. Was annealed. Further, the tungsten layer 60 was formed by the electron beam evaporation method using the mask 43. This state is shown in FIG.
It shows in (d). Next, the insulating layer 57 formed on the side surface of the columnar crystal 51 was removed by reactive ion etching using a mixed gas of HBr and HCl. In the reactive ion etching, the lengthwise direction of the columnar crystal 51 was made substantially perpendicular to the ion advancing direction, and the columnar crystal 51 was further rotated, whereby only the target region could be etched. This state is shown in FIG. Furthermore, a small amount of B
The thickness of SiH ₄ containing Br ₃ was reduced to 2 by the thermal decomposition CVD method.
After depositing a 00 nm P-type silicon conductor layer 56, a 200 nm thick tungsten layer 61 was formed by an electron beam evaporation method using the mask 43. This state is shown in FIG.
Shown in. The silicon columnar crystals 51 are the semiconductor substrate 5
Since it grows perpendicularly to 0, in the deposition process using the CVD method, it was deposited from the base and did not adhere to the side surface of the columnar crystal 51. Next, unnecessary regions were removed by reactive ion etching using a mixed gas of HBr and HCl to expose the tungsten layers 58, 59, 61 on the surface. A fine wire of gold is welded to the tungsten layers 58, 59, 61 to form a drain electrode 62, a gate electrode 63, and a source electrode 6.
4 was taken out. This state is shown in FIG.

The completed semiconductor device showed good characteristics of MISFET. Further, the occupied area of the substrate can be made extremely small as compared with the conventional MISFET formed on the surface of the semiconductor substrate by using the planar technique.

Further, the semiconductor layers 52 and 56 forming the source and drain are made of a semiconductor whose conductivity type is different from that of the columnar crystal 51 and whose impurity concentration is higher than that of the columnar crystal 51, so that the device characteristics are improved.

In the fifth embodiment, S is used as a silicon supply source for forming the columnar crystals 51 and the conductor layers 52 and 56.
Although iH ₄ was used as a dopant and a small amount of BBr ₃ was used, the sources of silicon were SiCl ₄ , SiHCl ₃ , and Si.
A hydrogen reduction method using H ₃ Cl and BCl ₃ and B ₂ H ₆ as dopants may be used. Further, plasma or ECR may be used to decompose the gas.

Further, P is used as the insulator layers 53, 55 and 57.
SG or SiO ₂ was used, but the material is not limited.

Further, although the insulator layer 57 and the conductor layer 54 are formed so as to be in contact with the side surfaces of the columnar crystals 51, the contact position, shape and size are not limited.

Further, although the electrodes are taken out by using the tungsten layers 58, 59, 61, a good ohmic contact can be formed with the conductor layer forming the source and drain and the semiconductor layer forming the gate, and the multilayer film is formed. In the step of depositing, columnar crystals 51 and other conductor layers 5
Any conductor may be used as long as it is diffused in 2, 54 and 56 and does not have an adverse effect.

Although P-type silicon is used for the conductor layers 52 and 56, metal or polysilicon that does not form a Schottky barrier with the columnar crystal 51 may be used.

(Sixth Embodiment) A sixth embodiment of the present invention will be described below. The surface is a smooth (111) surface with a specific resistance of 1 kΩ.
Doped P-type GaAs having a size of about cm or less was used as a semiconductor substrate. In the same manner as in the fourth embodiment, a needle made of gold was confronted with the GaAs substrate in a high vacuum and a predetermined pulse voltage was applied. As shown in FIG.
A fine gold protrusion 66 having a height of m and a height of about 5 nm was formed on the GaAs substrate 65. In Example 6, a pulse voltage with a positive bias on the needle side was applied, but similar results were obtained even when the polarity was changed. Also, similar results were obtained when the work was performed in the atmosphere. Next, the semiconductor substrate 65 on which the protrusions 66 are formed is installed in a MOCVD apparatus, and the substrate temperature is set to approximately 100 ° C. or higher and 550 by external high frequency heating.
The temperature is set to ℃ or less, and a mixed gas containing a small amount of diethylzinc as a dopant is introduced into trimethylgallium of a predetermined molar ratio and arsine diluted with hydrogen at a predetermined pressure, as shown in FIG. 8 (b). So that the diameter is 100n
A columnar crystal 67 of m-type and 5 μm-high p-GaAs was grown in a direction perpendicular to the substrate. The grown crystal was a good quality single crystal. Particularly at a growth temperature of 500 ° C. or lower, good selective growth results were obtained. Then, as shown in FIG. 8C, a conductor layer 68 and an insulator layer 6 are formed on the surface of the semiconductor substrate 65.
A multilayer film of 9, the metal layer 70, the insulator layer 71, and the conductor layer 72 was prepared. In Example 6, after depositing the multilayer film,
In order to easily take out the electrodes from the conductor layer 68, the metal layer 70, and the conductor layer 72, the insulator layer 69 and the metal layer 70 use the mask 42 to form the insulator layer 71, the conductor layer 72, and the gold layer.
The electrode layer 73 made of a zinc alloy was deposited using the mask 43. The mask used is that used in Example 4.

Specifically, at a substrate temperature of 700 ° C., a 1 μm-thick p-GaAs conductor layer 68 is formed by thermally decomposing a mixed gas containing a trace amount of diethylzinc as a dopant in trimethylgallium and arsine diluted with hydrogen. Was deposited. Next, the substrate temperature is 300 ° C. by the low temperature CVD method.
Then, a 70 nm thick insulator layer 69 of SiO ₂ was deposited. Further, at a substrate temperature of 300 ° C., an Al metal layer 70 having a thickness of 1 μm was formed by an electron beam evaporation method. Then, the substrate temperature is 300 ° C. and the thickness is 70 by the low temperature CVD method.
nm of SiO ₂ insulator layer 71 is deposited at a substrate temperature of 7
A 200 nm-thick p-GaA layer was formed by thermally decomposing a mixed gas containing a trace amount of diethylzinc as a dopant in trimethylgallium and arsine diluted with hydrogen at 00 ° C.
After depositing the conductor layer 72 of s, a thickness of 5 is obtained by electron beam evaporation.
An electrode layer 73 of a gold-zinc alloy having a thickness of 00 nm was formed. This state is shown in FIG. The columnar crystal 6 of GaAs
No. 7 grows perpendicularly to the semiconductor substrate 65, so MO
In the deposition process using the CVD method, it was deposited from the base and did not adhere to the side faces of the columnar crystals 67. Next, unnecessary regions are removed by reactive ion etching using a mixed gas of HBr and HCl to remove the conductive layer 68 and the metal layer 7.
0, the electrode layer 73 was exposed. Conductor layer 68, metal layer 7
0, the thin gold wire is welded to the electrode layer 73 to form the drain electrode 7
4, the gate electrode 75 and the source electrode 76 were taken out. This state is shown in FIG. It was possible to obtain good characteristics of the MESFET in which a voltage is applied between the source and the drain of the completed semiconductor device and the drain current is controlled by the voltage applied to the gate electrode. In addition, a MESFE formed on the surface of a conventional semiconductor substrate by using a planar technique.
The occupied area of the substrate can be made very small as compared with T.

Further, the use of a semiconductor having the same conductivity type as that of the columnar crystal 67 and having a higher impurity concentration than that of the columnar crystal in the conductor layer forming the source and drain improves the device characteristics.

In Example 6, gold was used for the needle, but instead of this, an attempt was made by using a similar manufacturing method using silver. When gold was used, similarly good results were obtained. It was When a predetermined voltage V _t of about several V was applied for a predetermined time Δt, fine silver protrusions could be formed on the GaAs substrate. Next, the semiconductor substrate on which the protrusions are formed is placed in an MOCVD apparatus, and a droplet of gold is generated by thermally decomposing a mixed gas containing a trace amount of diethylzinc as a dopant in trimethylgallium and arsine diluted with hydrogen at a substrate temperature of 700 ° C. When used, p-GaAs columnar crystals grew in the direction perpendicular to the substrate. In addition to gold and silver, a needle such as copper, nickel, and iron is used to evaporate the constituent metal from the tip to form a protrusion, and GaAs is grown from the local droplets. A columnar microstructure could be obtained.

Further, the columnar crystals 67 and the conductor layers 68, 72
Trimethylgallium and hydrogen-diluted arsine were used as a source of GaAs to form a, and diethylzinc was used as a dopant, but a gallium organometallic such as triethylgallium and arsine diluted with hydrogen were used as a source of GaAs. MOCVD using an organic metal of zinc or an organic metal of Cd as a dopant may be performed.

Although SiO ₂ is used as the insulating layer, the material is not limited.

Although the metal layer 70 is formed so as to be in contact with the side surface of the columnar crystal 67, the contact position, shape and size are not limited.

Although Al is used for the metal layer 70, any metal may be used as long as it forms a semiconductor forming the columnar crystal 67 and a good Schottky barrier.

Further, although the electrodes are taken out by using the conductor layer, the metal layer, and the electrode layer, a good ohmic contact can be formed with the conductor layer forming the source / drain and the metal layer forming the gate. In the step of depositing the film, any conductor may be used as long as it is a conductor that does not adversely affect the columnar crystals 67 and other semiconductors by diffusing.

Further, p-GaA is used for the conductor layers 68 and 72.
Although s is used, a metal that does not form the columnar crystal 67 and the Schottky barrier may be used.

In Example 6, the GaAs columnar crystals are homoepitaxially grown on the GaAs substrate,
Further, although a semiconductor element was manufactured, an example was given, but a semiconductor element could be manufactured by heteroepitaxially growing columnar crystals of InAs on a GaAs substrate by the same manufacturing method.
Also, a semiconductor device can be manufactured by growing columnar crystals of binary or multi-element compound semiconductors of other III-V group, II-VI group or IV-IV group such as GaP by the same manufacturing method. It was Substrate material is not only GaAs but also other III-
Binary or multi-element compound semiconductors of group V or group II-VI or group IV-IV could be used.

In each of Examples 4 to 6 described above, a junction type, a MISFET, and a MESFET were manufactured, but the semiconductor substrate and the columnar crystals were not limited in type and conductivity type, and any combination was possible. . It does not limit the semiconductor elements that can be manufactured.

Further, in Examples 4 to 6 described above, the conductor layer was formed on the semiconductor substrate on which the columnar crystal was grown, and the electrode was taken out from the conductor layer. If they are the same, the electrode can be formed at an arbitrary position on the semiconductor substrate, so that the step of forming the conductor layer can be omitted. When the semiconductor substrate and the columnar crystal are heteroepitaxially grown, it is a necessary condition that the carrier flow of the semiconductor element is not hindered by the difference in band gap. (Embodiment 7) In Embodiments 4 to 6 of the present invention, a method of evaporating the constituent metal element itself from the tip of a metal needle and depositing it on the substrate is used as a method of forming the metal microprojections. However, in this embodiment, in a gas containing a predetermined metal element, a tunnel current or a field emission current is caused to flow between a sharp needle facing the substrate and a sharp needle and the substrate,
The action decomposes the above-mentioned gas to form minute protrusions on the substrate.

Specifically, C ₅ H ₅ Pt (C ₃ H ₅ ) gas is introduced into the chamber, and the gas pressure is typically 5 × 1.
It was set to 0 ^{−6 to} 760 Torr. A low resistance silicon single crystal having a smooth surface (111) was used for the substrate. In the chamber, a tungsten needle is made to face a distance close to the silicon substrate, and typically the sample voltage V _s = 1 to 1
About 0 V, applied pulse time Δt = several nsec to several 100
When a pulse voltage of about msec was applied at a predetermined duty ratio, minute protrusions having a diameter of 100 nm and a height of 5 nm were formed. It is considered that the minute projections are composed of Pt deposited by decomposing the gas by a tunnel current or a field emission current. In this embodiment, a pulse voltage is applied so that the sample side is positively biased, but similar results were obtained even if the polarity was changed. After that, a semiconductor device was obtained by the same process as in Examples 4 to 6 above.

The organometallic gas used in this embodiment may be a predetermined organometallic gas containing Pt other than C ₅ H ₅ Pt (C ₃ H ₅ ) described above, and other Au, Ag, Cu,
You may use the organic metal containing Pd, Ni, etc. Further, as the needle, other than W, Pt, Au or the like may be used. This example was also effective for single element semiconductors or compound semiconductors other than silicon substrates. (Embodiment 8) Next, an eighth embodiment of the present invention will be described below. When a PtIr needle and a silicon (111) substrate were dipped in a diluted KAu (CN) ₂ solution, the needle was brought close to the substrate, and a negative voltage of typically sample voltage V _s = −1 to −10 V was applied, Minute protrusions having a diameter of several nm to several hundred nm were formed. Better results were obtained under light irradiation. It is considered that these minute projections were formed by neutralizing Au ions in the above solution by a tunnel current, a field emission current, or an ion current, and depositing. After that, in Example 4 above.
The semiconductor device was obtained by performing the same process as in Nos. 6 to 6.

The solution used in this example is the above KAu.
A predetermined solution containing Au other than (CN) ₂ may be used, or a solution containing other Ag, Cu, Pt, Pd, Ni or the like may be used. Further, as the needle, W, Au or the like may be used instead of PtIr. This example was also effective for single element semiconductors or compound semiconductors other than silicon substrates.

In the fourth to eighth embodiments, a method of manufacturing a semiconductor device made of one columnar crystal has been described. However, in the fourth to eighth embodiments, processing operations are performed at a plurality of positions on a semiconductor substrate. Furthermore, a plurality of semiconductor elements could be manufactured on the semiconductor substrate by performing a predetermined process. Furthermore, a simple logic circuit could be manufactured by connecting the manufactured elements.

[0079]

As is apparent from the above description, according to the present invention, the first semiconductor made of columnar crystals provided on the surface of the semiconductor substrate and the predetermined side surface between the tip portion and the root portion of the first semiconductor are provided. Since the first semiconductor provided in contact with or embedded in the region and the second semiconductor having a different conductivity type are provided, there is an advantage that the area occupied by the element in the substrate plane can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device of Example 1 according to the present invention.

FIG. 2 is a schematic sectional view of a semiconductor device of Example 2 according to the present invention.

FIG. 3 is a schematic sectional view of a semiconductor device of Example 3 according to the present invention.

4 (a), (b), (c), and (d) are process cross-sectional views of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention, and FIG. It is a schematic diagram of a semiconductor device.

FIG. 5 is a schematic view of a mask used in a method for manufacturing a semiconductor device of Example 4.

6 (a), (b), (c), and (d) are process cross-sectional views of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

7 (a) and 7 (b) are process cross-sectional views of a method for manufacturing a semiconductor device according to Example 5 of the present invention, and FIG. 7 (c).
FIG. 3 is a schematic view of a manufactured semiconductor device.

8A, 8B, and 8C are process cross-sectional views of a method for manufacturing a semiconductor device according to Example 6 of the present invention, and FIG. 8D is a sectional view of the manufactured semiconductor device. It is a schematic diagram.

[Explanation of symbols]

1, 11, 22, 32, 50, 65 Semiconductor substrate 2, 12, 23, 35, 51, 67 Columnar crystal 3, 7, 13, 16, 18, 24, 28, 36, 40,
52, 54, 56, 68, 72 Conductor layers 4, 6, 14, 15, 17, 25, 27, 37, 39,
53, 55, 57, 69, 71 Insulator layer 5, 38 Semiconductor layer 8, 19, 29, 47, 62, 74 Drain electrode 9, 21, 30, 49, 64, 76 Source electrode 10, 20, 31, 48 , 63, 75 gate electrode 26, 70 metal layer 33, 66 protrusion 34 droplet 41, 42, 43 mask 44, 45, 46, 58, 59, 60, 61 tungsten layer 73 electrode layer

Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location 7376-4M H01L 29/80 B (72) Inventor Kazuo Yokoyama 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Takao Nita, 1006 Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (13)

[Claims] 1. A first semiconductor made of columnar crystals provided at least on the surface of a semiconductor substrate, and provided in contact with or embedded in a predetermined region on a side surface between a tip portion and a root portion of the first semiconductor. A first semiconductor and a second semiconductor having a conductivity type different from that of the first semiconductor, wherein the second semiconductor has a gate electrode, and a tip portion and a root portion of the first semiconductor have a source electrode and a drain electrode or a drain electrode and a source electrode. A semiconductor device characterized by being provided. 2. A first semiconductor composed of columnar crystals provided at least on the surface of a semiconductor substrate, and provided in contact with or embedded in a predetermined region on a side surface between a tip portion and a root portion of the first semiconductor. An insulator layer and a conductor portion formed on the insulator layer, wherein the conductor portion is a gate electrode, and the tip portion and the root portion of the first semiconductor are a source electrode and a drain electrode or a drain electrode. And a source electrode are provided. 3. A first semiconductor composed of columnar crystals provided at least on the surface of a semiconductor substrate, and provided in contact with or embedded in a predetermined region on a side surface between a tip portion and a root portion of the first semiconductor, A gate electrode is provided on the first semiconductor and a metal portion forming a Schottky barrier, and a source electrode and a drain electrode or a drain electrode and a source electrode are provided on the tip portion and the root portion of the first semiconductor. A semiconductor device characterized by being provided. 4. The semiconductor device according to claim 1, wherein the conductivity type of the semiconductor substrate and the conductivity type of the first semiconductor are the same type. 5. A semiconductor is locally deposited on the surface of a semiconductor substrate, and then the temperature of the surface of the semiconductor substrate is set to be equal to or higher than the eutectic point temperature of the metal and the substrate material and equal to or lower than each melting point thereof. A local alloy droplet region is formed at a metal deposition site on the substrate surface, and columnar crystals are locally grown on the semiconductor substrate surface by using a vapor-liquid-solid reaction. Of manufacturing a semiconductor device. 6. A conductive needle having a sharp tip is brought close to the surface of the semiconductor substrate, and the needle is placed in a gas containing a metal having a eutectic phase equilibrium with the semiconductor substrate material at a predetermined pressure. 6. The semiconductor device according to claim 5, wherein at least the metal is locally deposited on the surface of the semiconductor substrate by applying a predetermined electric field between the surfaces of the semiconductor substrate and flowing a tunnel current or a field emission current. Production method. 7. A conductive needle having a sharp tip is brought close to the surface of the semiconductor substrate, and the needle and the surface of the semiconductor substrate are placed in a liquid containing a metal having a eutectic phase equilibrium with the semiconductor substrate material. 6. A semiconductor device according to claim 5, wherein at least the metal is locally deposited on the surface of the semiconductor substrate by applying a predetermined electric field between them to cause a tunnel current, a field emission current or an ion current to flow. Method. 8. A conductive needle containing a metal exhibiting a eutectic phase equilibrium with a semiconductor substrate material and having a sharp tip is brought close to the surface of the semiconductor substrate, and in a vacuum or in a gas at a predetermined pressure, 6. The semiconductor according to claim 5, wherein a predetermined electric field is applied between the needle and the surface of the semiconductor substrate to evaporate the constituent elements from the tip of the needle and locally attach the constituent elements to the surface of the semiconductor substrate facing the needle. Device manufacturing method. 9. A gas-liquid-solid reaction is carried out by directly applying a gas of a predetermined pressure composed of a halide containing at least the constituent elements of the semiconductor substrate or a predetermined element or an organometallic compound or hydride. Alternatively, the desired element is dissolved in the alloy droplet region by decomposing it using heat, electromagnetic waves or other energy and exposing it to the semiconductor substrate surface, and the crystal is locally formed on the semiconductor substrate surface in contact with the droplet region. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the reaction is a reaction for depositing on. 10. The metal forming the droplets is Au, Ag, C
u, Pt, Pd, Ni, Ir, Rh, Co, Os, R
The method for manufacturing a semiconductor device according to claim 5, further comprising any one of u, Fe, Hg, Cd, and Zn. 11. The method for manufacturing a semiconductor element according to claim 5, wherein the columnar crystal or the semiconductor substrate is composed of a single element semiconductor or a compound semiconductor. 12. A multilayer film comprising a first conductive layer, an insulator layer, a second semiconductor, an insulator layer, and a second conductive layer on the surface of a semiconductor substrate, wherein the first conductive layer and the second conductive layer are respectively 6. The method of manufacturing a semiconductor element according to claim 5, wherein the semiconductor layer is deposited so as to be electrically connected to a root portion and a tip portion of the columnar crystal, and the semiconductor layer is in contact with a predetermined region of the columnar crystal to be electrically conductive. 13. Instead of the step of depositing a first conductive layer,
13. The method for manufacturing a semiconductor device according to claim 12, wherein an electrode is formed on the semiconductor substrate.