JPH064653A - Still picture reproducing device - Google Patents

Abstract

(57) [Abstract] [Purpose] Transfers image data and controls display screen switching simultaneously in a still image playback device. In a still image reproducing apparatus including a control host processor 2, a plurality of image processing processors 18 and 19, and an image expansion processor 7, each image processing processor 1
8 and 19 local buses 20 and 21 are independent, the data to the look-up table 8 and 9 is rewritten via one of the local buses 20, and the screen refresh address counter 10 of the plural image memories 4 and 5 is rewritten. , 11 to transfer the image data from the I / O controller 3 to the image memories 4 and 5 via the other local bus 21, and to connect the image expansion processor 7 to the one local bus. The compressed image data from the I / O controller 3 is expanded and transferred to the image memories 4 and 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image file system or a general image file system which requires processing of a still image or image processing for switching images and displaying the processing result at the same time. The present invention relates to a still image reproducing device applicable to an image device.

[0002]

2. Description of the Related Art Conventionally, as this type of still picture reproducing apparatus, for example, there is one having a configuration shown in FIG. 2, and this still picture reproducing apparatus controls and manages the entire apparatus via a system bus 1. 2, an I / O controller 3 for controlling data transfer of input / output images, first and second image memories 4 and 5 corresponding to transfer destinations of the image data, and image data of the image memories 4 and 5. An image processor 6 that performs a predetermined process (including data transfer), an image decompression coprocessor (hereinafter referred to as a coprocessor) 7 that decompresses and transfers the image compressed data from the I / O controller 3 to a predetermined image memory, First and second look-up tables 8 for selecting the image data read from the image memories 4 and 5 according to a display area (composite display),
9, the screen refresh address counters 10 and 11 for outputting the screen refresh address signals (data) of the image memories 4 and 5, and the display images by the first and second look-up tables 8 and 9 are synthesized. A D / A for synthesizing a circuit 12 and for converting the image data synthesized by the synthesizing circuit 12 into an analog signal to output a video
It is composed of a conversion unit 13 and a host interface 14 connecting the image processing processor 6 to the system bus 1 so that the image processing processor 6 can be controlled and managed by the control host processor 2.

In the still image reproducing apparatus, a command is issued from the control host processor 2 when an image is input, a predetermined process of the input image and a switching display of the processed image are performed, and the I / O is issued by the command.
The controller 3, the image processing processor 6, and the coprocessor 7 execute predetermined processing.

Therefore, the image memories 4 and 5, the look-up tables 8 and 9 and the screen refresh address counters 10 and 11 are connected to the image processor by the data bus (including address data) 15a and the local bus 15 of the address line 15b. 6, the image processor 6 continuously rewrites the data into the look-up tables 8 and 9, and the screen refresh address data is transferred to the screen refresh address counters 9 and 1.
It is output to 0 and the output timing of the screen refresh is set. In addition, the buffer selectors 16 and 17 are selected depending on the output timing of the screen refresh.
Are switched, and the image data in the image memories 4 and 5 are input to the look-up tables 8 and 9 by this switching. The coprocessor 7 is connected to the system bus 1 and the local bus 15.

In the still picture reproducing apparatus having the above structure, continuous rewriting of data to the two look-up tables 8 and 9 connected to the local bus 15 of the image processor 6 is simultaneously performed. Be done.

Further, since the image data from the first and second look-up tables 8 and 9 by overwriting is combined by the combining circuit 12, two images can be overlapped on the same display area, In addition, various images can be switched by combining the switching of display images.

[0007]

In the still picture reproducing apparatus, when the control host processor 2 issues an image input command, the I / O controller 3 stores the input image data in a predetermined image memory. Transferred to.

Since this image data is transferred via the local bus 15, the input image data is I
/ O controller 3, system bus 1, host interface 14, image processor 6, local bus 1
5 is transferred to the first image memory 4 or the second image memory 5 via the path 5, and the input image data is transferred to the first image memory 4 via the path via the I / O controller 3, the system bus 1, the coprocessor 7, and the local bus 15. It is transferred to the image memory 4 or the second image memory 5.

Therefore, the input image data cannot be transferred when the screens are switched (when the images are combined), and conversely, the screen switching control (image combination control) is performed when the input image data is transferred. Can't do.

In other words, this is because bus contention occurs in the local bus 15, which makes it difficult to smoothly perform the transfer of the input image data and the switching control of the screen at the same time, thereby lowering the execution efficiency of the device control. Was there.

In addition, the instruction from the control host processor 2 to each processor may conflict on the system bus 1, and it may not be possible to control each processor at an arbitrary time.

The present invention has been made in view of the above problems, and an object thereof is to smoothly perform transfer of image data (or compressed image data) and screen switching control at the same time without occurrence of locus bus competition. Another object of the present invention is to provide a still image reproducing device which can be controlled by the control host processor at any time.

[0013]

In order to achieve the above object, the present invention provides a control host processor, an image processing processor, an image expansion coprocessor, an I / O processor for performing at least image processing and switching of a plurality of images. An O controller, a plurality of image memories, a plurality of look-up tables and a screen refresh address counter are provided, and the image data from the I / O controller is transferred to a predetermined image memory, and the compressed image data from the I / O controller is transferred. Is expanded and transferred to the image memory, the data in the image memory is subjected to predetermined processing, and at the time of the transfer or predetermined processing of the image data or compressed image data, the screen refresh address counter outputs the address signal of the image memory. , And the above look-up A still image reproducing device capable of switching a display image by continuously rewriting data into a table to synthesize a plurality of images and displaying the plurality of images, wherein the first image processor converts the plurality of images into the plurality of look-up tables. Data rewriting and the data output of the screen refresh address counter are controlled, the second image processor performs predetermined processing on the image data from the I / O controller, and the image decompression coprocessor controls the I / O controller from the I / O controller. The first image processor, the plurality of look-up tables and the screen refresh address counter are connected to each other by the first local bus in order to perform the predetermined processing of the compressed image data of Multiple image memory as second local bus And connecting the first and second image processors to the system bus of the control host processor via the host interface and connecting the image decompression coprocessor to the second local bus. The gist is that the control host processor can manage and control at least each of the processors at an arbitrary time and can synthesize a plurality of display images.

[0014]

In the still picture reproducing apparatus having the above structure, the first local bus and the second local bus are independent of each other, and the image data input by the I / O controller is transferred to the predetermined image memory. At this time, the transfer function of the image data is shared by the second image processor, and the image data is transferred to the predetermined image memory via the second local bus.

When the compressed image data from the I / O controller is decompressed and transferred to the predetermined image memory, the image data is decompressed by the image decompression coprocessor, and the decompressed image data is the second image data. Is transferred to a predetermined image memory via the local bus.

Since the first local bus is not used in the transfer of the image data (or the compressed image data), depending on the first image processor connected to the first local bus, the plurality of look-ups may be performed. Rewriting of data to the up table and data writing of the screen refresh address counter can be performed simultaneously with the transfer of the image data.

As described above, since the first and second local buses can cause the first and second image processors to perform different processing independently of each other, the transfer of the image data and the screen switching control are performed. (Screen composition control) is performed smoothly at the same time.

In the control host processor, the image expansion processor may be connected to the first local bus when controlling the processors and the I / O controller as sub processors. It is possible to control the instruction of each processor at an arbitrary time without causing bus contention on the system bus.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A still image reproducing apparatus of the present invention connects two image processing processors and I / O controllers controlled and managed by a control host processor to a system bus, and a plurality of image processing processors are connected to a local bus. An image memory and an image decompression processor are connected, and a plurality of look-up tables and screen refresh address counters are connected to a local bus of the other image processing processor which is independent of this image processing processor, and one image processing processor is connected. By the continuous rewriting of data to a plurality of look-up tables connected to the local bus (that is, simultaneously controlling the output levels of two image output signals), and the initial value of the screen refresh counter of the image memory. Was rewritten and the same image processing was performed. Timing control of the output address of the screen refresh counter by independent another image processor to processor, performs transfer control of the input image data from the I / O controller, the I / O
An image decompression coprocessor connected to the controller decompresses the input compressed image data from the I / O controller and controls the transfer.

Therefore, the still picture reproducing apparatus has the structure shown in FIG. In the figure, the same parts as those in FIG. 2 and corresponding parts are designated by the same reference numerals, and a duplicate description will be omitted.

In FIG. 1, 18 is at least data rewriting to the first and second look-up tables 8 and 9 for screen switching (image composition), and switching address data to the screen refresh counters 10 and 11. Is a first image processor for outputting at least the image data in the image memories 4 and 5 and is a first image processor for performing predetermined processing (including data transfer processing). The two image processing processors 18 and 19 are connected to the system bus 1 via the host interface 14 and are managed and controlled by the control host processor 2. Further, the I / O controller 3 connected to the system bus 1 is provided with an image decompression coprocessor (hereinafter referred to as a coprocessor) 7 that decompresses and transfers the input compressed image data from the I / O controller 3. It is connected.

First of the first image processor 18
The local bus 20 of the first and second look-up tables 8 and 9 and the screen address counter 1
0 and 11 are connected, and the output addresses of the screen address counters 10 and 11 are buffer selectors 16 and
Selected at 17. The selection of this address is performed by the address line 21b of the second image processor 19.

The second image processor 19 is also used.
First and second image memories 4 and 5 and an image expansion coprocessor (hereinafter referred to as a coprocessor) 7 are connected to the local bus 21 of FIG.

The coprocessor 7 is connected to the I / O controller 3 so that the compressed image data from the I / O controller 3 is expanded and transferred to the image memories 4 and 5. The output timing (screen refresh timing) of the screen refresh address counters 10 and 11 is controlled by the second image processor 18.

As before, the first and second local buses 20 and 21 are data buses (including address data) 19a and 20a and address lines 19b and 20.
The address line 20b is the address of the first and second look-up tables 8 and 9, and the address line 21b is the screen refresh timing, that is, the buffer selectors 16 and 1.
7 selection signal.

As a result, the I / O controller 3, the first image processor 18 and the second image processor 19 are connected to the control host processor 2 by the system bus 1, and the first and second image processors 18 and 19 are connected. The image processors 18 and 19 may have a common host interface 14.

The second image processor 19 is also provided.
The second local bus 21 provides a transfer path for transferring the image data from the image device connected to the I / O controller 3 to the first or second image memory 4, 5. In this case, as a transfer path for transferring the image data as it is, I
A path for the I / O controller 3, the system bus 1, the host interface 14, the second image processor 19, the second local bus 21, the first and second image memories 4 and 5 is secured, and for compressed image data. As a result, the paths of the I / O controller 3, the coprocessor 7, and the first and second image memories 4 and 5 are secured.

Here, separate commands are issued by the control host processor 2 to the first and second image processing processors 18 and 19, for example, transfer of image data input via the I / O controller 3, and When the screen switching control command is issued, the screen switching control (image combining processing) by the first image processor 18 and the first local bus 20 and the image by the second image processor 19 and the second local bus 21. The transfer control and the transfer control are performed almost in parallel at the same time.

That is, the first local bus 20 and the second local bus 21 are independent of each other, and, for example, input image data is transferred to the I / O controller 3, the system bus 1,
When transferring to the image memory 4 or the image memory 5 through the route of the host interface 14, the second image processor 19 and the second local bus 21, it is not necessary to use the first local bus 20 for the image data transfer. Because.

On the other hand, with respect to the compressed image data input from the I / O controller 3, the coprocessor 7 decodes the compressed image data into restored image data, and the restored image data is transferred to the second local bus 21. And is directly transferred to the designated image memory.

The first image processor 18 is also provided.
Is similar to the conventional one, the first and second image memories 4, 5
Screen refresh address counter 10, 11
The initial value of each is set independently, and the reference display position based on the screen refresh function is set to the first and second look
The data is given to the up tables 8 and 9 and the data is rewritten to the first and second look up tables 8 and 9.

As a result, the screen switching processing such as image composition by the first image processor 18 and the second image processing are performed.
The image data transfer processing (or the image data expansion transfer) by the image processor 19 can be performed independently and in parallel, and the processing can be smoothly performed simultaneously.

Further, when the decompressed transfer of the compressed image data by the coprocessor 7 and the image processing by the first and second image processing processors 18 and 19 are not required, the system bus 1 need not be used, and the coprocessor 7 can be used. I
Connected to the I / O controller 3 and the first and second image processors 18 and 19 are connected to the host interface 1
It is connected to the system bus 1 via 4. Therefore, the control host processor 2 can manage the I / O controller 3 connected to the system bus 1 and the first and second image processing processors 18 and 19 as sub processors on an equal basis. Can be controlled at any time, which facilitates system control of the still image reproducing apparatus.

[0034]

As described above, according to the still picture reproducing apparatus of the present invention, the local buses of the two image processing processors are made independent, and one of the image processing processors synthesizes images (switches display screens). Rewriting data to the first and second look-up tables, setting screen refresh address data of a plurality of image memories, transferring the data of a plurality of image memories by the other image processing processor, and performing various processing. And, the two image processors are connected to the system bus of the control host processor via a common host interface, and the input compressed image data from the I / O controller connected to the system bus is expanded and stored in the image memory. Connect the image decompression coprocessor to be transferred to the local bus of the other image processing processor, and Since the host processor controls and manages each processor, the one image processing processor and the other image processing processor can independently perform different processing. Even when performing data transfer processing or processing that expands and transfers compressed image data from the I / O controller, image switching (data to multiple look-up tables Rewriting), that is, the transfer of the image data (compressed image data) and the screen switching process can be smoothly performed simultaneously.

Further, in the control host processor of the still picture reproducing apparatus of the present invention, the system bus can be utilized when the image data is transferred and the screen is switched at the same time as described above. The processors and the I / O controller can be equally managed as sub-processors, each processor can be controlled at an arbitrary time, and the system control of the still image reproducing apparatus can be easily performed. .

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a still image reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a still image reproducing device.

[Explanation of symbols]

 1 System Bus 2 Control Host Processor 3 I / O Controller 4 First Image Memory 5 Second Image Memory 7 Image Decompression Coprocessor 8 First Look Up Table 9 Second Look Up Table 10, 11 Screen refresh address counter 12 Compositing circuit 13 D / A converter 14 Host interface 18 First image processor 19 Second image processor 20 First local bus 21 Second local bus

Claims (1)

[Claims] 1. A control host processor, an image processing processor, an image expansion coprocessor, an I / O controller, a plurality of image memories, and a plurality of look-up tables for performing at least image processing and switching of a plurality of images. And a screen refresh address counter, the image data from the I / O controller is transferred to a predetermined image memory, the compressed image data from the I / O controller is decompressed and transferred to the image memory, In addition to processing the data in a predetermined manner, transferring the image data or the compressed image data, outputting the address signal of the image memory by the screen refresh address counter in the predetermined processing, and continuing the data to the plurality of look-up tables. Displayed by rewriting A still image reproducing apparatus capable of switching between images and combining and displaying a plurality of images, wherein the plurality of look
The data rewriting to the up table and the data output of the screen refresh address counter are controlled so that the second image processor performs predetermined processing of the image data from the I / O controller, and the image decompression coprocessor performs the same processing. The first image processor, a plurality of look-up tables and a screen refresh address counter are connected by a first local bus to perform a predetermined process on the compressed image data from the I / O controller, and the second image is processed. The processing processor and the plurality of image memories are connected by a second local bus, the first and second image processing processors are connected to the system bus of the control host processor via the host interface, and the image expansion is performed. Coprocessor A still image reproducing device connected to the second local bus, capable of managing and controlling at least each of the processors at an arbitrary time by the control host processor and capable of synthesizing a plurality of display images. .