JPH064689A - Linear array parallel DSP processor - Google Patents

Abstract

(57) [Summary] [Purpose] Write and read for the next process are executed simultaneously during the same instruction cycle. [Structure] A three-transistor memory cell is used for the memory A cell 3 and the memory B cell 5, and the write bit line and the read bit line thereof are dedicated and individually provided. That is, one vertical bit line for each processor element from the input SAM section to the ALU array section via the data memory A section has a conventional ALU array from the input SAM section via the data memory A section. There are two vertical bit lines for each processor element, that is, a read bit line reaching the area and a write bit line extending from the ALU array section to the data memory A section. At this time, in the memory A cell 3, one transistor for writing and two transistors for reading are connected to different write bit lines and read bit lines, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a linear array type parallel DSP processor capable of programmatically processing a video signal of a television or the like, and particularly to a read / write bit line of a memory cell of its constituent elements. The present invention relates to a memory access and a memory access read and write separately, enabling pipeline operation and improving the processing performance of the processor.

[0002]

BACKGROUND OF THE INVENTION The present invention relates to a digital signal processing of a video signal of a television or the like by a software program,
The present invention relates to the configuration of a SIMD-controlled programmable linear array type parallel DSP processor, and in particular, in order to improve its processing capability, the configuration is such that the writing and reading between the ALU and the data memory in each processor element are pipelined. (SIMD control: Single Instruction stream Mu
lti Data stream / All processor elements work together by one program).

As a conventional technique, there is a SIMD-controlled linear array type processor (for example, JIM CHILDERS, et al "SVP: SERI) as a configuration of a processor for programmable digital signal processing of a video signal of a television or the like.
AL VIDEO PROCESSSOR "IEEE1990 CUSTOM INTEGRATED CI
RCUITS CONFERENCE 17.3).

As shown in FIG. 2, this processor has a form in which a 1-bit ALU arithmetic array is incorporated in a VRAM. Hereinafter, description will be made from FIG.

This processor is mainly composed of an input SAM.
(Serial access memory) section, Data memory A section, A
It is divided into an LU array section, a data memory B section, an output SAM section, a program control section, and the like.

The program control unit includes a program memory and its sequence control circuit. Also, an input SAM unit, a data memory A unit, an ALU array unit, a data memory B unit,
The output SAM unit constitutes a large number of linear array type linearly arranged processor element groups as a whole, and SIMD control is performed in conjunction with one common program control unit in the program control unit.

The input SAM unit, the data memory A unit, the data memory B unit, and the output SAM unit are basically memories, and the ROW address decoding for these memories will not be described in detail, but in FIG. Will be described below as being included in this program control unit.

A single element of a number of paralleled processor elements is a vertical elongated area, as shown by the diagonal lines in FIG. 2, which are arranged in a horizontal linear arrangement in the figure. That is, the vertically long and slender processor elements shown by the slanted lines in FIG. 2 respectively realize the configuration of the processor as shown in FIG. 3 that is generally necessary for constructing one processor element.

The input SAM unit corresponds to the input buffer memory (IQ). The output SAM unit corresponds to the output buffer memory (OQ). The data memory B section corresponds to the first data memory (RFB). The data memory A section corresponds to the second data memory (RFA). The ALU array unit corresponds to the selector (SEL) and ALU for selecting and operating the data of the first data memory and the data of the second data memory as needed.

The difference between this processor element and an ordinary processor is that in an ordinary processor, the hardware is a word processor and the word is processed as a unit. In the case of this processor, the hardware is a bit processor, and Is a point to be processed. Bit processors have small hardware and can realize a large number of parallel numbers that cannot be realized normally. The parallel number of the linear array of processor elements is set to match the number of pixels (H) in one horizontal scanning period of the video signal.

Further, the structure of this processor element is
It can be roughly written as shown in FIG. One processor element of the input SAM unit is composed of one input pointer cell 1 in FIG. 4 and a plurality of input SAM cells 2 arranged vertically.
Consists of. The input SAM cells 2 are prepared by vertically arranging them by the number of input bits (ISB) in FIG. 2, but in FIG. 4, they are omitted and only one is shown as a representative. The input pointer cell 1 is a flip-flop (FF) for forming a shift register.

For one processor element of the data memory A section, the memory A cell 3 in FIG.
The number of bits of AB is prepared and arranged vertically,
In FIG. 4, it is omitted and only one is shown as a representative.

One processor element of the ALU array section is the ALU cell 4 in FIG. Where A
The real ALU portion in the LU cell 4 is a 1-bit ALU, which is about the full adder. Also A
The selector (SEL) in the LU cell 4 is a 1-bit ALU
Input selection, and selects data from one of the intersections with the buses indicated by a plurality of X's in the figure. FF is a flip-flop (1-bit register).

For one processor element of the data memory B section, the memory B cell 5 in FIG.
Although the number of bits of BB is prepared and arranged vertically, it is omitted in FIG. 4 and only one is displayed as a representative.
The memory A cell 3 and the memory B cell 5 may be the same.

One processor element of the output SAM section is composed of one output pointer cell 7 in FIG. 4 and a plurality of output SAM cells 6 arranged vertically. The output SAM cells 6 are prepared by arranging them vertically for the number of output bits (OSB) in FIG. 2, but in FIG. 4, they are omitted and only one is displayed. The output pointer cell 7 is a flip-flop (FF) for forming a shift register. The output pointer cell 7 and the output SAM cell 6 may be the same as the input pointer cell 1 and the input SAM cell 2, respectively.

The input SAM read signal (IR), the memory access signal (AA and AB), the output SAM write signal (OW), etc. are the word lines of the memory cell and are assumed to be address-decoded. For read-modify-write, a signal for reading is generated in the first half of the cycle and a signal for writing is generated in the latter half of the cycle.

In FIG. 4, connection lines (bit lines) that vertically pass through the cells are assumed to pass while vertically connecting circuit elements. Of the horizontal connection lines, the word line of the memory and the input data bus pass while connecting the circuit elements arranged side by side in the same manner, and the pointer line connects the corresponding circuit elements arranged next to each other. Connected.

Next, the operation of this processor will be described with reference to FIGS.
Use to explain. The input signal is guided to the input SAM section. The flip-flops that compose the input pointer cell 1 compose a shift register, and a 1-bit signal, that is, an input pointer signal (IP), which is one logic "H" relayed by this shift register, is generated and the logic "H" is generated. Input data (IN) is written to the input SAM cell 2 of the processor element designated by H ″. The input data bus and the input SAM cell 2 each have only ISB bits,
In FIG. 4, only one bit is shown.

The input data can be stored in the SAM of the processor element in the right direction in order from the SAM of the leftmost processor element of the input SAM section by the input pointer every horizontal scanning period of the video signal. Since the number of processor elements is equal to the number of pixels (H) in one horizontal scanning period of the video signal, the clock SA corresponding to the data rate of the input video signal causes SA to the right in the one horizontal scanning period.
M writing can be continued and input data for one horizontal scanning period can be stored in the input SAM section. Such an input operation is repeated every horizontal scanning period.

The program control unit controls the input SAM unit, the data memory A unit, the ALU array unit, the data memory B unit, and the output SAM unit by SIMD as follows, and executes the processing.

The input data accumulated in the input SAM section for one horizontal scanning period is transferred from the input SAM section to the data memory B section under the control of the program control section as needed in the next one horizontal scanning period. Moved and used for arithmetic processing.
In this operation, the stored contents of the necessary bits of the input SAM section are accessed by the program by the input SAM read signal (IR), and then the memory access signal (AB) is sent to the predetermined memory cell of the data memory B section of the transfer destination. It is realized by taking out and writing.

The input SAM read signal (IR) and the memory access signal (AB) are word lines, and there are a plurality of word lines, which are decoded by the address decoder. In addition, these word lines are for read-modify-write, so the signals for reading are in the first half of the cycle.
The signal for writing is generated at the timing of the latter half of the cycle. This data transfer is performed bit by bit through the vertical bit lines. There is nothing to be processed by the ALU at the time of this data movement, but it is designed to pass through the ALU cell 4, and at that time, the ALU output control signal (BB) is generated at a predetermined timing.

The read signal (IR) from each input SAM cell 2 of the input SAM section and the memory access signal (AA) to each memory cell of the data memory A section have the same address space and are decoded by the same ROW decoder of the memory. Has been
It is given as a word line.

In the data arithmetic processing, if necessary, between the data memory A section and the data memory B section, a memory access signal (AA, AB) is issued to a predetermined memory cell to read or write the data, and the data is stored. You can move. This is also read-modify-write as in the data transfer from the input SAM section to the data memory B section, and one bit per bit is performed via the vertical bit line. Also at this time, there is nothing to be processed by the ALU at the time of data movement, but it is configured to pass through the ALU cell 4, and at that time
The U output control signal (BA or BB) is generated at a predetermined timing.

Therefore, in the data memory A section and the data memory B section, the input data written in the past as described above and the data in the middle of calculation are stored. 1-bit register (FF) in those data or ALU cell 4
Using the data stored in, the bit arithmetic processing in the ALU required in each cycle can be performed.

The arithmetic operation in this ALU cell 4 is
It is specified by the program by the control signal (ALU-CONT). The result calculated by the ALU cell 4 is stored in the 1-bit register in the ALU cell 4, or is written again in the data memory A section or the data memory B section as needed.

For example, the data of the memory A cell 3 of a certain bit in the data memory A section and the data of the memory B cell 5 of a certain bit of the data memory B section are added to each other, and the memory B cell of the bit just read in the data memory B section. The case of writing the addition result to 5 is as follows. A read signal (AA) to the memory A cell 3 of a predetermined bit in the data memory A section,
In addition, the memory B cell 5 of a predetermined bit in the data memory B section
A read signal (AB) is issued in the first half of the cycle. The data read from the data memory A section and the data read from the data memory B section are AL of the ALU array section.
U is calculated. The output from the ALU outputs a write signal (AB) to the memory B cell 5 of the previous bit of the data memory B section in the latter half of the cycle and writes it there. At that time, the ALU output control signal (BB) is given at a predetermined timing.

In this way, the data is read from the data memory A and the data memory B located above and below according to the program, and the necessary arithmetic operation or logical operation is performed in the ALU array section, and the data memory A is read again. Part or data memory B part can be written to a predetermined address. This arithmetic processing is all bit processing, 1 bit 1
Advance bit processing.

When the calculation processing for one horizontal scanning period is completed,
During the horizontal scanning period, it is necessary to transfer the output data for the horizontal scanning period to the output SAM section at the last part of the program. If the data to be output is present in the data memory A section, the memory access signal (AA) is output to a predetermined memory cell in the first half of the cycle to read the data, and the output SAM of a predetermined bit of the output SAM section is also used. A write signal (OW) is generated in the output SAM cell 6 in the latter half of the cycle so that the data is transferred to the cell 6.

Data is transferred one bit at a time through one bit line in the vertical direction. Also at this time, there is nothing to be processed by the ALU at the time of data movement, but the data is passed through the ALU cell 4, and at that time, the ALU output control signal (BB) is generated at a predetermined timing.

The write signal (OW) to each output SAM cell 6 of the output SAM section and the memory access signal (AB) to each memory cell of the data memory B section have the same address space and are decoded by the same ROW decoder of the memory. Given as a word line.

As described above, during the time of one horizontal scanning period, reading of the input data accumulated in the input SAM section, necessary arithmetic processing, necessary data movement, and output S
The writing of output data to the AM section is controlled by the SIMD control program in units of bits. This program process is repeated in units of horizontal scanning period.

Output SAM after this program processing is completed
The output data transferred to the section is further in the next horizontal scanning period,
It is output from the output SAM unit as follows.

The output signal is led from the output SAM section to the output data bus and output to the outside of this processor. The flip-flops that form the output pointer cell 7 form a shift register, and a 1-bit signal, ie, an output pointer signal (OP), which is one logic "H" relayed by this shift register, is generated, and the logic "H" is generated. The output data is read from the output SAM cell 6 of the processor element designated by the above to the output data bus and becomes the output data (OUT). The output data bus and the output SAM cell 6 have only OSB bits, but only one bit is shown in FIG.

The output data can be read every horizontal scanning period of the video signal by the output pointer while sequentially shifting the location from the SAM of the leftmost processor element of the output SAM section to the SAM of the right processor element. Since the number of arranged processor elements is equal to the number of pixels (H) in one horizontal scanning period of the video signal, the output data for one horizontal scanning period is output from the SAM unit with a clock adapted to the data rate of the output video signal. Can be output.
Such an output operation is repeated every horizontal scanning period.

1. Input operation by writing input data to the input SAM section. 2. Input SA by SIMD control of program control unit
Input data read from M section, data memory A section, A
Execution of arithmetic processing by the LU array unit and the data memory B unit, data transfer, and writing of output data to the output SAM unit. 3. Output operation by reading output data from the output SAM section. The above three operations are pipeline operations in units of one horizontal scanning period of the video signal, and if attention is paid to the input data of one horizontal scanning period, the respective operations are shifted by the time of one horizontal scanning period. However, the three operations can proceed sequentially and concurrently.

[0037]

In the configuration of the conventional example, the input SAM section by the SIMD control of the program control section, the data memory A section, the ALU array section, the data memory B section,
In the execution of the arithmetic processing by the output SAM unit, two data sources of the ALU input are the input SAM cell 2, the data memory A unit, the data memory B unit, and the 1-bit register in the ALU cell 4. The data destination of the ALU output is one of the output SAM cell 6, the data memory A section, the data memory B section, and the 1-bit register in the ALU cell 4.

The instruction cycle in this processor is
That is, data is read from two data sources, arithmetic processing is performed by the ALU, and writing is performed in the data destination. That is, data is basically A in all operations.
It is supposed to pass through the LU, and all the processing cycles are read-modify-write operations.

Generally, the input SAM cell 2, the memory A cell 3, the memory B cell 5 and the output SAM cell 6 of this processor are made of a DRAM structure, so that the access time is slow even by themselves. In addition, since the read-modify-write operation is performed in which both read and write operations are executed in one cycle, the processing cycle is slow.

Since the processor having the architecture shown in FIG. 2 performs program processing in units of one horizontal scanning period, it realizes high programmability by real-time processing even for a video signal having a high data rate. This is realized because one processor element is extremely miniaturized with a processing unit being a bit unit, and thus a large number of processor elements are parallelized.

The processing performance of the processor of this architecture is such that the length in the vertical direction of FIG.
AM section, data memory A section, data memory B section, output S
Even if the memory size of the AM section is increased, the address space of each data memory is expanded and the working memory is increased. In addition, even if the horizontal length of FIG. 2 is increased, that is, the number of parallel processor elements is increased,
This parallel number of processor elements is meaningless because it is used in correspondence with the number of pixels in one horizontal scanning period of the applied video signal.

The processing performance of the processor of this architecture is such that the instruction cycle is accelerated or the ALU is parallelized.
Or it could only be done by parallelizing the entire processor. In order to speed up the instruction cycle of the processor of FIG.
Memory A cell 3 and memory B cell 5 by transistors
Instead of (these are the same), a memory cell having a large output as shown in FIG. 5 by using three transistors was used, and thereby the load on the sense amplifier was reduced to speed up the operation. However, it was still a read modify write operation. In FIG.
W is a write access signal line (write word line), and R is a read access signal line (read word line).

This case is intended to solve the conventional drawback that the instruction cycle in this processor is slow. In this case, the memory read and write are set as separate cycles to speed up the instruction cycle.

[0044]

A first means according to the present invention is a linear array type parallel DSP processor,
A linear array parallel DSP processor having a read bit line and a write bit line connected to a memory cell of a data memory unit.

A second means according to the present invention is the linear array parallel DSP processor according to the first means,
At least a SAM (serial access memory) unit, a data memory unit, and an ALU array unit, and a memory read or write that is data exchange between the data memory unit and the ALU array unit are independently performed. It is an array type parallel DSP processor.

A third means according to the present invention is the linear array parallel DSP processor according to the second means.
A linear array parallel DSP processor characterized in that a read line of a memory cell of a data memory unit is connected to an input of an ALU unit and a write line of a memory cell of the data memory unit is connected to an output of an ALU unit. is there.

A fourth means according to the present invention is the linear array parallel DSP processor according to the third means,
The processor is a linear array type parallel DSP processor characterized in that all the processors are SIMD control in which one processor operates in synchronization with one program.

A fifth means according to the present invention is the linear array parallel DSP processor according to the fourth means,
The processor is a linear array type parallel DSP processor characterized by comprising a number of processors corresponding to the horizontal resolution of a video signal, and all the processors process information of one horizontal scanning line in one period.

[0049]

According to this, the S signal for digital signal processing of the video signal of the television etc. by the software program is provided.
The present invention relates to a configuration and control of a programmable linear array type processor of IMD control, and particularly to a linear array type processor of SIMD control, in which a bit line of a data memory of each processor element, which is a component thereof, is written and read. Write and read between the ALU and the data memory of each processor element are pipelined so that each processor element has a dedicated one.
This speeds up the instruction cycle, and during the same instruction cycle, writing and reading for the next processing can be executed simultaneously.

[0050]

FIG. 1 is a model of one processor element of the embodiment. While the conventional example is realized by the model of FIG. 4 based on FIG. 2, the embodiment is realized by the model of FIG. 1 based on FIG.

The difference between the model of FIG. 4 and the model of FIG. 1 is that the memory A cell 3 and the memory B cell 5 (these are the same) are
The memory cell of 3 transistors similar to that of FIG. 5 is used, and the write bit line and the read bit line thereof are dedicated and provided individually.

In the embodiment, the read modify write operation is no longer performed. That is, on one bit line, only reading or writing is performed in each cycle. However, since the number of bit lines is increased compared to the conventional one, the same data transfer is possible. Read operation and write operation related to one data transfer are
The 1-bit register (FF) in the LU cell 4 performs a pipeline operation, and the two operations are divided into two continuous cycles.

That is, one vertical bit line for each processor element from the input SAM section to the ALU array section via the data memory A section in FIG. Via ALU
There are two vertical bit lines for each processor element, a read bit line reaching the array portion and a write bit line extending from the ALU array portion to the data memory A portion. At this time, in the memory A cell 3, one transistor for writing and two transistors for reading are connected to different write bit lines and read bit lines, respectively, unlike FIG.

Further, one vertical bit line for each processor element from the ALU array section to the output SAM section via the data memory B section in FIG.
Output SAM from U array section via data memory B section
To the write bit line and the data memory from the B section to the A section
There are two vertical bit lines for each processor element of the read bit lines reaching the LU array section. At this time, the memory B cell 5 (same as the memory A cell 3) has one transistor for writing and two transistors for reading, which are different from those in FIG. It is connected to the bit line.

Therefore, in the processor of FIG. Input operation by writing input data to the input SAM section. 2. Input SAM by SIMD control of program control unit
Of arithmetic processing by the unit, the data memory A unit, the ALU array unit, the data memory B unit, and the output SAM unit. 3. Output operation by reading output data from the output SAM section. Of the three operations of 1. And 3. Does not change. Below 2. The operation of will be described.

The input data accumulated in the input SAM section for one horizontal scanning period is transferred from the input SAM section to the data memory B section under the control of the program control section as needed in the next one horizontal scanning period. Be transferred. This operation is performed by accessing a required bit of the input SAM section by an input SAM read signal (IR) by a program, and from the input SAM cell 2 of the bit through the read bit line of the upper half of the processor to the ALU cell. It is temporarily stored in the 1-bit register 4 and is delivered to the predetermined bit memory B cell 5 of the data memory B section through the write bit line in the lower half of this processor via the ALU in the next cycle. It is realized by issuing a memory write signal (WB) to the cell 5 and writing.

This data transfer is carried out bit by bit. Although there is nothing to be processed by the ALU at the time of this data movement, it is designed to pass through the ALU cell 4,
At that time, the ALU output control signal (BB) is generated at a necessary timing. Although one data transfer looks like two cycles, the cycle does not increase when a large number of bits are transferred continuously because it is a pipeline.

If necessary, a write signal (RA or RB) and a read signal (W) are written between the data memory A section and the data memory B section to a predetermined memory cell by a program.
You can move the data by issuing A or WB).

For example, in the data transfer from the data memory A section to the data memory B section, first, the data memory A to be moved.
A read signal (R
A) from the memory A cell 3 of the bit, and once stored in the 1-bit register of the ALU cell 4 through the read bit line in the upper half of this processor, and then in the next cycle
The data is sent to a predetermined bit memory B cell 5 of the data memory B section through the write bit line in the lower half of this processor via the LU, and a write signal (WB) is issued to the memory B cell 5 of the bit to write. .

This is also performed for each one bit. Although there is nothing to process with the ALU when moving this data,
It passes through the ALU cell 4, and at that time, the ALU output control signal (BB) is generated at a necessary timing.
Although one data transfer looks like two cycles, the cycle does not increase when a large number of bits are transferred continuously because it is a pipeline.

Therefore, in the data memory A section and the data memory B section, the input data written in the past as described above and the data in the middle of calculation are stored. 1-bit register (FF) in those data or ALU cell 4
It is possible to perform the necessary bit arithmetic processing in the ALU using the data of. The arithmetic operation in this ALU cell 4 is designated by the ALU control signal (ALU-CONT). The result calculated by the ALU cell 4 is stored in the 1-bit register in the ALU cell 4 or written in the data memory A section or the data memory B section as needed.

For example, the data of the memory A cell 3 of a certain bit in the data memory A section and the data of the memory B cell 5 of a certain bit of the data memory B section are added to each other, and the memory B cell of the currently read bit in the data memory B section is added. The case of writing the addition result to 5 is as follows. First, in the first cycle, a read signal (RA) is issued to the memory A cell 3 of a predetermined bit of the data memory A section, and the ALU cell 4 is output from the memory A cell 3 of that bit through the read bit line of the upper half of this processor. It is temporarily stored in one 1-bit register of the ALU input. At the same time, a read signal (R) is similarly sent to the memory B cell 5 of a predetermined bit in the data memory B section.
B) from the memory B cell 5 of that bit, and through the read bit line of the lower half of this processor, and temporarily stores it in another 1-bit register of the ALU input of the ALU cell 4.

Then, in the next cycle, A for addition
A LU control signal (ALU-CONT) is issued, addition is performed by the ALU, and a predetermined bit memory B cell 5 of the data memory B section is passed through the write bit line in the lower half of this processor.
To write to the memory B cell 5 of that bit by issuing a write signal (WB). This is also performed by 1 bit 1 bit. The ALU output control signals (BA and BB) are generated at the required timing. Although one operation looks like two cycles, it is a pipeline and since each data path is used for only one purpose, it is possible to operate a large number of bits consecutively in each cycle. ALU is 3 in the figure.
Input 2 output, 1 input 1 output (explained) is for carry (carry), stored in the 1 bit register before the 3rd ALU input, and the operation result from the lower bit is stored in the next cycle. To make it one higher carry input.

In the ALU array section, from the data memory A section and the data memory B section which are present above and below,
The data is read according to the program, the necessary arithmetic operation or logical operation is performed, and the data is again written to a predetermined address of the data memory A section or the data memory B section. This arithmetic processing is all bit processing, and 1 bit 1 bit processing is advanced.

When the calculation processing for one horizontal scanning period is completed,
The output data for the one horizontal scanning period is output S at the last part of the program within the time for the one horizontal scanning period.
It is necessary to move to the AM section. When it is assumed that the data to be output is in the data memory A section, a read signal (RA) is first issued to a predetermined memory A cell 3 in the first cycle, and the memory A cell 3 of that bit outputs the upper half of this processor. It is temporarily stored in the 1-bit register of the ALU cell 4 through the read bit line of, and is output through the write bit line of the lower half of this processor via the ALU in the next cycle. The write signal (OW) is delivered to the output SAM cell 6 and written to the output SAM cell 6.

In this case as well, 1-bit 1-bit data is transferred via the vertical bit lines. Also at this time, there is nothing to be processed by the ALU at the time of data movement, but the data is passed through the ALU cell 4, and at that time, the ALU output control signal (BB) is generated at a necessary timing. Although one data transfer looks like two cycles, the cycle does not increase when a large number of bits are transferred continuously because it is a pipeline.

As described above, during the time of one horizontal scanning period, reading of the input data accumulated in the input SAM section, necessary arithmetic processing, necessary data movement, and output S
The writing of output data to the AM section is controlled by the SIMD control program in units of bits. This program process is repeated in units of horizontal scanning period.
Descriptions of other points that are the same as those of the conventional example are omitted.

Some variations will be supplemented. In the above description, there is no case where the data of the input SAM section is used as the arithmetic input in the ALU and the ALU output is written to the output SAM section, but these are also possible from the configuration of the drawing of this embodiment.

In the above explanation, the two required for the ALU operation are
It was explained that one operation input and one operation output among one operation input and one operation output are matched with the same address on the memory cell, but the sum of these two operation inputs and one operation output is described. It is possible that the addresses on the three memory cells are all different from the configuration shown in the drawing of the embodiment.

[0070]

In the configuration of the conventional example, one cycle is long because the operation of each memory cell of the input SAM section, the data memory A section, the data memory B section, and the output SAM section is the read modify write operation. However, according to the embodiment of the present application, read and write are different cycles, and the cycle of one cycle is shortened.

It is difficult to reduce it to less than half, but 60 to 70
%, Which is expected to be 1.5 times faster. This directly improves the processing performance of the processor. At this time, 1-bit data transfer and 1-bit operation seem to take 2 cycles, but since the pipeline operation is actually possible, the processing cycle does not increase.

In the embodiment, the number of transistors does not increase when comparing the memory cells of the data memory A portion and the data memory B portion in FIG. 5 in the conventional example (FIG. 4).
In the embodiment and the conventional example (FIG. 4), the increase in the vertical bit line in each processor element is an increase in hardware, and this is minor.

[Brief description of drawings]

FIG. 1 is a model diagram of an example of a processor element of a linear array parallel DSP processor according to the present invention.

FIG. 2 is a configuration diagram of a linear array type processor.

FIG. 3 is a diagram illustrating a configuration of a general processor.

FIG. 4 is a model diagram of a conventional processor element.

FIG. 5 is another memory cell configuration diagram.

[Explanation of symbols]

 1 Input Pointer Cell 2 Input SAM Cell 3 Memory A Cell 4 ALU Cell 5 Memory B Cell 6 Output SAM Cell 7 Output Pointer Cell

Claims (5)

[Claims] 1. A linear array type parallel DSP processor having a read bit line and a write bit line connected to a memory cell of a data memory section in the linear array type parallel DSP processor. 2. The linear array type parallel D according to claim 1.
In the SP processor, at least a SAM (serial access memory) unit, a data memory unit, and an ALU array unit are provided, and memory reading or writing, which is data exchange between the data memory unit and the ALU array unit, can be independently performed. Characteristic linear array type parallel DSP processor. 3. The linear array type parallel D according to claim 2.
In the SP processor, the read line of the memory cell of the data memory unit is connected to the input of the ALU unit, and the write line of the memory cell of the data memory unit is connected to the output of the ALU unit. Parallel DSP processor. 4. The linear array type parallel D according to claim 3.
In the SP processor, the processor is SIMD control in which all the processors operate in synchronization with one program, which is a linear array parallel DSP processor. 5. The linear array type parallel D according to claim 4.
In the SP processor, the processor is composed of a number of processors corresponding to the horizontal resolution of a video signal, and all the processors process information of one horizontal scanning line in one period, which is a linear array parallel DSP processor.