JPH0647577A - Solder material and method for joining - Google Patents

Solder material and method for joining

Info

Publication number
JPH0647577A
JPH0647577A JP4189194A JP18919492A JPH0647577A JP H0647577 A JPH0647577 A JP H0647577A JP 4189194 A JP4189194 A JP 4189194A JP 18919492 A JP18919492 A JP 18919492A JP H0647577 A JPH0647577 A JP H0647577A
Authority
JP
Japan
Prior art keywords
layer
solder
solder layer
melting point
joined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4189194A
Other languages
Japanese (ja)
Inventor
Shunichi Abe
俊一 阿部
Naoto Ueda
直人 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4189194A priority Critical patent/JPH0647577A/en
Publication of JPH0647577A publication Critical patent/JPH0647577A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/011Apparatus therefor
    • H10W72/0113Apparatus for manufacturing die-attach connectors

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】 【目的】 共晶半田層7aを高融点化する際の熱処理時
間を極めて短くする。 【構成】 蒸着又はスパッタ法により薄いSn層5が形
成された半導体素子1と、Pb層6が形成されたダイパ
ット2とを重ね合わせ、Sn層及びPb層の融点以下の
温度に加熱して共晶半田層7aを形成した後、この共晶
半田層を高融点化するために極めて短時間熱処理する。
(57) [Summary] [Purpose] The heat treatment time for raising the melting point of the eutectic solder layer 7a is extremely shortened. [Structure] A semiconductor element 1 having a thin Sn layer 5 formed by vapor deposition or a sputtering method and a die pad 2 having a Pb layer 6 formed thereon are superposed and heated to a temperature equal to or lower than the melting points of the Sn layer and the Pb layer. After forming the eutectic solder layer 7a, the eutectic solder layer is heat-treated for an extremely short time in order to have a high melting point.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、一方の被接合部材例
えば半導体素子と、他方の被接合部材例えば基材とを接
合するために用いられる半田材料及び接合方法に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder material and a joining method used for joining one member to be joined, such as a semiconductor element, and the other member to be joined, such as a base material.

【0002】[0002]

【従来の技術】図2は例えば特願平3−4832号に開
示されたものと同様な従来の半導体装置の構成を示す断
面図である。図において、1は一方の被接合部材として
の半導体素子、2は他方の被接合部材としての基材例え
ばダイパット、3はこれら半導体素子1とダイパット2
とを接合するための三層半田であって、例えば組成が9
5Pb−5Snで厚みが50μmの高融点(305℃)
半田3a及びこの95Pb−5Sn半田3aの上下両面
にメッキにより形成され、例えば組成が37Pb−63
Snで厚みが10μmの共晶半田3bから成る。そして
4は載置されたダイパット2を加熱するためのヒートブ
ロックであり、これは半導体装置の一部ではない。
2. Description of the Related Art FIG. 2 is a sectional view showing a structure of a conventional semiconductor device similar to that disclosed in, for example, Japanese Patent Application No. 3-4832. In the figure, 1 is a semiconductor element as one member to be joined, 2 is a base material such as a die pad as the other member to be joined, 3 is these semiconductor element 1 and die pad 2
A three-layer solder for joining and
High melting point of 5Pb-5Sn and thickness of 50μm (305 ℃)
The solder 3a and the 95Pb-5Sn solder 3a are formed on both upper and lower surfaces by plating. For example, the composition is 37Pb-63.
The eutectic solder 3b is made of Sn and has a thickness of 10 μm. Reference numeral 4 denotes a heat block for heating the mounted die pad 2, which is not a part of the semiconductor device.

【0003】このような半導体装置では、半導体素子1
とダイパット2とを三層半田3を介して重ね合わせ、還
元性雰囲気中で共晶半田3bの融点183℃以上で且つ
半田3aの融点305℃以下の温度例えば200℃にヒ
ートブロック4で加熱し、共晶半田3bのみを溶融させ
て半導体素子1とダイパット2を接合する。その後、上
述した温度200℃に保持することによって共晶半田3
bと半田3aとの間でPbとSnとが相互拡散を起こ
し、図3のPb−Sn系状態図からわかるように、共晶
半田3b中のSn濃度が18%以下になると凝固する。
その後Sn濃度の低下に伴い固相線温度直下の温度にな
るように温度を上昇させると、Snの拡散速度は更に加
速される。図3に示すように最終的には半田3aと共晶
半田3bとの組成が同じになり、最初の状態の共晶半田
3bよりも三層半田3の融点が高くなる。このため半田
3aが溶融されないことによる間隔保持の効果に加え
て、接合時の加熱温度200℃より高い耐熱性を有する
半導体装置を得ることができる。
In such a semiconductor device, the semiconductor element 1
And the die pad 2 are overlapped with each other with the three-layer solder 3 interposed therebetween, and heated in a reducing atmosphere to a temperature of, for example, 200 ° C. which is a melting point of the eutectic solder 3b of 183 ° C. or more and a melting point of the solder 3a of 305 ° C. or less in the heat block 4. , The eutectic solder 3b alone is melted to bond the semiconductor element 1 and the die pad 2 together. Then, by maintaining the above-mentioned temperature of 200 ° C.
Pb and Sn interdiffuse between b and the solder 3a, and solidify when the Sn concentration in the eutectic solder 3b becomes 18% or less, as can be seen from the Pb-Sn system state diagram of FIG.
Then, when the temperature is increased so as to reach a temperature just below the solidus temperature as the Sn concentration decreases, the diffusion rate of Sn is further accelerated. As shown in FIG. 3, finally, the compositions of the solder 3a and the eutectic solder 3b become the same, and the melting point of the three-layer solder 3 becomes higher than that of the eutectic solder 3b in the initial state. Therefore, it is possible to obtain a semiconductor device having a heat resistance higher than the heating temperature of 200 ° C. at the time of joining, in addition to the effect of maintaining the gap by not melting the solder 3a.

【0004】なお、三層半田3の融点は、共晶半田3b
と半田3aの厚みによって決定される三層半田全体のP
bとSnの組成比によって決定され且つ制御できる。そ
の後、ヒートブロック4から半導体装置を取り上げ、半
導体素子1上の電極(図示しない)と外部リード(図示
しない)とを金線(図示しない)で接続するワイヤボン
ド工程、半導体装置を封止するモールド樹脂封止工程等
の諸工程を経て半導体装置を完成させる。
The melting point of the three-layer solder 3 is eutectic solder 3b.
And P of the entire three-layer solder determined by the thickness of the solder 3a
It can be determined and controlled by the composition ratio of b and Sn. After that, the semiconductor device is picked up from the heat block 4, a wire bonding step of connecting an electrode (not shown) on the semiconductor element 1 and an external lead (not shown) with a gold wire (not shown), a mold for sealing the semiconductor device. A semiconductor device is completed through various steps such as a resin sealing step.

【0005】[0005]

【発明が解決しようとする課題】上述したような従来の
半導体装置では、三層半田3の共晶半田3bを半田3a
の表面にメッキにて形成するので、共晶半田3bの厚み
を極めて薄く且つ精度良く制御することは大変難しく、
目標とする厚みを10μmとする場合5μm〜20μmと
バラツキ、厚みが目標値よりも厚くなる傾向があった。
そのため、三層半田3の高融点化に必要な熱処理時間も
図4からわかるようにバラツクのみならず、長時間の熱
処理が必要であるという問題点があった。なお、図4は
実測値と良く相関がとれたシミュレーション結果を示す
図である。
In the conventional semiconductor device as described above, the eutectic solder 3b of the three-layer solder 3 is replaced by the solder 3a.
It is very difficult to control the thickness of the eutectic solder 3b very thinly and accurately because it is formed on the surface of
When the target thickness was 10 μm, the thickness varied from 5 μm to 20 μm, and the thickness tended to become thicker than the target value.
Therefore, there is a problem that the heat treatment time required for raising the melting point of the three-layer solder 3 is not only varied as shown in FIG. Note that FIG. 4 is a diagram showing a simulation result that is well correlated with the actual measurement value.

【0006】この発明は、このような問題点を解決する
ためになされたもので、二層半田の高融点化に必要な熱
処理時間のバラツキを殆んど無くし且つ熱処理時間その
ものを短縮することができる半導体装置接合用の半田材
料及び接合方法を得ることを目的としている。
The present invention has been made in order to solve such a problem, and it is possible to almost eliminate the variation in heat treatment time required for raising the melting point of a two-layer solder and to shorten the heat treatment time itself. An object of the present invention is to obtain a solder material and a joining method for joining a semiconductor device that can be used.

【0007】[0007]

【課題を解決するための手段】この発明に係る半田材料
は、一方の被接合部材に蒸着又はスパッタ法により形成
された薄い第1の半田層と、他方の被接合部材に形成さ
れ、前記第1の半田層よりも高い融点及び厚い厚みを有
する第2の半田層と、を備えたものである。
A solder material according to the present invention comprises a thin first solder layer formed on one member to be joined by vapor deposition or a sputtering method and another thin member to be joined. A second solder layer having a higher melting point and a larger thickness than the first solder layer.

【0008】この発明に係る接合方法は、一方の被接合
部材に蒸着又はスパッタ法により薄い第1の半田層を形
成するステップと、他方の被接合部材に前記第1の半田
層よりも高い融点及び厚い厚みを有する第2の半田層を
形成するステップと、両方の被接合部材を重ね合わせ、
前記第1及び第2の半田層の融点以下の温度に加熱して
共晶半田層を形成するステップと、前記共晶半田層を含
む二層半田層を加熱して高融点化させると共に前記両方
の被接合部材を接合するステップと、を含むものであ
る。
In the joining method according to the present invention, a step of forming a thin first solder layer on one joined member by vapor deposition or a sputtering method and a melting point higher than that of the first solder layer on the other joined member. And a step of forming a second solder layer having a large thickness, and superposing both members to be joined,
Forming a eutectic solder layer by heating to a temperature equal to or lower than the melting points of the first and second solder layers, and heating the two-layer solder layer including the eutectic solder layer to increase the melting point and And a step of joining the members to be joined.

【0009】[0009]

【作用】この発明の半田材料では、第1の半田層を薄く
形成できる。この発明の接合方法では、第1の半田層ひ
いては共晶半田層を薄く形成できるので、共晶半田層を
含む二層半田の高融点化処理時間を極めて短縮できる。
With the solder material of this invention, the first solder layer can be formed thin. According to the joining method of the present invention, since the first solder layer and thus the eutectic solder layer can be formed thin, the high melting point treatment time of the two-layer solder including the eutectic solder layer can be extremely shortened.

【0010】[0010]

【実施例】【Example】

実施例1.以下、この発明をその一実施例について説明
する。図1はこの発明の一実施例を用いて半導体装置を
製造する工程を説明する断面図である。図1のAにおい
て、1,2,4は従来例と全く同じ半導体素子、ダイパ
ット、ヒートブロックである。5は半導体素子1の裏面
に蒸着又はスパッタ法により形成された1μm程度の第
1の半田層例えばSn層である。このようにSn層5を
蒸着又はスパッタ法により形成すると、その厚みを1μ
mと極めて薄くできるのみならず、バラツキを目標値±
10%程度に抑えることができた。6はダイパット2の
表面にメッキにより形成された10μm〜20μm例えば
20μm程度の第2の半田層例えばPb層である。
Example 1. The present invention will be described below with reference to an embodiment thereof. FIG. 1 is a cross-sectional view for explaining a process of manufacturing a semiconductor device using an embodiment of the present invention. In FIG. 1A, reference numerals 1, 2, and 4 are the same semiconductor elements, die pads, and heat blocks as in the conventional example. Reference numeral 5 is a first solder layer, for example, a Sn layer of about 1 μm formed on the back surface of the semiconductor element 1 by vapor deposition or sputtering. When the Sn layer 5 is formed by vapor deposition or sputtering in this way, its thickness is 1 μm.
Not only can it be made extremely thin at m
It could be suppressed to about 10%. Reference numeral 6 denotes a second solder layer, for example, a Pb layer having a thickness of 10 μm to 20 μm, for example, 20 μm, which is formed on the surface of the die pad 2 by plating.

【0011】このような半導体装置では、Sn層5が形
成された半導体素子1と、Pb層6が形成されたダイパ
ット2とを重ね合わせ、還元性雰囲気中でSn層5の融
点232℃及びPb層6の融点327℃以下で、Pb−
Sn半田系における共晶温度183℃以上の温度例えば
190℃にヒートブロック4で加熱する。そうすると、
Sn層5とPb層6との間で反応が起こり、その界面に
Pb−Sn共晶半田層7aが形成される。もう少し詳し
く云えば、厚み1μmのSn層5と厚み20μmのPb層
6とを190℃に加熱すると、図1のBに示すように厚
み1μmの共晶半田層7aが形成されると共に、Pb層
6はその厚みが20μmから19μmに減少する(この厚
みが減少したPb層を符号7bで表す)。なお、共晶半
田層7aはPbとSnの相互拡散によって生じられるの
で、1μmと極めて薄い。その後、従来例と同様に熱処
理を行ってPbとSnの相互拡散を更に進行させること
により共晶半田層7a及び厚みが減少したPb層7bか
ら成る二層半田7の融点が高くなり、高い耐熱性を有す
る半導体装置が得られることになる。この時に必要な熱
処理時間は、共晶半田層7aの厚みによって一義的に決
まるので、図4から明らかなように従来十数時間かかっ
たのが、わずか十分程度ですみ、極めて短縮化される。
In such a semiconductor device, the semiconductor element 1 on which the Sn layer 5 is formed and the die pad 2 on which the Pb layer 6 is formed are overlapped with each other, and the melting point of the Sn layer 5 is 232 ° C. and Pb is Pb in a reducing atmosphere. When the melting point of the layer 6 is 327 ° C. or lower, Pb-
The eutectic temperature in the Sn solder system is heated by the heat block 4 to a temperature of 183 ° C. or higher, for example, 190 ° C. Then,
A reaction occurs between the Sn layer 5 and the Pb layer 6, and a Pb-Sn eutectic solder layer 7a is formed at the interface. More specifically, when the Sn layer 5 having a thickness of 1 μm and the Pb layer 6 having a thickness of 20 μm are heated to 190 ° C., the eutectic solder layer 7a having a thickness of 1 μm is formed as shown in FIG. No. 6 has its thickness reduced from 20 μm to 19 μm (this reduced Pb layer is represented by reference numeral 7b). Since the eutectic solder layer 7a is generated by the mutual diffusion of Pb and Sn, it is extremely thin as 1 μm. After that, heat treatment is performed in the same manner as in the conventional example to further promote the mutual diffusion of Pb and Sn, so that the melting point of the two-layer solder 7 composed of the eutectic solder layer 7a and the Pb layer 7b having the reduced thickness is increased, resulting in high heat resistance. A semiconductor device having properties is obtained. Since the heat treatment time required at this time is uniquely determined by the thickness of the eutectic solder layer 7a, as is apparent from FIG.

【0012】実施例2.実施例1では半導体素子1にS
n層5を、ダイパット2にPb層6を設けたが、その逆
でも同様の効果が得られる。
Example 2. In the first embodiment, S is added to the semiconductor element 1.
Although the n layer 5 and the Pb layer 6 are provided on the die pad 2, the same effect can be obtained by vice versa.

【0013】実施例3.実施例1ではPb層6をメッキ
にて形成したが、蒸着、スパッタ法、又は圧接等で形成
しても良い。
Embodiment 3. In the first embodiment, the Pb layer 6 is formed by plating, but it may be formed by vapor deposition, sputtering, pressure welding, or the like.

【0014】実施例4.実施例1では半田層としてPb
−Sn系を用いたが、In−Pb系、Pb−Sb系、S
n−Bi系、Sn−Au系等が考えられる。
Example 4. In Example 1, Pb was used as the solder layer.
-Sn system was used, but In-Pb system, Pb-Sb system, S
An n-Bi system, a Sn-Au system, etc. are considered.

【0015】[0015]

【発明の効果】以上、詳しく説明したように、この発明
の半田材料は、一方の被接合部材に蒸着又はスパッタ法
により形成された薄い第1の半田層と、他方の被接合部
材に形成され、前記第1の半田層よりも高い融点及び厚
い厚みを有する第2の半田層と、を備えたので、またこ
の発明の接合方法は、一方の被接合部材に蒸着又はスパ
ッタ法により薄い第1の半田層を形成するステップと、
他方の被接合部材に前記第1の半田層よりも高い融点及
び厚い厚みを有する第2の半田層を形成するステップ
と、両方の被接合部材を重ね合わせ、前記第1及び第2
の半田層の融点以下の温度に加熱して共晶半田層を形成
するステップと、前記共晶半田層を含む二層半田層を加
熱して高融点化させると共に前記両方の被接合部材を接
合するステップと、を含むので、第1の半田層ひいては
共晶半田層を薄く形成でき、その結果として共晶半田層
を含む二層半田の高融点化処理時間を極めて短縮できる
という効果を奏する。
As described above in detail, the solder material of the present invention is formed on one of the members to be joined by a thin first solder layer formed by vapor deposition or sputtering and the other member to be joined. And a second solder layer having a higher melting point and a larger thickness than the first solder layer, and the joining method of the present invention is a thin first layer formed by vapor deposition or sputtering on one member to be joined. Forming a solder layer of
Forming a second solder layer having a melting point and a thicker thickness than the first solder layer on the other member to be joined, and superposing both members to be joined,
Forming a eutectic solder layer by heating the solder layer to a temperature equal to or lower than the melting point of the solder layer, and heating the two-layer solder layer including the eutectic solder layer to increase the melting point and joining both members to be joined. The first solder layer and thus the eutectic solder layer can be thinly formed, and as a result, the high melting point treatment time of the two-layer solder including the eutectic solder layer can be extremely shortened.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を説明すための断面図であ
る。
FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention.

【図2】三層半田を用いた従来の半導体装置を示す断面
図である。
FIG. 2 is a sectional view showing a conventional semiconductor device using three-layer solder.

【図3】三層半田の凝固過程を説明する状態図である。FIG. 3 is a state diagram illustrating a solidification process of three-layer solder.

【図4】共晶半田の厚みと熱処理時間の関係を示すグラ
フである。
FIG. 4 is a graph showing the relationship between the thickness of eutectic solder and the heat treatment time.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 ダイパット 5 Sn層 6 Pb層 4 二層半田 7a Pb−Sn共晶半田層 1 semiconductor element 2 die pad 5 Sn layer 6 Pb layer 4 two-layer solder 7a Pb-Sn eutectic solder layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 一方の被接合部材に蒸着又はスパッタ法
により形成された薄い第1の半田層と、 他方の被接合部材に形成され、前記第1の半田層よりも
高い融点及び厚い厚みを有する第2の半田層と、 を備えたことを特徴とする半田材料。
1. A thin first solder layer formed on one of the members to be joined by vapor deposition or sputtering, and a melting point and a thickness thicker than the first solder layer formed on the other member to be joined. And a second solder layer having the solder layer.
【請求項2】 一方の被接合部材に蒸着又はスパッタ法
により薄い第1の半田層を形成するステップと、 他方の被接合部材に前記第1の半田層よりも高い融点及
び厚い厚みを有する第2の半田層を形成するステップ
と、 両方の被接合部材を重ね合わせ、前記第1及び第2の半
田層の融点以下の温度に加熱して共晶半田層を形成する
ステップと、 前記共晶半田層を含む二層半田層を加熱して高融点化さ
せると共に前記両方の被接合部材を接合するステップ
と、 を含むことを特徴とする接合方法。
2. A step of forming a thin first solder layer on one of the members to be joined by vapor deposition or a sputtering method, and a step of forming a thin first solder layer on the other member to be joined, which has a higher melting point and a greater thickness than the first solder layer. A step of forming a second solder layer, a step of forming a eutectic solder layer by superposing both members to be joined and heating to a temperature equal to or lower than a melting point of the first and second solder layers; And a step of heating the two-layer solder layer including the solder layer to raise the melting point and joining the both members to be joined together.
JP4189194A 1992-07-16 1992-07-16 Solder material and method for joining Pending JPH0647577A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4189194A JPH0647577A (en) 1992-07-16 1992-07-16 Solder material and method for joining

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4189194A JPH0647577A (en) 1992-07-16 1992-07-16 Solder material and method for joining

Publications (1)

Publication Number Publication Date
JPH0647577A true JPH0647577A (en) 1994-02-22

Family

ID=16237096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4189194A Pending JPH0647577A (en) 1992-07-16 1992-07-16 Solder material and method for joining

Country Status (1)

Country Link
JP (1) JPH0647577A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002028574A1 (en) * 2000-10-02 2002-04-11 Asahi Kasei Kabushiki Kaisha Functional alloy particles

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002028574A1 (en) * 2000-10-02 2002-04-11 Asahi Kasei Kabushiki Kaisha Functional alloy particles
US7169209B2 (en) 2000-10-02 2007-01-30 Asahi Kasei Kabushiki Kaisha Functional alloy particles

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