JPH0648868Y2 - Semiconductor device cooling structure - Google Patents

Semiconductor device cooling structure

Info

Publication number
JPH0648868Y2
JPH0648868Y2 JP1989071921U JP7192189U JPH0648868Y2 JP H0648868 Y2 JPH0648868 Y2 JP H0648868Y2 JP 1989071921 U JP1989071921 U JP 1989071921U JP 7192189 U JP7192189 U JP 7192189U JP H0648868 Y2 JPH0648868 Y2 JP H0648868Y2
Authority
JP
Japan
Prior art keywords
cooling
semiconductor chips
refrigerant
cooling structure
coolant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1989071921U
Other languages
Japanese (ja)
Other versions
JPH0310548U (en
Inventor
貴志男 横内
光隆 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1989071921U priority Critical patent/JPH0648868Y2/en
Publication of JPH0310548U publication Critical patent/JPH0310548U/ja
Application granted granted Critical
Publication of JPH0648868Y2 publication Critical patent/JPH0648868Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Description

【考案の詳細な説明】 〔概要〕 多数の半導体チップをセラミック回路基板に搭載し、強
制液冷する冷却構造に関し、 効率よく半導体チップを冷却することを目的とし、 配線基板(5)上にマトリックス状に装着してある複数
の半導体チップ(6)を格納するパッケージの蓋部
(9)に冷媒の流入口(7)と流出口(8)とが設けて
あり、配列している前記半導体チップ(6)に対して冷
媒を一定方向に循環して冷却する構造体において、半導
体チップ(6)に近接し、流路を介して対向する蓋部
(9)の天井部にそれぞれ鋸歯状の突起(10)を設ける
ことを特徴として半導体装置の冷却構造を構成する。
DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a cooling structure in which a large number of semiconductor chips are mounted on a ceramic circuit board and forced liquid cooling is performed, a matrix is formed on a wiring board (5) for the purpose of efficiently cooling the semiconductor chips. A plurality of semiconductor chips (6) mounted in a shape are provided with a coolant inlet (7) and a coolant outlet (8) in a lid (9) of a package, and the semiconductor chips are arranged. In a structure that circulates a cooling medium in a certain direction with respect to (6) to cool, a saw-toothed protrusion is provided on a ceiling part of a lid part (9) that is close to a semiconductor chip (6) and faces through a flow path. A cooling structure for a semiconductor device is configured by providing (10).

〔産業上の利用分野〕[Industrial application field]

本考案は冷媒を強制循環させて多数の半導体チップを冷
却する半導体装置の冷却構造に関する。
The present invention relates to a semiconductor device cooling structure for cooling a large number of semiconductor chips by forcibly circulating a coolant.

情報処理装置の処理能力をより増大するため、半導体装
置は大容量化すると共に実装密度も向上している。
In order to further increase the processing capability of the information processing device, the semiconductor device has a large capacity and the packaging density is also improved.

すなわち、多数の単位素子を集積化して構成される半導
体チップは単位素子の小形化と素子数の増大が行われて
LSIやVLSIが実用化されている。
That is, a semiconductor chip configured by integrating a large number of unit elements has been downsized and the number of elements has been increased.
LSI and VLSI are in practical use.

また、パッシベーション技術の進歩と共に実装方法も改
良され、当初はハーメチックシールパッケージ型の外装
方法が採られていたのに対し、フリップチップタイプな
どの半導体チップをセラミック多層回路基板上に密に配
列してLSIモジュールとする形態が採られるようになっ
た。
Also, with the progress of passivation technology, the mounting method has been improved, and at the beginning, the hermetically sealed package type outer packaging method was adopted.However, semiconductor chips such as flip chip type are closely arranged on the ceramic multilayer circuit board. LSI modules have come to be adopted.

このように半導体チップの集積化と高密度実装が進むに
従ってLSIモジールの発熱量は膨大となり、従来の強制
空冷に代わって強制液冷が必要となった。
In this way, as the integration of semiconductor chips and high-density mounting progress, the amount of heat generated by the LSI module becomes enormous, requiring forced liquid cooling instead of conventional forced air cooling.

〔従来の技術〕[Conventional technology]

従来のLSIチップの使用中における発熱量は4ワット
(W)程度であったが、集積度が増加したVLSIにおいて
は約10Wに及んでいる。
The amount of heat generated during the use of conventional LSI chips was about 4 watts (W), but it has reached about 10 W in VLSIs with increased integration.

そのため、このような半導体チップが配列しているLSI
モジュールにおいては冷媒を循環させ、強制冷却する方
法が必要となった。
Therefore, LSIs in which such semiconductor chips are arranged
In the module, it was necessary to circulate the refrigerant and to forcibly cool it.

こゝで、冷媒としては非腐蝕性、非解離性で沸点がLSI
モジュールの最高使用温度である85℃以下のもの、例え
ば沸点が30℃のC5F12,沸点が56℃のC6F14などが適して
いる。
Here, the refrigerant is non-corrosive, non-dissociative and has a boiling point of LSI.
A module with a maximum operating temperature of 85 ° C or lower, such as C 5 F 12 with a boiling point of 30 ° C and C 6 F 14 with a boiling point of 56 ° C, is suitable.

さて、従来の冷却構造はマトリックス状に配列している
多数の半導体チップを隔壁により複数列に分割したパッ
ケージ構造をとり、冷媒を一定の方向に流し、排出した
冷媒はポンプと熱交換器を通して冷却させながら循環さ
せる構造が採られていた。
Now, the conventional cooling structure has a package structure in which a large number of semiconductor chips arranged in a matrix are divided into multiple rows by partition walls, the refrigerant is flowed in a certain direction, and the discharged refrigerant is cooled through a pump and a heat exchanger. It had a structure that allows it to circulate while allowing it to move.

こゝで隔壁が必要な理由は冷媒の流路を作って整流する
ことにより各半導体チップに対する冷却効率を均一化す
るためである。
The reason why the partition wall is required is that the cooling efficiency for each semiconductor chip is made uniform by forming a flow path of the coolant and rectifying the flow path.

この冷却方式は冷媒を強制循環させる構造をとっている
ために、従来の半導体チップの発熱によって、これと接
する冷媒を温度上昇させ、これにより自然対流させる
か、或いは冷媒の沸騰による対流によってチップを冷却
させる方式に較べれば冷却能力は遥かに優れている。
Since this cooling system has a structure in which the coolant is forcedly circulated, the temperature of the coolant in contact with the conventional semiconductor chip is raised by the heat generated by the conventional semiconductor chip, whereby natural convection is caused or the chip is convected by the boiling of the coolant. The cooling capacity is far superior to the cooling method.

然し、半導体チップの集積度が益々向上している現在、
液冷により冷却効果を最大限にまで向上させた冷却構造
を開発することが必要である。
However, as the integration of semiconductor chips is increasing,
It is necessary to develop a cooling structure that maximizes the cooling effect by liquid cooling.

〔考案が解決しようとする課題〕[Problems to be solved by the device]

マトリックス状に配列している半導体チップをパッケー
ジに設けてある隔壁により分割して複数の流路を作り、
冷媒を循環させて半導体チップを冷却する場合に、冷却
効率を向上させるには冷媒の境界層を除去することであ
る。
The semiconductor chips arranged in a matrix are divided by the partition walls provided in the package to form a plurality of flow paths,
When cooling the semiconductor chip by circulating the cooling medium, the boundary layer of the cooling medium is removed in order to improve the cooling efficiency.

第2図は境界層の存在を説明する断面模式図であって、
パイプ1の中を流体が流れる場合、矢印で示すように流
速2は中心部が最も速く、管壁に近づくに従って遅くな
り、管壁3においては流速は殆ど0となる。
FIG. 2 is a schematic sectional view explaining the existence of a boundary layer,
When the fluid flows in the pipe 1, the flow velocity 2 is highest at the center as shown by the arrow, and becomes slower as it approaches the pipe wall, and the flow velocity at the pipe wall 3 becomes almost zero.

この理由は粘性をもつ流体の管壁との摩擦による。The reason for this is the friction of the viscous fluid with the tube wall.

そこで、この冷媒の境界層の影響を如何にして減少させ
るかゞ解決を要する課題である。
Therefore, how to reduce the influence of the boundary layer of the refrigerant is a problem that needs to be solved.

〔課題を解決するための手段〕[Means for Solving the Problems]

上記の問題は配線基板上にマトリックス状に装着してあ
る複数の半導体チップを格納するパッケージに冷媒の流
入口と流出口とが設けてあり、配列している半導体チッ
プに対して冷媒を一定方向に循環して冷却する構造体に
おいて、半導体チップに近接し、流路を介して対向する
パッケージの天井部にそれぞれ鋸歯状の突起を設けた半
導体装置の冷却構造をとることにより解決することがで
きる。
The above problem is that a package for storing a plurality of semiconductor chips mounted in a matrix on a wiring board is provided with a coolant inlet and a coolant outlet, and the coolant is directed in a fixed direction with respect to the arranged semiconductor chips. This can be solved by adopting a cooling structure of a semiconductor device in which a saw-toothed protrusion is provided on each ceiling portion of a package which is close to the semiconductor chip and faces through a flow path .

〔作用〕[Action]

本考案に係る冷却構造は強制循環させている冷媒に乱流
を生じさせ、これにより冷媒の境界層を剥き取るもので
ある。
The cooling structure according to the present invention creates a turbulent flow in the forcedly circulated refrigerant, thereby stripping the boundary layer of the refrigerant.

第1図は本考案に係る冷却構造の原理図であって、多数
の入出力用のリードピン4を備えた配線基板5があり、
この上にフリップチップタイプの半導体チップ6が装着
されており、この配線基板5を覆うようににして冷媒の
流入口7と流出口8を備えたパッケージの蓋部9が設け
られている。
FIG. 1 is a principle diagram of a cooling structure according to the present invention, in which there is a wiring board 5 having a large number of input / output lead pins 4,
A flip chip type semiconductor chip 6 is mounted thereon, and a package lid 9 having a coolant inlet 7 and a coolant outlet 8 is provided so as to cover the wiring board 5.

こゝで、従来は図示を省略したポンプにより低沸点の冷
媒を流入口7から圧入して流出口8より吸引して循環さ
せていたが、本考案に係る冷却構造は流路を介して半導
体チップ6と対向するパッケージの端部9の天井部に鋸
歯状の突起10を設けるものである。
Here, conventionally, a pump (not shown) was used to pressurize a low-boiling-point refrigerant from the inlet port 7 and suck it from the outlet port 8 to circulate it. A saw-toothed protrusion 10 is provided on the ceiling of the end 9 of the package that faces the chip 6.

考案者等は冷媒の境界層を除去する方法として、 冷媒を沸騰させて除去する。As a method of removing the boundary layer of the refrigerant, the inventors have boiled the refrigerant to remove it.

冷媒に乱流を起こさせて除去する。Remove the turbulent flow in the refrigerant.

の二つの方法があるが、両者を併用することにより冷却
効率を向上させるものである。
There are two methods, but the combined use of both methods improves the cooling efficiency.

すなわち、の沸騰による方法は半導体チップ6と冷媒
との境界で気泡を生じ、これにより境界層が破れること
で、従来より行われているが、の乱流による方法は冷
媒が鋸歯状の突起10と半導体チップ6との狭い隙間を通
り抜けて広がることにより渦を生じさせ、この渦により
冷媒の境界層を剥ぎ取るものである。
That is, the method using boiling has generated air bubbles at the boundary between the semiconductor chip 6 and the coolant, thereby breaking the boundary layer, and the method using turbulence has used the method using turbulent flow. The vortex is generated by spreading through a narrow gap between the semiconductor chip 6 and the semiconductor chip 6, and the vortex strips the boundary layer of the refrigerant.

このためには鋸歯状の突起10と半導体チップ6との隙間
は狭いことが必要条件となる。
For this purpose, it is a necessary condition that the gap between the saw-toothed protrusion 10 and the semiconductor chip 6 is narrow.

本考案は半導体チップ6に通電すると発熱により冷媒の
沸騰が起こることゝ、冷媒の乱流により冷媒の境界層が
破れることを利用して冷却効率の向上を実現させるもの
である。
The present invention realizes the improvement of cooling efficiency by utilizing the fact that when the semiconductor chip 6 is energized, the refrigerant boils due to heat generation and that the boundary layer of the refrigerant is broken by the turbulent flow of the refrigerant.

〔実施例〕〔Example〕

第3図は本考案に係る冷却構造の断面図(A)と蓋部内
部の平面図(B)である。
FIG. 3 is a sectional view (A) of the cooling structure according to the present invention and a plan view (B) of the inside of the lid.

多層配線を施したアルミナセラミックスによりなる配線
基板12の下側には多数の入出力用のリードピン6が設け
てあるが、この配線基板12の上には4×4個のフリップ
チップタイプの半導体チップ6が装着されており、この
上に断面が鋸歯状の突起10と隔壁13および冷媒の流入口
7と流出口8とを備えた蓋部14を当接して一体し、パッ
ケージを形成した。
A large number of input / output lead pins 6 are provided on the lower side of the wiring board 12 made of alumina ceramic with multi-layered wiring, and 4 × 4 flip-chip type semiconductor chips are provided on the wiring board 12. 6 is attached, and a lid portion 14 provided with a projection 10 having a saw-tooth cross section, a partition wall 13, and an inlet 7 and an outlet 8 for the coolant is brought into contact with and integrated with each other to form a package.

こゝで、鋸歯状の突起10の高さとピッチはそれぞれ2mm
づつとして、鋸歯状の突起10と半導体チップ6の表面と
の間隔は0.5mmになるようにした。
Here, the height and pitch of the serrated protrusions 10 are 2 mm each.
The distance between the saw-toothed protrusion 10 and the surface of the semiconductor chip 6 is 0.5 mm.

そして、流出口8と流入口(7)を図示を省略した熱交
換器とポンプに連絡し、弗化炭素(C6F14)を流速1m/s
で強制循環させた。
Then, the outflow port 8 and the inflow port (7) are connected to a heat exchanger (not shown) and a pump, and carbon fluoride (C 6 F 14 ) is supplied at a flow rate of 1 m / s.
And forced circulation.

次に、半導体チップ(6)に電力を印加すると、冷媒の
沸騰と鋸歯状の突起10によって起こる乱流によって冷媒
の境界膜が剥ぎ取られるために、チップ当たりの冷却能
率は従来構造の場合が60W/cm2であったのに対し、110W
/cm2程度まで向上することができた。
Next, when power is applied to the semiconductor chip (6), the boundary film of the coolant is stripped off due to the boiling of the coolant and the turbulent flow caused by the saw-toothed protrusions 10, so that the cooling efficiency per chip may be the same as that of the conventional structure. 110W while it was 60W / cm 2
It was possible to improve to about / cm 2 .

〔考案の効果〕[Effect of device]

本考案の実地により半導体チップの大容量化に対応して
冷却能力を向上させることができ、これにより半導体パ
ッケージの小形化が可能になる。
According to the practice of the present invention, the cooling capacity can be improved in response to the increase in the capacity of the semiconductor chip, which makes it possible to reduce the size of the semiconductor package.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案に係る冷却構造を説明する原理図、 第2図は境界層を説明する模式図、 第3図は本考案に係る冷却構造の断面図(A)と蓋部内
部の平面図(B)、 である。 図において、 5,12は配線基板、6は半導体チップ、 7は流入口、8は流出口、 9,14は蓋部、10は鋸歯状の突起、 13は隔壁、 である。
FIG. 1 is a principle diagram illustrating a cooling structure according to the present invention, FIG. 2 is a schematic diagram illustrating a boundary layer, and FIG. 3 is a cross-sectional view (A) of the cooling structure according to the present invention and a plane inside a lid portion. Figure (B). In the figure, 5 and 12 are wiring boards, 6 is a semiconductor chip, 7 is an inflow port, 8 is an outflow port, 9,14 is a lid, 10 is a saw-toothed protrusion, and 13 is a partition.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】配線基板(5)上にマトリックス状に装着
してある複数の半導体チップ(6)を格納するパッケー
ジの蓋部(9)に冷媒の流入口(7)と流出口(8)と
が設けてあり、配列している前記半導体チップ(6)に
対して冷媒を一定方向に循環して冷却する構造体におい
て、 半導体チップ(6)に近接し、流路を介して対向する蓋
部(9)の天井部にそれぞれ鋸歯状の突起(10)を設け
ることを特徴とする半導体装置の冷却構造。
1. A refrigerant inlet port (7) and a refrigerant outlet port (8) in a lid portion (9) of a package for storing a plurality of semiconductor chips (6) mounted in a matrix on a wiring board (5). In a structure in which a cooling medium is circulated in a certain direction to the arranged semiconductor chips (6) and is cooled, a lid that is close to the semiconductor chips (6) and faces through a flow path. A cooling structure for a semiconductor device, characterized in that a saw-toothed protrusion (10) is provided on a ceiling portion of the portion (9).
JP1989071921U 1989-06-20 1989-06-20 Semiconductor device cooling structure Expired - Lifetime JPH0648868Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989071921U JPH0648868Y2 (en) 1989-06-20 1989-06-20 Semiconductor device cooling structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989071921U JPH0648868Y2 (en) 1989-06-20 1989-06-20 Semiconductor device cooling structure

Publications (2)

Publication Number Publication Date
JPH0310548U JPH0310548U (en) 1991-01-31
JPH0648868Y2 true JPH0648868Y2 (en) 1994-12-12

Family

ID=31609388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989071921U Expired - Lifetime JPH0648868Y2 (en) 1989-06-20 1989-06-20 Semiconductor device cooling structure

Country Status (1)

Country Link
JP (1) JPH0648868Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012138473A (en) * 2010-12-27 2012-07-19 Zycube:Kk Mounting structure for semiconductor device and electronic component

Also Published As

Publication number Publication date
JPH0310548U (en) 1991-01-31

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