JPH0652009A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To execute down-load and up-load at a high speed, and also, to efficiently operate a system. CONSTITUTION:In the in-circuit emulator having a direct access controller part 16 for executing up-load and down-load of a program between a host computer 11 and a target system 15, this in-circuit emulator is provided with a direct access controller control circuit 17 which is provided between the host computer 11 and the direct access controller part 16, converts a command sent from the host computer 11 to a command of the direct access controller part 16 and sends it therein, and also, controls a mutual waiting time caused by a speed difference of the host computer 11 and the direct access controller part 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator having improved control of a direct access controller for downloading and uploading a program, which is a typical function of the in-circuit emulator.

[0002]

2. Description of the Related Art Conventionally, an in-circuit emulator is connected to a target system instead of a microprocessor to arbitrarily execute / stop a program, read / write a resource such as memory, trace a function of execution, etc. Is known as a microprocessor development support device having

FIG. 8 is a block diagram for explaining control of a direct access controller in a conventional in-circuit emulator.

In FIG. 1, the intermediate control microprocessor 1 encodes a command for downloading or uploading a program given from the host computer 2 into a command suitable for an in-circuit emulator, and vice versa. In-circuit
Emulator CPU that controls each part of the emulator
When the bus 3 is released, it is directly connected to the target system 5 via a direct access controller (hereinafter referred to as DAC) 4 and direct memory access (hereinafter referred to as DMA) is performed. In addition, the applicant of the present invention,
JP-A-4-13640 discloses an in-circuit capable of flexibly coping with diversification of models of emulation CPUs and diversifying and speeding up access processing.
The technology related to the emulator is disclosed.

[0005]

That is, in the conventional in-circuit emulator, the intermediate control processor 1 is involved in the downloading and uploading in the DAC 4, so the processing becomes slower accordingly.
Moreover, the efficiency of the system could not be improved. In recent years, delays in downloading and uploading have become non-negligible in debugging a large-capacity program, and it has been required to efficiently reduce the delay.

Therefore, an object of the present invention is to provide an in-circuit emulator capable of speeding up download and upload and improving the efficiency of the system.

[0007]

In order to achieve the above object, the in-circuit emulator of the present invention is a direct access controller section for uploading and downloading a program between a host computer and a target system. In-circuit with
In the emulator, provided between the host computer and the direct access controller unit, converts a command sent from the host computer into a command of the direct access controller unit, and sends the command. A direct access controller control circuit for controlling the mutual waiting time due to the speed difference of the direct access controller is provided.

[0008]

According to the present invention, the command sent from the host computer is converted into the command of the DAC section for downloading and uploading and is sent, and the waiting time due to the difference between the speed of the host computer and the speed of the DAC section. By omitting the above, the speed can be increased, and since the ECP does not need to be involved in the download and upload commands, the efficiency of the system can be improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to an embodiment shown in the drawings. FIG. 1 is an overall block diagram illustrating an in-circuit emulator according to an embodiment of the present invention.

In the figure, the in-circuit emulator of this embodiment is a command transmitted and received from a host computer 11 via a first-in-first-out section (hereinafter referred to as a FIFO section) 12 constituting a host interface. An emulator control processor (hereinafter referred to as ECP) 13 for controlling each function of the emulator based on data and data, and a DAC for controlling the bus of the emulation CPU 14 to directly connect to the target system 15 for direct memory access. A DAC control circuit 17 is provided between the host computer 11 and the unit 16 for converting download and upload commands, and for eliminating waiting time due to a speed difference between the host computer 11 and the DAC unit 16.

The host computer 11 is, for example, a commercially available personal computer,
A debugger (program) is driven, and a program for converting a command by an operator into a packet for notifying (communication) to the ECP 13 is also provided.

The ECP 13 is a microprocessor for controlling functions typified by an emulator. For example, control of the emulation CPU 14 and trace control, control of an emulation memory (not shown) mainly for allocation, And controls for communicating these functions with the host computer 11.

Here, the host computer 11 and the ECP
A communication packet for the 13 to send and receive data is defined in advance as a data structure. A command having a data length of 1 byte related to download and upload from the host computer 11 is read by the ECP 13 from the FIFO unit 12. Such commands are defined in advance according to the format of communication,
For example, if it is “40”, a data read command on the target system 15 controlled by the ECP 13,
If it is "41", the target controlled by ECP13
If the data write command on the system 15 is “42”, the data read command on the target system 15 without the ECP 13 is “43”.
It is a single data file up command on the target system 15 without the ECP 13 intervening. Details of the structure example of the communication soft packet of the above command will be described later.

The DAC control circuit 17 is used in the download (write) direction in order to realize high-speed communication between the host computer 11 and the DAC unit 16.
FO unit 21, DAC control unit 22 for controlling DAC unit 16, direct FIFO access controller (hereinafter referred to as DFAC) 23 provided to reduce the processing of ECP 13, and upload (read) direction DAC data read register 24 used in
And a timing control unit 25 for generating a timing signal for controlling the DAC unit 16 and the like. DFAC
24 can be used by setting in a control register provided inside the DAC control unit 22 and the like, and can be used with the ECP 13 with a main bus release request signal (MHOL).
D) and its acknowledge signal (MHLDA), and DMA is performed between the FIFO units 12 of the communication software installed on the host computer 11. Further, the DAC control unit 22 also performs a process of shifting an array of data sent from the host computer 11 side with respect to an address. In this embodiment, D is set by setting the above control register.
The ECP 13 is configured to be able to perform processing related to download without using the FAC 23.
At this time, the DFIFO unit 21 still has the FIFO structure, and the writing of data is performed by the DF having a 16-bit length.
The number of IFO registers is set one by one. However, the read-out of the DFIFO unit 21 has a dedicated area reserved for reading out the required data by addressing. Note that writing to this area is prohibited and is masked in hardware. Further, in the present embodiment, the host computer 11 and the DAC unit 16 communicate with each other by directly using the DFAC 23 of the DAC control circuit 17, and the ECP 13 reads the communication data and
There are two methods for sending data to the AC unit 16 or vice versa, that is, two methods in which the ECP 13 sequentially intervenes in communication. The DFAC23 method is used only for download commands.

FIG. 2 is a block diagram for explaining the DAC control circuit portion related to the download according to the embodiment of the present invention. The parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In the figure, the DFIFO unit 21 is composed of six 16-bit data registers for temporarily recording the data sent from the host computer 11 side. It is connected to the. One of these data registers is selected and read or write is controlled by a signal supplied from a read / write DFIFO selector 26 which constitutes a part of the DAC control unit 22. The read / write DFIFO selector 26 uses the DF from the DFA C 23.
IFO write signal (DFIFO WR-), DAC unit 1
DFIFO read request signal (DFIFO RD
-) Is input and an acknowledge signal (DFIFO RDY) is output to the DAC unit 16. Also, DFAC
23 is a FIFO unit 12 on the host computer 11 side
To the read request signal (FIFO RD-).

FIG. 3 is a block diagram showing the configuration of the direct access controller according to the embodiment of the present invention.

In the figure, the DAC unit 16 stores the data sent from the DFIFO unit 21 at the time of download.
Converted for AC, and also DAC data when uploading.
D prepares the data for output to the read register
A FIFO window section 31, an address generation section 32 that generates an address based on the data given from the DFIFO window section 31, and outputs it to the bus controller, and a DFIFO.
A bus release request signal (DH) is sent to the emulation CPU 14 based on the data section 33 that controls data between the window section 31 and the bus controller, and the data such as continuation / end and length given from the DFIFO window section 31.
OLD) and outputs its acknowledge signal (DHLDA)
, A DFIFO access signal to output the acknowledge signal (DFIFO RDY), and a signal to control each unit of the DAC unit 16, and a clock signal (ECLK) and a ROM.
It is composed of a timing generation unit 35 which inputs an address, generates a timing signal, and outputs it to the control unit 34. The details of the configuration and operation of such a direct access controller are disclosed in the above-mentioned Japanese Patent Laid-Open No. 64-13640, so detailed description thereof will be omitted.

FIG. 4 is a diagram for explaining an example of the structure of the packet of the embodiment of the present invention, and FIG. 5 is a diagram for explaining an example of the structure of the start address of the packet of the embodiment of the present invention.

In the packet structure example of this embodiment, the above-mentioned command is the download protocol type of "42", and as shown in FIG. 4, the format of the packet sent from the host computer 11 side is the continuation code ( 1
6 bits), start address (32 bits), length (32 bits), followed by arbitrary data to be transferred (length), and end code (16 bits) with 5
A word dummy follows. The start address is the base address of the transfer destination, the length is the transfer data length, and the data is any data to be transferred. The continuation code is a code for recognizing the same command and downloading again according to the new transfer destination address and length, and the end code is a code for ending the data transfer. The structure of the start address is, for example, composed of 5 words as shown in FIG.
A dummy and a dummy follow the bit and the upper 16 bits. Note that other upload type packet structures and the ECP 13 read communication data, and the DAC unit 16
The description of an example packet structure for sending to or from the packet is omitted.

Next, the operation of the in-circuit emulator having the above configuration will be described with reference to timing charts. FIG. 6 is a timing diagram for explaining the download operation in the DFAC according to the embodiment of the present invention. It should be noted that this timing diagram excludes cycles related to addresses and lengths.

A timing signal (FIF for writing to the FIFO unit 12 output from the host computer 11
OWR-) and readable signal (FIFO RDY)
A command or data is written to the FIFO 12 based on the above. Next, when the first command is recognized by the ECP 13, it is notified to the DAC control circuit 17, and when it is set in the control register, a start signal (START-) is output, and its use becomes possible.

Next, in the DAC control circuit 17, the FIFO
After the section 12 becomes readable (FIFO RDY is “high level”), a bus release request signal (MHOLD is “high level” and a in the figure) is generated, and the DFIFO section 21
When data is not filled in all registers of (D
When the FIFO FULL- or DAC RDY is "low level", b) in the figure, or when the FIFO unit 12 becomes unreadable (FIFO RDY is "low level", c in the figure), a bus release request signal is sent to the ECP 13. Output (MHOLD is "low level"). That is, F
There is data to be transmitted to the IFO unit 12, and the DFIF
When it is possible to write to O section 21, ECP
A bus release request signal is output to 13 and then EC
The acknowledge signal (MHLDA is “high level”) is output from P13, and then the bus is released and the FIF
Data is written in the O section 12.

Next, in the DAC section 16, the DFIFO section 2
The read request signal of 1 (DFIFORD- is “low level”) is read by the DFIFO unit 21 as a read enable signal (DFI).
This occurs when FORDY is "high level" as shown in d) of the figure, and subsequently, similarly, a bus release request cycle (DHOLD and DHLDA) to the emulation CPU 14 is generated.
Occurs. That is, when there is data to be transmitted to the DFIFO section 21 and the DAC section 16 is readable, a bus release request signal (DHOLD is “high level”) is output to the emulation CPU 14, and then the emulation CPU 14 outputs. The acknowledge signal (DHLDA is “high level”) is output, the bus is released, and the target system 15 can be written (USER WR− is “low level”). Further, the read request signal (DFIFO of the DFIFO unit 21
When RD- outputs "low level", the DAC
The control circuit 17 puts the DFIFO unit 21 in a writable state (“low level” of DFIFO FULL− is “high level” e in the figure).

FIG. 7 is a diagram for explaining the state transition of the DAC section according to the embodiment of the present invention.

First, when starting from the standby state (A) by the reset signal, it shifts to the state (B) of waiting for an address from the DAC control circuit 17 or ECP 13, and when all the data corresponding to the address is set, The state shifts to the length waiting state (C) from the DAC control circuit 17 or the ECP 13. Next, when all the data corresponding to the length has been set, the state is changed to the data write or data read state (D or E) based on the upload or download set in the predetermined register in advance, and in this state the predetermined The data of the length given by the length is written to or read from the address. Next, the branch state (E) given from the DAC control circuit 17 or the ECP 13 is passed, and in the case of the continuation, the address wait (B) and the length wait (C) are moved again to write or read data. Is done. In the case of the end, the state moves to the end state (G), an interrupt is generated, and the state returns to the initial state. In the data write or data read state (D or E),
When it is a stop, it moves to the end state. The start or stop is performed by the start register or the stop register of the DAC unit 16. Next, when an error occurs in the data write or data read state (D or E), the state moves to an urgent error state (H) and an interrupt occurs, or the halt state (I) is set. Then, the fact that an error has occurred is notified, and the state of data write (D), the state of data read (E), or the state of end (G) is entered again by an instruction from the DAC control circuit 17 or ECP 13.

As described above, in the above configuration, when the program data is downloaded from the host computer 11 to the target system 15, the packet has the format shown in FIG. 4, and the first command is ECP.
13 recognizes and notifies the DAC control circuit 17. With this notification, the DAC control circuit 17 makes a bus release request to the ECP 13, and when the ECP 13 bus is released,
The host computer 11 and the DAC control circuit 17 are directly connected. The DAC control circuit 17 converts a command given from the host computer 11 into one suitable for the DAC unit 16 and sends the command and data to the DAC unit 16. The packet has a continuation code and an end code. When the packet is continued, it is recognized that the command is the same, and the download is performed again according to the address and length of the new transfer destination. In addition, when ending, the DAC unit 16
When the final data transfer is completed, the bus is released to the ECP 13 and the process is completed. The same principle applies to uploading, only that the data direction is from the DAC unit 16 to the host computer 11 side. Therefore,
The command enables the DAC control circuit 17 to be used, the processing of the ECP 13 can be reduced, the download and upload can be speeded up, and the efficiency of the system can be improved.

[0028]

As described in detail above, according to the present invention, the command sent from the host computer is
By converting and sending to the command of the DAC unit for downloading and uploading, and by eliminating the waiting time due to the difference between the speed of the host computer and the speed of the DAC unit, it is possible to achieve higher speed. Since there is no need for the ECP to be involved in the download and upload commands, the efficiency of the system can be improved.

[Brief description of drawings]

FIG. 1 is an overall block diagram illustrating an in-circuit emulator according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a DAC control circuit portion related to downloading according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a direct access controller according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a packet structure according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of the structure of a start address of a packet according to the embodiment of this invention.

FIG. 6 is a timing diagram illustrating a download operation in the DFAC according to the embodiment of this invention.

FIG. 7 is a diagram illustrating state transition of the DAC unit according to the embodiment of this invention.

FIG. 8 is a block diagram illustrating control of a direct access controller in a conventional in-circuit emulator.

[Explanation of symbols]

 11 host computer 12 FIFO unit 13 ECP 14 emulation CPU 15 target system 16 DAC unit 17 DAC control circuit 21 DFIFO unit 22 DAC control unit 23 DFAC 24 DAC data read register 25 timing control unit

Claims (1)

[Claims] 1. An in-circuit emulator having a direct access controller section for uploading and downloading a program between a host computer and a target system, wherein the host computer and the direct access controller section are connected to each other. Direct access commands sent from the host computer provided between
While converting into a command of the controller part and sending it,
An in-circuit emulator comprising a direct access controller control circuit for controlling a waiting time of each other depending on a speed difference between the host computer and the direct access controller section.