JPH0652778B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor technology and a technology particularly effective when applied to the formation of a transistor in a semiconductor integrated circuit. For example, a bipolar transistor and a MISFET (insulated gate type) are formed on the same semiconductor substrate. Field effect transistor)
The present invention relates to a technique effectively used in a process of a semiconductor integrated circuit in which a film is formed.

[Background Art] In a MOS integrated circuit in which MISFETs are integrated on a semiconductor substrate, hot carriers are injected into a gate insulating film due to high integration due to miniaturization of MISFETs. The problem is that characteristic deterioration over time occurs. This is because the potential gradient between the source and the drain becomes steeper as the channel length becomes shorter, and the carriers flowing from the source to the drain are accelerated to obtain high energy, and a part of it becomes the silicon substrate and the insulating film on its surface. This is because it enters the insulating film beyond the barrier at the interface of and is trapped by the trap level inside.

In order to prevent the hot carrier injection phenomenon into the gate insulating film as described above, for example, as shown in FIG. 2, both sides of the gate electrode 101 formed on the semiconductor substrate 1 via the gate insulating film 100 are formed. A sidewall 102 made of an insulator is formed. And this sidewall 102
Before and after the formation of the source and drain regions, impurities are introduced to form high concentration source and drain regions 103a.
A low-concentration semiconductor region 103b is formed on the inside of the so-called LDD (Lightly Dy) to relax the drain electric field and suppress the hot carrier injection phenomenon.
MISFETs having an open drain structure have been proposed ("Nikkei Electronics (Separate Volume Micro Devices)", published by Nikkei McGraw-Hill, August 22, 1983, pages 83, 84, IEEE Trans. El.
electron. Derices, Vol, ED-29,
PP. 590-595, Apr. 1982) N-channel type MISFETs and P-channel type MISSFs in CMOS (complementary MOS) integrated circuits are utilized by utilizing the technology related to the LDD structure MISFETs described above.
The present inventor has developed the following process technology as a method of forming both ETs in an LDD structure.

That is, as shown in FIG. 3A, after the P well region 104 and the N well region 105 are formed on the semiconductor substrate 1, a thick field oxide film 106 for separation is formed on the substrate surface at the boundary between them.

Then, after forming a silicon oxide film 107 serving as a gate insulating film on the main surface of the substrate, a conductive layer such as a polysilicon layer is entirely formed on the silicon oxide film 107 by a CVD method, and then photoetching is performed. Go MISFET
Gate electrodes 108a and 108b are formed.

Then, as shown in FIG. 3 (B), P channel MISF
With the gate 110b made of a polysilicon layer used as a mask, N-type impurities are ion-implanted and diffused in a state where a mask 110 such as a photoresist coating covers the element region where ET is formed. Then, low-concentration N ⁻ type semiconductor regions 109a are formed in self-alignment with the gate electrode 108b on the substrate surface on both sides of the gate electrode 108b.

Next, after removing the photoresist coating 110,
In the same manner as described above, the P-type impurity is injected and diffused by ion implantation or the like in the state where the upper part of the element region where the N-channel MISFET is formed is covered with the photoresist film as shown by the chain line A. Then, the gate electrode 10
On the main surface of the substrate on both sides of 8a, a P ⁻ type semiconductor region (11
2a) is formed in self-alignment with the gate electrode 108a.

Therefore, after removing the photoresist film (A),
A silicon oxide film is formed relatively thick on the entire main surface of the substrate by a CVD method, and then the silicon oxide film is removed by reactive ion etching or the like. Then, the insulating films 111 called sidewalls are left on the side portions of the gate electrodes 108a and 108b, respectively.

In this state, after thinly oxidizing the surfaces of the N ⁻ type region 109a and the P ⁻ type region 112a, as shown in FIG.
A photoresist film 110 'is covered over the element region where the channel MISFET is formed, and N-type impurities are ion-implanted and diffused. Then, the high concentration N ⁺ type semiconductor region 109b is formed outside the N ⁻ type semiconductor region 109a by being self-aligned with the insulating film 111 forming the sidewall.

After the state of FIG. 3 (C), the photoresist coating 11
After removing 0 ', this time N channel MISFET
Ion implantation of P-type impurities is performed with the upper part of the formation region covered with a photoresist film. Then, a high concentration P ⁺ type semiconductor region is formed outside the P ⁻ type semiconductor region 112a by being self-aligned with the sidewall (111), and an LDD structure similar to the N channel MISFET is formed.

However, in the above process, the N-channel MISFET and the P-channel MISFE are masked with the source and drain regions of the LDD structure including the low-concentration semiconductor region and the high-concentration semiconductor region using the photoresist film as a mask.
Since T and T are formed separately, there is the inconvenience that the process becomes considerably complicated.

Therefore, a so-called BiCM in which a bipolar transistor is formed together with a MISFET on the same semiconductor substrate.
In the OS process, when the above process is used to form the LDD structure MISFET, BiCMOS
The process becomes more complicated.

[Object of the Invention] An object of the present invention is to provide a semiconductor device having an LDD structure N-channel type insulated gate field effect transistor and a P-channel type insulated gate field effect transistor, and a bipolar transistor on the same semiconductor substrate. In the manufacturing process of, without deteriorating the device characteristics,
It is to provide a semiconductor manufacturing technique capable of simplifying the manufacturing process.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention] The outline of a typical invention disclosed in the present application will be described below.

That is, an N-channel type insulated gate field effect transistor and a P-channel type insulated gate field effect transistor forming a complementary type insulated gate field effect transistor and a bipolar transistor are provided on the same semiconductor substrate, and the N channel The source region and the drain region of the n-type insulated gate field effect transistor each have a low-concentration first region inside a pair of high-concentration first N-type semiconductor regions.
The source region and the drain region of the P-channel type insulated gate field effect transistor are each formed inside a pair of high-concentration first P-type semiconductor regions. The bipolar transistor comprises a double-structure semiconductor region in which a low-concentration first P-type semiconductor region is formed, and the bipolar transistor has a high-concentration external base region outside a low-concentration second P-type semiconductor region serving as an intrinsic base region. In the method for manufacturing a semiconductor device including the second P-type semiconductor region, the low-concentration N-type is formed in the formation region of the N-channel type insulated gate field effect transistor, the P-channel type insulated gate field effect transistor, and the bipolar transistor. By introducing impurities, the N-channel type insulated gate field effect transistor is formed in the formation region. Forming a low-concentration first N-type half T-body region and forming a low-concentration second N-type semiconductor region in the formation region of the P-channel type insulated gate field effect transistor and bipolar transistor; Of the second N formed in advance in the formation region of the P-channel type insulated gate field effect transistor and the formation region of the bipolar transistor after masking the region in which the gate type insulated gate field effect transistor is formed.
The low-concentration first P-type semiconductor region is formed in the formation region of the P-channel type insulated gate field effect transistor by introducing a low-concentration P-type impurity so as to convert the P-type semiconductor region into the P-type semiconductor region. Forming and forming the intrinsic base region in the formation region of the bipolar transistor, masking the P-channel type insulated gate field effect transistor and the bipolar transistor, and then forming the N-channel type insulated gate field effect By introducing an N-type impurity into the transistor,
Forming the high-concentration first N-type semiconductor region in a formation region of a channel type insulated gate field effect transistor; forming region of the P channel type insulated gate field effect transistor; and forming region of the bipolar transistor By introducing a high concentration P-type impurity into the region, the high concentration first P-type semiconductor region is formed in the formation region of the P-channel insulated gate field effect transistor, and the intrinsic region is formed in the formation region of the bipolar transistor. By having the step of forming the external base region outside the base region, at least one mask can be omitted, and the number of exposure processing steps such as exposure, development and baking can be reduced. Therefore, the manufacturing process can be simplified. In addition, the impurity introduction step for forming the low-concentration second N-type semiconductor region of the N-channel type insulated gate field effect transistor is first performed to enhance the formation accuracy of the low-concentration second N-type semiconductor region. Therefore, the device characteristics are not deteriorated. Therefore, it is possible to simplify the manufacturing process without deteriorating the element characteristics.

Further, the low-concentration first P-type semiconductor region of the P-channel type insulated gate field effect transistor and the intrinsic base region of the bipolar transistor are simultaneously formed, and the P-channel type insulated gate field effect transistor of the P-channel type insulated gate field effect transistor is formed. By simultaneously forming the high-concentration first P-type semiconductor region and the external base region of the bipolar transistor, the N-channel insulated gate field-effect transistor of the LDD structure and the P-channel are formed without deteriorating the device characteristics. It is intended to achieve the above object of simplifying the manufacturing process of a semiconductor device having a bipolar insulated gate field effect transistor and a bipolar transistor.

[Embodiment] FIGS. 1A to 1I show a static RAM (random access memory) in which the memory array portion is a CMOS circuit and the peripheral circuit is a bipolar transistor and a CMOS circuit as an example of the present invention. An example when applied to a memory process is shown in the order of manufacturing steps.

In this embodiment, a semiconductor substrate 1 such as a P-type single crystal silicon substrate is prepared, the surface thereof is oxidized to form a silicon oxide film, and the silicon oxide film is used as a mask to heat N-type impurities such as phosphorus. The N ⁺ buried layers 2a and 2b are formed by introducing and diffusing on the main surface of the semiconductor substrate 1 by diffusion or the like.
Then, after the P ⁺ buried layers 3a and 3b are formed between the N ⁺ buried layers 2a and 2b by the same method, the oxide film serving as the mask is removed, and then the semiconductor substrate 1 is formed on the semiconductor substrate 1 by the vapor phase growth method. The N-type epitaxial layer 4 is formed on the entire surface, and the state shown in FIG.

Next, the surface of the N-type epitaxial layer 4 is oxidized to form a silicon oxide film and then photoetching is performed, and the N-channel M is formed by using the silicon oxide film as a mask.
A P-well region 5 is formed so as to reach the P ⁺ buried layer 3b by diffusing a P-type impurity in the place where the ISFET is formed. In addition, the bipolar transistor formation region and the MISF
Ion implantation of a P-type impurity for forming the channel stopper layer is performed on the boundary of the ET formation region at the same time as the ion implantation for forming the P well or in another step. Then, after removing the silicon oxide film used as the mask, the surface of the substrate 1 is thinly oxidized again to form the oxide film 7a.
Then, the silicon nitride film 6 is formed by the CVD method (chemical vapor deposition method) or the like. Then, photoetching is performed so that the silicon nitride film 6 remains only on the regions where elements such as bipolar transistors and MISFETs are to be formed.

Using the silicon nitride film 6 as an oxidation resistant mask, the surface of the semiconductor substrate 1 is selectively thermally oxidized in an oxidizing atmosphere to form a relatively thick field insulating film 7. At this time,
Since the silicon nitride film 6 is impermeable to oxygen, the main surface of the substrate below the silicon nitride film 6 is not oxidized. By this heat treatment, the P-type impurity that has been implanted in advance is diffused, and P is formed as a channel stopper layer reaching the P ⁺ buried layer 3a immediately below the field insulating film 7 at the boundary between the bipolar transistor and the MISFET. The type semiconductor region 8 is formed, and the state shown in FIG.

After the state of FIG. 1 (B), the silicon nitride film 6 serving as an oxidation resistant mask on the main surface of the substrate and the silicon oxide film 7a thereunder are removed, and then thermal oxidation is performed to expose the exposed substrate. A silicon oxide film 11 serving as a gate insulating film is formed on the main surface. Then, a conductive layer such as a polysilicon layer is entirely formed on the silicon oxide film 11 by the CVD method,
Furthermore, after forming a coexisting layer of molybdenum and silicon on it, photo-etching is performed to form a dual structure MIS
The FET gate electrodes 12a and 12b are formed.

Then, using a photoresist film or the like as a mask, an N-type impurity such as phosphorus is implanted into the portion serving as the collector pull-up port by ion implantation or the like, and then heat treatment is performed. By this heat treatment, the layer in which molybdenum and silicon coexist in the upper layers of the gate electrodes 12a and 12b is completely silicidized, and the impurity implanted into the portion serving as the collector pull-up port is diffused to diffuse the N ⁺ buried layer 2a. The N-type diffusion layer 9 reaching the temperature is formed, and the state shown in FIG.

Then, using the gate electrodes 12a and 12b as a mask, an N-type impurity such as phosphorus is ion-implanted through the silicon oxide film 11 serving as a gate insulating film at a dose amount of, for example, 1 × 10 ¹³ / cm ^2. And heat it. Then, the N channel MI that is originally desired to be the N ⁻ type region
The surface of the P well region 5 where the source and drain regions of the SFET are formed and the surface of the N type epitaxial layers 4a and 4b as the N well region of the base of the bipolar transistor and the source and drain of the P channel MISFET. In addition, the low-concentration N ⁻ type semiconductor regions 15a, 15b, 15c having a concentration of about 1 × 10 ¹⁷ / cm ³ are formed.
Are formed in a self-aligned manner with respect to the gate electrodes 12a and 12b, resulting in the state of FIG.

After the state of FIG. 1 (D), as shown in FIG. 1 (E), the element region where the N-channel MISFET is formed and the collector pull-up port (9) are covered with a mask such as a photoresist film 13. In this state, to form a base region of the bipolar transistor, a P-type impurity such as boron is ion-implanted at a dose amount of about 1.5 × 10 ¹⁴ / cm ² , and thereafter, heat treatment is performed to diffuse it. Then, the ion implantation for forming the base region is performed by the N ⁻
Since the ion dose exceeds the ion implantation for forming the type semiconductor region 15a by one digit or more, the N ⁻ type which has already been formed in the base region and the portions to be the source and drain regions of the N channel MISFET are formed. The conductivity type (N ⁻ type) of the semiconductor regions 15c and 15a is canceled by the P type impurity and changed to the opposite conductivity type, and P
^- -type semiconductor regions 10a, 14a are formed.

Then, after removing the photoresist coating 13, a silicon oxide film is formed relatively thick on the entire main surface of the substrate by the CVD method, and then the silicon oxide film is removed by reactive ion etching or the like. Then, since the reactive ion etching proceeds in parallel from above, the relatively thick portions, that is, the gate electrodes 12a and 12b.
Insulating films 17 called sidewalls are left on both sides of each. Therefore, in this state, after thinly oxidizing the surfaces of the N ⁻ and P ⁻ type semiconductor regions, the base forming region (10
Covering the periphery of a) and the device region where the P-channel MISFET is formed with a photoresist film 18,
For example, an N-type impurity such as arsenic is ion-implanted at a dose amount of 5 × 10 ¹⁵ / cm ² and diffused.

Then, it is self-aligned with the insulating film 17 forming the sidewall, and as shown in FIG. 1 (F), a high concentration of about 1 × 10 ²⁰ / cm ³ is provided outside the N ⁻ type semiconductor 15b. The N ⁺ type semiconductor region 19 is formed.

After the state of FIG. 1 (F), as shown in FIG. 1 (G), with the photoresist film 18 ′ covered above the bipolar element region and the N-channel MISFET formation region,
For example, ion implantation of P-type impurities is performed with a dose amount of about 3 × 10 ¹⁵ / cm ² . Then, the sidewall (1
7) self-aligned to the P ⁻ -type semiconductor region 14a and a high concentration P ⁺ -type semiconductor region 14b outside the P ⁻ -type semiconductor region 14a, and a high concentration outside the P ⁻ -type semiconductor region 10a that is an intrinsic base region (right side in the figure). The outer base region 10b is formed.

Next, after the silicon oxide film 20 is formed over the entire surface of the semiconductor substrate by, for example, the CVD method under a high temperature and a low pressure, the silicon oxide film 20 is selectively etched so that the silicon oxide film 20 is formed on the intrinsic base region (10a) and N channel MIS
Contact window 21 on the source and drain regions of the FET
a and 21b are formed. Then, a second polysilicon layer is entirely formed by the CVD method, and then patterning is performed to form a polysilicon electrode 22a for the emitter and a polysilicon electrode 22b for the source and drain of the N-channel MISFET. A polysilicon layer 22c for forming a resistance element is left above the gate electrode 12b of the N-channel MISFET via the silicon oxide film 20.

Then, the polysilicon layer 2 for forming the resistance element
2c with only the upper part of 2c covered with a photoresist film
Type impurities are ion-implanted and annealed, and polysilicon layers other than the polysilicon layer 22c serving as the resistance element (2
2a, 22b) has a low resistance. At this time, due to the impurity diffusion from the polysilicon electrode 22a, an N ⁺ type semiconductor region 23, which is a relatively shallow emitter region, is formed on the intrinsic base region (10a), and the state shown in FIG. 1 (H) is obtained.

After the state of FIG. 1 (H), an interlayer insulating film 2 such as a PSG film (phosphorus / silicate glass film) is formed on the entire semiconductor substrate.
After forming 4, the contact windows 25a to 25e are opened in the interlayer insulating film 24 by dry etching. Then, after depositing an aluminum layer on the entire surface, patterning is performed to form the emitter electrode 26a, the base electrode 26b, the collector electrode 26c and the MISFET.
The source and drain electrodes 25d and 25e are formed and the state shown in FIG. 1 (I) is obtained.

Then, a final passivation film is entirely formed on the aluminum electrodes (25a to 25e) to complete the film.

In the above embodiment, the N-channel MI of LDD structure is used.
The formation of the N ⁻ type semiconductor region 15b for obtaining the SFET is performed without a mask. Therefore, the N ^- type semiconductor region (15
b, 109a) and the P ⁻ type semiconductor region (14a, 112a) of the P channel MISFET are formed by using different photoresist masks, compared with the method shown in FIG. The number is small, and the photoresist mask forming step can be omitted.

In the above embodiment, the P channel MI manufactured by LDD is used.
P for obtaining a SFET ^- performs formation type semiconductor region 14a in the same step as the introduction of the P-type impurity for base formation of the bipolar transistor, the low concentration which is previously formed N ^- type semiconductor region 15a of the N ^- type Of the P ⁻ type semiconductor region 14a in a form of being compensated by a high concentration P type impurity introduced later.
Is formed.

Therefore, the base region 10a of the bipolar transistor
And a P-channel MISFET P ^- -type semiconductor region 14a
In the BiCMOS process, it is not necessary to separately form the LDD, and LDD can be performed without complicating the process.
A MISFET having a structure can be obtained. As a result, in a semiconductor integrated circuit such as a static RAM composed of bipolar transistors and MISFETs, M
Higher integration and higher functionality can be achieved by miniaturizing the ISFET.

Moreover, P ⁺ of the P-channel MISFET of LDD structure
Since the P-type impurity is ion-implanted into the external base region 10b of the bipolar transistor at the same time when the type semiconductor region 14b is formed, the resistance value of the external base region can be effectively reduced without increasing the number of steps. Therefore, the performance of the bipolar transistor can be improved.

Further, first, by performing an impurity introduction step for forming the N ⁻ type semiconductor region 15b of the N-channel MISFET having the LDD structure, the formation accuracy of the N ⁻ type semiconductor region 15b, for example, the impurity concentration and the thickness are set. Since the precision can be made high, it is possible to simplify the manufacturing process without deteriorating the element characteristics.

In the above-mentioned embodiment, the one applied to the BiCMOS process has been described. However, also in the CMOS process, the P ⁻ type semiconductor region of the P channel MISFET is formed in advance without the microphone of the N ⁻ type semiconductor region of the N channel MISFET. After the formation, the N of the source and drain regions of the P-channel MISFET formed by the formation
^The number of masks can be reduced by performing ion implantation of P-type impurities so as to cancel the ⁻ type.

Further, in the above embodiment, the emitter region (23) is formed by impurity diffusion from the polysilicon layer 22a, but the present invention is not limited to this. For example, it is formed by performing direct diffusion or ion implantation on the main surface of the semiconductor substrate, or the source of an N-channel MISFET,
By forming the N ⁺ -type semiconductor region 19 which is the drain region in a step subsequent to the formation of the P ⁺ -type semiconductor region 14b of the P-channel MISFET, the source and drain regions (19) of the N-channel MISFET are formed. At the same time, it is possible to form the emitter region.

Further, in the above-described embodiment, the sidewalls (1) are formed on both sides of the gate electrode 12a for the P-channel MISFET as well.
7) is provided so that the source and drain regions have an LDD structure including a P ⁺ type semiconductor region 14b and a P ⁻ type semiconductor region 14a. However, P channel MI
Since the characteristics of the SFET are relatively unlikely to deteriorate due to the phenomenon of injection of hot carriers into the gate oxide film, the P-channel MISFET has a general M structure that does not have the LDD structure.
It can be an ISFET structure.

[Effect] (1). An N-channel type insulated gate field effect transistor and a P-channel type insulated gate field effect transistor forming a complementary type insulated gate field effect transistor and a bipolar transistor are provided on the same semiconductor substrate. The source region and the drain region of the insulated gate field effect transistor each have a double structure semiconductor region in which a low concentration first N-type semiconductor region is formed inside a pair of high concentration first N-type semiconductor regions. The source region and the drain region of the P-channel type insulated gate field effect transistor each have a double structure semiconductor region in which a low-concentration first P-type semiconductor region is formed inside a pair of high-concentration first P-type semiconductor regions. Consists of
In the method of manufacturing a semiconductor device, the bipolar transistor includes a high-concentration second P-type semiconductor region serving as an external base region outside a low-concentration second P-type semiconductor region serving as an intrinsic base region. By introducing a low concentration N-type impurity into the formation region of the gate type field effect transistor, the P channel type insulated gate field effect transistor and the bipolar transistor,
The low-concentration first N-type semiconductor region is formed in the formation region of the N-channel type insulated gate field effect transistor, and the low-concentration first N-type semiconductor region is formed in the formation region of the P-channel type insulated gate field effect transistor and the bipolar transistor. Forming a second N-type semiconductor region and masking a region in which the N-channel type insulated gate field effect transistor is formed, and then forming a region of the P-channel type insulated gate field effect transistor, the bipolar transistor Forming a P channel type insulated gate field effect transistor by introducing a low concentration P type impurity so as to convert the previously formed second N type semiconductor region into a P type semiconductor region. Forming the low-concentration first P-type semiconductor region in the region to form the bipolar transistor A step of forming the intrinsic base region in the region, masking the P-channel type insulated gate field effect transistor and the bipolar transistor, and then introducing an N-type impurity into the N-channel type insulated gate field effect transistor. Thereby forming the high-concentration first N-type semiconductor region in the formation region of the N-channel type insulated gate field effect transistor, the formation region of the P-channel type insulated gate field effect transistor, and By introducing a high-concentration P-type impurity into the formation region of the bipolar transistor, the P
Forming the high-concentration first P-type semiconductor region in a formation region of a channel-type insulated gate field effect transistor, and forming the external base region outside the intrinsic base region in the formation region of the bipolar transistor. By having at least one mask, the number of exposure processing steps such as exposure, development and bake processing can be reduced, and the manufacturing process can be simplified. Also, first N
By performing the impurity introduction step for forming the low-concentration second N-type semiconductor region of the channel-type insulated gate field-effect transistor, the formation accuracy of the low-concentration second N-type semiconductor region can be increased. It does not cause deterioration of the element characteristics. Therefore, it is possible to simplify the manufacturing process without deteriorating the element characteristics.

(2). A low concentration first P type semiconductor region of the P channel type insulated gate field effect transistor and an intrinsic base region of the bipolar transistor are simultaneously formed, and a high concentration of the P channel type insulated gate field effect transistor is formed. By simultaneously forming the first P-type semiconductor region and the external base region of the bipolar transistor, the N-type insulated gate field effect transistor of the LDD structure and the P-channel type of the LDD structure are not brought about. It is possible to further simplify the manufacturing process of the semiconductor device having the insulated gate field effect transistor and the bipolar transistor.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment,
Buried layers 2a, 2b and 3a, 3b are formed on a semiconductor substrate, an N-type epitaxial layer 4 is formed thereon, and a P well region 5 is formed therein. Although the channel MISFET and the base region of the bipolar transistor and the P-channel MISFET are formed on the N well regions 4a and 4b formed of the epitaxial layers, the P well region is directly formed on the main surface of the substrate without forming the epitaxial layer 4. Alternatively, it can be applied to a CMOS or BiCMOS process in which a P well region and an N well region are formed and respective elements are formed thereon.

[Field of Use] In the above description, the invention mainly made by the present inventor is described as being applied to the process of the static RAM having the BiCMOS structure, which is the field of use as the background, but the present invention is not limited thereto. BiCMO
The S process or the CMOS process can be generally used.

[Brief description of drawings]

1 (A) to 1 (I) are sectional views showing an embodiment of the present invention applied to a BiCMOS process in the order of steps, and FIG. 2 is a sectional view showing an example of a conventional MISFET having an LDD structure, 3 (A) to 3 (C) show a CMOS process
It is sectional drawing which shows an example of the procedure of forming MISFET of LDD structure. 1 ... Semiconductor substrate, 2a, 2b ... N ⁺ buried layer, 3a,
3b ... P ⁺ buried layer, 4 ... N-type epitaxial layer, 5
...... P well region, 6 ... silicon nitride film, 7 ... field insulating film, 8 ... P type semiconductor region (channel stopper layer), 9 ... N type semiconductor region (collector pulling port), 10a ... P Type semiconductor region (base region), 10
b ... External base region, 11 ... Silicon oxide film (gate insulating film), 12a, 12b ... Gate electrode, 13, 1
8,18 '... photoresist film, 14a ... P ^- -type semiconductor region, 14b ... ^{P +} -type semiconductor region, 15a, 1
5b, 15c ... N ^- type semiconductor region, 17 ... Insulating film (sidewall), 19 ... N ⁺ type semiconductor region, 20
... Silicon oxide film, 21a, 21b, 25a to 25e
...... Contact window, 22a ・ ・ ・ Polymer electrode for emitter, 22b ・ ・ ・ Polysilicon electrode for source and drain, 24 ・ ・ ・ Interlayer insulating film (PSG film), 26a to 26e
...... Aluminum electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-56-7462 (JP, A) JP-A-57-26463 (JP, A) Practical application Sho-59-98656 (JP, U)

Claims (3)

[Claims] 1. An N-channel type insulated gate field-effect transistor and a P-channel type insulated gate field-effect transistor forming a complementary type insulated gate field-effect transistor and a bipolar transistor are provided on the same semiconductor substrate. The source region and the drain region of the N-channel insulated gate field effect transistor have a double structure in which a low-concentration first N-type semiconductor region is formed inside a pair of high-concentration first N-type semiconductor regions, respectively. And a source region and a drain region of the P-channel type insulated gate field effect transistor, each of which has a lightly doped first P-type semiconductor region inside a pair of heavily-doped first P-type semiconductor regions.
The bipolar transistor is formed of a double-structured semiconductor region in which a high-concentration second P-type semiconductor serving as an external base region is provided outside a low-concentration second P-type semiconductor region serving as an intrinsic base region. In a method of manufacturing a semiconductor device having a region, introducing a low concentration N-type impurity into a formation region of the N-channel type insulated gate field effect transistor, the P-channel type insulated gate field effect transistor and the bipolar transistor. Thus, the low concentration first N-type semiconductor region is formed in the formation region of the N-channel type insulated gate field effect transistor, and the low concentration is formed in the formation region of the P-channel type insulated gate field effect transistor and the bipolar transistor. Forming a second N-type semiconductor region having a high concentration, and the N-channel type insulating gate. After masking the region in which the gate type field effect transistor is formed, the second N type semiconductor region previously formed is formed in the P channel type insulated gate field effect transistor and the bipolar transistor forming region. By introducing a low-concentration P-type impurity so as to convert the first-type P-type semiconductor region in the formation region of the P-channel type insulated gate field effect transistor to form the bipolar transistor. Forming the intrinsic base region in the region, masking the P-channel type insulated gate field effect transistor and the bipolar transistor, and introducing N-type impurities into the N-channel type insulated gate field effect transistor. As a result, the N-channel insulated gate field effect transistor Forming a high-concentration first N-type semiconductor region in the formation region, and introducing a high-concentration P-type impurity into the formation region of the P-channel type insulated gate field effect transistor and the formation region of the bipolar transistor. The above P
Forming the high-concentration first P-type semiconductor region in a formation region of a channel-type insulated gate field effect transistor, and forming the external base region outside the intrinsic base region in the formation region of the bipolar transistor. A method of manufacturing a semiconductor device, comprising: 2. A low-concentration first P-type semiconductor region of the P-channel insulated gate field effect transistor and an intrinsic base region of the bipolar transistor are formed simultaneously. A method of manufacturing a semiconductor device according to the item. 3. A high-concentration first P-type semiconductor region of the P-channel type insulated gate field effect transistor and an external base region of the bipolar transistor are formed at the same time. Alternatively, the method of manufacturing a semiconductor device according to the item 2.