JPH0656554B2 - Electronic musical instrument - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electronic musical instrument, and more particularly to a musical instrument which reads a memory and generates a musical tone based on the read data.

(Prior Art) In recent years, electronic musical instruments have become capable of producing sophisticated tones by introducing digital signal processing technology. Such an electronic musical instrument is disclosed in, for example, Japanese Patent Laid-Open No. 59-214091.

The operation principle whose block diagram is shown in FIG. 14 will be described.

The tone generator 1 and tone synthesis data ROM 2 are connected to the microcomputer bus. Performance information, such as the pitch and ON / OFF information of the played keyboard, effect information such as vibrato and pitch control instructed during the performance, or tablet information indicating which tone of the instrument to play is played through the microcomputer bus. It is transferred to the generator 1. Tone generator 1
Creates note data and actor data from pitch information, creates a note clock with nart data, and creates an address signal with octave data and tablet data. ROM2 stores musical tone waveform data for each tone for each octave. The tone generation section 1 reads out desired waveform data from the ROM 2 using the address signal as an address and the note clock as a read clock.

The musical sound generating unit 1 adds a predetermined effect to the read waveform data to create musical sound data, and sends the musical sound data to the filter 3 in accordance with the note clock. The filter 3 removes noise (quantization noise, aliasing noise) mixed in the musical sound data and sends it to the speaker 4. The waveform data stored in ROM2 is a digitally encoded sound of a natural musical instrument.
The timbre produced by is similar to that of a natural musical instrument.

FIG. 15 is a block diagram of the musical sound synthesis data ROM 2. The start address of 128 words corresponds to each key on the keyboard, and is the data indicating which control data or waveform data corresponds to the pressed key. The start address of the corresponding control data is written. . The musical tone generating section 1 reads a leading address by pressing a key and generates a musical tone waveform while reading control data and waveform data based on the leading address.

(Problems to be Solved by the Invention) However, in the above configuration, both waveform data and control data are 16-bit data as shown in the figure. This is because the commercially available ROM has a structure of 1 word and 8 bits, but it is not always necessary to have 16 bits for waveform data and control data. The upper or lower 4 bits are wasted.

In view of the above problems, the present invention provides an electronic musical instrument with improved ROM usage efficiency.

(Means for Solving the Problems) In order to solve the above problems, in the present invention, the number of bits of one word of waveform data is N, the number of bits of one word of the data bank is M, and the relationship between M and N is , , The total number of words in the data bank is W, and the upper M bits and the lower (NM) bits of the data of the i-th word of the waveform data are the addresses stored in the data bank, respectively.
Ai and Bi However, [] is a Gaussian symbol and represents the integer part of the numerical value in [].

It is equipped with a data bank in which the relationship is established.

(Operation) According to the present invention, the data is divided into the upper bit and the lower bit by the above configuration, and the lower bits are collectively set as one word.
Store in ROM. As a result, the number of unused bits is reduced or eliminated altogether, and the utilization efficiency of the ROM can be significantly improved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram when the information processing apparatus according to the present invention is used in an electronic musical instrument. To explain FIG. 1, 1-
1 is a keyboard. Reference numeral 1-2 is a tablet, which is an operation unit for instructing selection of a tone color of a musical sound output from the electronic musical instrument. 1-3 are effect switches, which are switches for instructing control of various effects on musical sounds, for example, on / off of effects such as vibrato and tremolo. 1-4 is a microcomputer
1-5, which is a (microcomputer) and corresponds to, for example, a microcomputer 8049 manufactured by Intel Corp., is a tone generation unit that performs waveform calculation and frequency calculation based on a control signal given from the microcomputer 1-4. Reference numeral 1-6 is a data bank, which is a ROM (read-only memory) in which waveform data and envelope data used in the musical tone generator 1-5 are stored. 1-
A filter 7 removes aliasing noise of the musical tone signal output from the musical tone generating unit 1-5. 1-8 are speakers.

Next, the operation of the electronic musical instrument shown in FIG. The microcomputer 1-4 follows the instructions written in advance inside the keyboard.
Search the status of 1-1, tablet 1-2, effect switch 1-3 in order. Also, the microcomputer 1-4 turns on the key on the keyboard 1-1.
Based on the ON / OFF state, the code of the pressed key is assigned to multiple channels of the tone generator 1-5, and an assignment signal is sent out, while the tablet 1-2 and effect switch 1-
Control data is sent according to the state of 3. Tone generator 1-
In 5, the allocation signal and other control signals sent from the microcomputer 1-4 are taken into the internal register,
On the basis of these signals, necessary tone data and envelope data are read out from the data bank 1-6 and a tone signal is synthesized. The musical tone signal synthesized by the musical tone generating section 1-5 is sent to the speaker 1-8 through the filter 1-7 to generate a musical tone.

Figure 1 (b) shows the timing chart when data is transferred from the microcomputer 1-4 to the tone generator 1-5. Table 1 shows the contents of the data sent from the microcomputer 1-4 to the tone generator 1-5. In Table 1, NOD is note octave data, which consists of note data ND, octave data OCT, and key-on data Kon. Table 2 shows the bit structure of NOD, Table 3 shows the correspondence between note data ND and note names, and Table 4 shows the correspondence between octave data OCT and range. It is shown. That is, if it is desired to output the sixth octave sound of the note G # (hereinafter abbreviated as G #) from the channel 1 to the tone generator 1-5, the address 000000 in FIG.
01, 10011110 will be sent as data from the microcomputer 1-4. Next, PDD is pitch detune data, which is 8-bit data for shifting the tuning. PDD is 2
It is represented by the complement display of, and the variable range is from -128 to +127.
There are 256 ways. RLD is release data, which is 4-bit data that controls the attenuation characteristics after key-off. VOL is a volume flag, and when this bit is set to "1", the output level of the musical tone signal from the musical tone generating unit 1-5 can be controlled according to the volume data VLD described later.
DMP is a damper flag, which is a flag that makes the attenuation after key-off in the case of a piano type envelope to be a rapid attenuation, and works when DMP = 1. SOL is a solo flag, and when a tone with the same name as another channel is assigned, it is a flag that selects whether or not to match the phase characteristics of the tone generated by that channel with the tone that is about to be generated. When = 1, phase matching is canceled. TAB is tablet data, and the data specified by tablet 1-2 in Fig. 1 is this 5
go into bit. PE is a pitch extend flag. Pitch extend is applied to the channel for which this bit is set to "1". VLD is volume data, and controls the level of the musical sound output from the channel with 8 bits of fineness together with the above-mentioned volume flag VOL. Note that this series of data can be set independently for each channel.

Next, the calculation sequence in the musical sound generating section 1-5 will be described.

Tables 5 and 6 show the operation sequence of the musical tone generator 1-5. In this tone generation unit 1-5, the operation sequence has two modes, the initial mode and the normal mode, in order to perform more data processing in a short operation cycle, and both modes are a log sequence and a short sequence, respectively. I know. The initial mode short sequence and the normal mode long sequence have two states of EVEN and ODD, respectively.

In the initial mode, when the microcomputer 1-4 commands the musical tone generator 1-5 to generate a new musical tone, the various registers etc. are initialized for the channel specified by the microcomputer 1-4 in the musical tone generator 1-5. It is a mode to set, it starts from long sequence, and after performing shunt sequence twice, it enters normal mode. Of the two short sequences in this initial mode, the first is ODD,
The second time will be an EVEN short sequence. After the end of the initial mode, the mode shifts to the normal mode, but the short sequence is repeated 6 times and the long sequence is repeated once.

In this embodiment, for each channel, two independent waveforms are multiplied by two independent envelopes, and a fine pitch adjustment function is also provided. A large number of calculation steps are required to perform the processing for eight channels in a time division manner. Therefore, short sequences are used for operations that need to be performed in short cycles, and long sequences are used for operations that are infrequently operated, that is, operations that can be performed in long cycles. The long sequence is inserted between the short sequences to improve the efficiency of calculation.

Figure 1 (c) shows the timing chart of the short sequence and log sequence. As shown in FIG. 1C, the short sequence consists of 11 time slots of (0) to (10), and the long sequence consists of 9 time slots of (11) to (19). Each time slot is 250 ns, and is divided into four, and the whole system operates with two non-overlapping two-phase clocks of ψ1 and ψ3.
The relationship between the short sequence and the long sequence is that the short sequence is 8 from channel 0 to channel 7.
Each time it is repeated, a long sequence for one channel is entered. Thus, for example, a channel 3 short sequence will occur once every 11 × 8 + 9 97 time slots and a long sequence will occur once every 97 × 8 776 time slots. Furthermore, since the normal mode long sequence has two states, EVEN and ODD,
The system is operating with 1552 time slots of 776 × 2 as a cycle.

Next, each operation sequence will be described based on Tables 5 and 6. As described above, since the musical sound generating unit 1-5 is in a new key press and starts from the initial mode long sequence, the explanation will be given for each time slot from the initial mode long sequence.

Adder (13) PDD + PED → PDR (15) 0 → TR1 (16) 0 → TR2 (17) 0 → ZR1 (18) 0 → ZR2 The time slot (13) means the contents of the register PDD. And the contents of the PED register are added to PD
It means to store in the register called R. Time slots (15) to (18) mean that 0 is written in the registers TR1, TR2, ZR1, and ZR2.

Data bank readout section (12) WTD → HAD → HAD (14) HAD → CONT → CONT, DIF1 (16) ~ (17) HAD → STE → EAR1 These meanings mean the data at the left end (for example, time slot ( If it is 14), the data called HAD) is used as an address and the data CONT described in the center is read from the data bank 1-6, and the name register CONT and
It means to store in DIF1.

Initial mode sequence Adder (1) PDR + JD LB; 0 → ER2 / 1 (3) ORG + OCT +1 → WE2 → Δ WAR (4) DB + EAR1 → EAR2 (6) 0 → WR1 (8) 0 → ER1 (9) 0 → WE2 (10) 0 WE1, WR2 0 → ER2 / 1 in time slot (1) means writing 0 to the register ER2 at the first short sequence, ODD, and ER1 at the second short sequence, EVEN. .
Further, LB means that the calculation result of PDR + JD is sent to the multiplication unit (described later) via the L bus (described later) without being stored in the register. In the time slot (3), it means that the operation result is once stored in the register WE2, then decoded and stored in ΔWAR. Time slot
DB in (4) means that the value obtained by the data bank reading unit described later is sent to the adder via the D bus (described later) without passing through a register or the like.

Multipliers (4) to (6) CB × CN1 → FR The above CB means that the result obtained by the adder is directly input to the multiplier without passing through the register, and in this case, the time slot ( It means the calculation result of PDR + JD obtained in 1).

Data bank reading section (1) HAD → ΔSTE → AB (3) ~ (4) EAR1 / 2 → E1 / 2 → ΔT1 / 2, ΔE1 / 2, ΔZ
1/2 (6) to (7) HAD → STW / ΔSTW → STW / WAR Here, AB of the time slot (1) is A of the direct addition unit that directly adds the value obtained by reading the data bank without using a register or the like. Means input to input. In addition, STW / ΔSTW → STW / WAR of time slots (6) to (7) reads the data STW at the first short sequence, that is, ODD, and stores it in the register STW, and the data ΔSTW at the second time, that is, EVEN. This means reading and storing in a register called WAR.

Next, the normal mode will be described.

Normal mode short sequence In Table 6, the part marked with * indicates that the calculation is performed only in the first short sequence after the note clock is generated, and the flag for controlling this operation is the calculation request flag CLRQ. I will call it.

Adder (1) WE2 + WE1 → LB (2) STW + WAR → DB, BB (3) ZR1 + ΔZ1 → ZR1 (4) DIF1 + CB → DB (5) ER1 + ΔE1 + Ci → ER1 (6) ZR2 + ΔZ2 → ZR2 (7) WAR + ΔWAR → WAR * (8) ER2 + ΔE2 + Ci → ER2 (9) FR + CDR → CDR * Here, the LB of time slot (1) passes the calculation result through a register. It means inputting directly to the multiplying unit. Similarly, DB and BB of the time slot (2) mean that the calculation result is directly input to the B input of the data bank reading unit and the addition unit. CB in time slot (4) is
This means inputting the operation result of the adder directly without going through a register. In this case, the ST in time slot (2)
W + WAR calculation result is input. The DB means that the calculation result is directly input to the data bank reading unit. Ci of the time throats (5) and (8) is the rounding up of calculation in the time slots (3) and (6), respectively.
It means to add (carry).

Multiplier (1) to (3) WR2 + ER2 → WE2 * (4) to (6) CB × CN → (DAC) (7) to (9) WR1 × ER1 → WE1 * where time slot (4) CB in (6) means that the output of the adder is directly input to the multiplier without passing through a register or the like. In this case, WE2 + W in time slot (1)
It corresponds to the calculation result of E1. In addition, (DAC) means that this calculation result is input to a DAC (DA converter; described later).

Data bank read section (4) to (5) CB → W1 → WR1 * (7) to (8) CB → w1 → WR2 * where CB of time slots (4) to (5) is the calculation result of the addition section Is directly input to the data bank reading unit and used as the address of the data bank 1-6. In this case, this corresponds to the operation result of STW + WAR of the time slot (2) in the adding unit. Similarly, the CBs of the time slots (7) to (8) also correspond to the calculation result of DIF1 + (STW + WAR) of the time slot (4).

Long sequence adder (13) ΔT1 / 2 + TR1 / 2 → TR1 / 2 (14) PDR + JD → LB (15) ΔEAR1 / 2 + EAR1 / 2 + Ci → EAR1 / 2 (16) PDD + PED → PDR Here, LB of the time slot (14) means that the calculation result of the adder, that is, the value of PDR + JD is directly input to the multiplier without passing through the register. Ci of time slot (15) is a rounded up result of the calculation of time slot (13)
Means (carry).

Multipliers (16) to (18) CN + CB → FR where CB means to input the operation result of the adder directly to the multiplier without passing through the register. In this case, adder time slot (14) The calculation result of PDR + JD in is input.

Data bank readout section (14) to (15) EAR2 / 1 → E2 / 1 → ΔT2 / 1, ΔE2 / 1, ΔZ2
/ 1 Here, 2/1 means odd number of times, that is, 2 at 0DD
(E2 for E2 / 1, for example), 1 for the even number of times, ie EVEN
(Same E1) means that another data is read by EVEN and ODD and stored in another register.

FIG. 2 is a detailed diagram of the musical sound generating section 1-5 in FIG. First, the outline of the function of each block will be described with reference to this figure. 2-1 is a master clock.
= 8.00096MHz is used. 2-2 is a sequence
(Hereinafter referred to as SEQ), which divides the clock signal by the master clock 2-1 to generate a sequence signal (hereinafter referred to as SQ signal) and various control signals in the entire musical tone generating section 1-5. 2-3 is a microcomputer interface unit (hereinafter referred to as UCIF), and various data shown in Table 1 are sent from the microcomputer 1-4 asynchronously with the tone generation unit 1-5.
This circuit takes in this data and synchronizes with the SQ signal generated by SEQ. Further, the flag Kon generates a flag INI for instructing the mode switching between the initial mode and the normal mode. 2-4 is the comparison register (hereinafter C
It is referred to as DR), and compares 8 channels of the register CDR shown in the above operation sequence with a 10-bit frequency-divided signal obtained by sequentially dividing the master clock, and outputs a note clock for 8 channels and a calculation request flag. Generate CLRQ. 2-5
Is a radam access memory unit (hereinafter referred to as a memory), which stores various calculation results performed in the tone generation unit 1-5. 2-
6 is a full adder unit (hereinafter referred to as FA), which has a built-in 16-bit full adder that adds various data. 2-7
Is a multiplication unit (hereinafter referred to as MPLY), and has a multiplier that performs (2's complement 12 bits) × (absolute value 10 bits). Reference numeral 2-8 is a digital-analog converter (hereinafter referred to as DAC), which converts the digital musical tone data output from the MPLY2-7 into analog musical tone data. 2-9 is the analog buffer memory section (hereinafter A
BM) is used to convert the tone data generated by the DAC2-8 in the machine cycle period into pitch synchronization by the note clock generated by the CDR2-4. The ABM2-9 has the same function and configuration as the analog buffer memory disclosed in Japanese Patent Laid-Open No. 59-214091. 2-10 is the input / output circuit section
(Hereinafter referred to as I / 0), send an address signal to the data bank 1-6, read the waveform data and envelope data corresponding to the address signal, and convert the read data as necessary. To do. 2-11 is a matrix switch part (hereinafter referred to as MSW), which is UCIF2-3,
Horizontal bus line connected to CDR2-4, memory 2-5
(HA, HB, HC, HD, HE, HL buses) and FA2-6, MPLY2-7
, I / 0 2-10 connected to the vertical bus line (A,
B, C, D, L buses) according to the SQ signal. These circuits execute the operation sequences shown in Tables 5 and 6.

Next, individual blocks will be described.

FIG. 4 is a detailed view of SEQ2-2 in FIG.

4-1 is a counter that divides the master clock and
It generates various timing signals shown in FIG. TS is a signal that represents the time slot in FIG.
C is a channel code, which is a signal representing the channel number in FIG. EV is a signal representing 0DD and EVEN in the calculation sequence, and EV = 0 is 0DD,
EV = 1 means EVEN. 4-2 is SQROM (sequence ROM)
The signal TS indicating the time slot and the flag INI are input to the address input of the SQROM4-2, and various control commands in each time slot are generated based on these inputs. 4-3 is a logic gate, SQROM4-2
Further control the output by the various flags and calculation request flag CLRQ, etc., and instruct how each functional block should operate for each time slot according to the instruction of SQ signal (performance information, effect switch 1-3, etc.). Signal (abbreviated as SQ in the figure) is generated.

Figure 5 is a detailed diagram of UCIF2-3. In FIG. 5, 5-
Reference numeral 1 is a latch which latches A / Ds 0 to 7 given by the microcomputer 1-4 in FIG. 1 by ALE. A / D 0
Since the relationship between 7 and ALE is as shown in Fig. 1 (b),
The addresses shown in Table 1 are latched in the latch 5-1. 5-2 is a latch, which latches A / Ds 0 to 7 given by the microcomputer 1-4 with ▲ ▼. A / D 0
Since the relationship between 7 and ▲ ▼ is as shown in FIG. 1 (b), the data shown in Table 1 is latched in the latch 5-2. 5-3 is a latch, which is controlled by ▲ ▼ and latches the output of latch 5-1. The reason why the address is latched in two stages is that the ALE becomes “1” periodically regardless of ▲ ▼, and by latching the address in two stages in this way, new data by ▲ ▼ Addresses and data are stored in the latches 5-3 and 5-2 until writing is performed. Five-
Reference numeral 4 is a 1-word 8-bit RAM, A is an address input, OE is an output control terminal, and a data terminal D is connected to the HE bus. Here, when OE = 1, the data of the address given by the A input is output from the D terminal. WE is a write control terminal, which writes the data given to the D terminal when WE = 1 to the address given by the A input.
OE and WE are controlled by the SQ signal. In RAM5-4, various data (NOD, PDD, RLD, VOL, DMP,
SOL, TAB / PE, VLD), control data CONT (written from the data bank, details will be described later), and data PDR of the pitch data register are stored for 8 channels each. Reference numeral 5-5 is a selector, which selectively outputs the address designated by the microcomputer 1-4 and the address designated by the SQ signal by using another SQ signal, and supplies it to the A input of the RAM 5-4. A signal processor 5-6 is connected to the HE bus and takes in data on the bus to generate various flag signals. Also, 16 types of release envelope data corresponding to 4 bits of release data RLD sent from the microcomputer 1-4 are generated and sent to the HE bus. 5-7 is a gate, SQ
The output of the latch 5-2, that is, the data from the microcomputer 1-4 is sent to the HE bus according to the signal.

Next, the operation of UCIF2-3 will be described.

Assuming that the data shown in Table 1 is given from the microcomputer 1-4 at the timing shown in Fig. 1 (b), the address
05 ₁₆ , data is 89 _{16, that} is, if channel 5 is instructed to press the key of F # 1, first the address is latched in the latch 5-1 by the ALE signal, and then by the ▲ ▼ signal.
At the same time as the data is latched in 5-2, the address is latched in the latch 5-3. Then, at a predetermined timing, the selector 5-5 selects the output of the latch 5-3, the gate 5-7 is opened at the same time, and the write signal is given to the WE of the RAM 5-4. By this write signal, the data latched in the latch 5-2, that is, the data that the microcomputer 1-4 tried to write, that is, 89 ₁₆ is given to the HE bus, and the latch is input to the A input of the RAM 5-4.
Since 05 ₁₆ which is the output of 5-3 is given, the data of 89 ₁₆ is written to the address 05 _{16 of} RAM 5-4. In this way, the various data shown in Table 1 are written in the RAM 5-4. As shown in Table 1, RAM5-4 has VOL flag,
Flags such as PE flags are written, but these flags are sent to the signal processor 5-6 via the HE bus and once latched here, they are used.

FIG. 6 is a detailed diagram of CDR2-4. 6-1 is a 10-bit frequency divider with the master clock as input. 6-2 with comparator
RAM (hereinafter referred to as CDRAM), 8 bits per word 13 bits
Have a word. A comparator is provided for the upper 10 bits of each word, and the data is compared with the divided data by the divider 6-1 input from terminal T. If all 10 bits match, a match pulse is output from terminal C. Is output. OE, WE,
The functions of A and D are the same as those of the RAM 5-4 described above. 6-3 is a decoder, and the relationship between A input, EN input and D output is as shown in Table 8. 6-4 to 6-11 are RS latches, and when a positive pulse is applied to the S input, the Q output becomes "1", and when a positive pulse is applied to the R input, the Q output becomes "0". RS latch
6-4 is channel 0, RS latch 6-5 is channel 1, ...
The coincidence pulse of ... Is given to S. 6-12 is a selector, which selects the channel code CH from the 8 signals given to the A input.
One of the signals is selected by the C 3 bit and output from D. 6-13 is a latch, which selects according to the SQ signal.
Latch the output of 6-12. 6-14 is an AND gate.

Next, the operation of CDR2-4 shown in FIG. 6 will be described. The frequency divider 6-1 divides the master clock to give a 10-bit frequency division output to the T input of the CDRAM 6-2. Each word of the CDRAM6-2 contains an arbitrary value, but a matching pulse is output from the C terminal every time the upper 10 bits of these values match the output value of the frequency divider 6-1. A signal representing CHC, that is, a channel is input to the A input of the CDRAM 6-2, so that each word corresponds to each channel, and therefore a coincidence pulse is generated for each channel. This coincidence pulse is RS
Since it is input to the latches 6-4 to 6-11, the Q output of the RS latch corresponding to the channel in which the coincidence pulse is generated is set to "1". One of the Q outputs of the RS latches 6-4 to 6-11 is selected according to the channel code CHC 6-
It is sequentially selected by 12 and latched in the latch 6-13. The output of latch 6-13 is given to AND gate 6-14, so
If the Q output of the RS latch currently selected by the selector 6-12 is "1", the corresponding channel of the D output of the decoder 6-3 becomes "1" by the SQ signal applied to the AND gate 6-14. The Q output of the above RS latch is reset to "0".

FIG. 7 is a detailed view of the memory 2-5. In FIG.
7-1 to 7-4 are RAMs, and the functions of OE, WE, A, and D are the same as those of the RAM 5-4 described above. Here, RAM7-1 has WAR and EA
R1, ΔZ1, ΔE1, WE1, EAR2, ΔZ2, ΔE2 registers are stored in RAM7-2 in WR2, ZR1, ΔT1, FR, ΔWAR, ZR2,
Each register of ΔT2 is ER1, TR1, DIF1, DW in RAM7-3.
1, ER2, TR2, STW, TAB ', and HAD registers are R
The AM7-4 stores NOD ', WE2, and VLD' registers for eight channels each. NOD ', TAB',
VLD 'is the data of NOD, TAB, and VLD in RAM5-4 described above. 7-5 is 1 word 10 bits 13
It is a ROM of words and stores the note coefficient CN in the operation sequences shown in Tables 5 and 6. Here, Q is an output, A is an address input, and OE is an output control terminal. When OE = 1, the contents of the ROM are output, and when OE = 0, Q = high impedance. The value of note coefficient CN is shown in Table 7. The 10-bit output of ROM7-5 is connected to the lower 10 bits of the HD bus. 7-6 is a signal processor, which reads ND (note data) and OCT (octave data) from NOD 'stored in RAM 7-4 and generates peach detune data PED based on these data and PE flag. , And a decoding circuit for reading and decoding the data in the register WE2.

Figure 8 is a detailed diagram of FA2-6. In FIG. 8, 8-1
8-8 are latches, which operate with the signals ψ1 and ψ3 generated by SEQ2-2. An adder 8-9 adds the value given to the A input, the value given to the B input (both 16 bits) and the value given to the carry input Ci, and outputs from C and Co. Co is the carry output resulting from the operation. 8-10 and 8-11 are bit processing circuits, and latches 8-1 and
It is a row circuit that performs bit manipulation of the output by the latch 8-2. 8-
Reference numeral 12 is a logic gate which forcibly sets the output of the latch 8-6 to "1" or "0" according to the SQ signal. Alternatively, the output is performed as it is. 8-13 is a RAM, the size of which is 9 bits per word and 12 words.
The functions of A, D, WE, and OE are the same as those of the RAM 5-4 described above.
The D output 9 bits are connected to the lower 9 bits of the C bus.

RAM8-13 is a phase register for phase adjustment (discussed later).
Addresses (WA) for reading individual waveform data of sound notes
R) phase management.

FIG. 9 (a) is a detailed view of MPLY2-7. 9 in Fig. 9
-1 to 9-9 are latches. Here, the latch 9-3 is connected to bits 0 to 9 of the L bus, and the latch 9-5 is connected to bits 9 to 12 of the L bus. 9-10 is an encoder. The input / output relationship is shown in Table 9. 9-11
Is a shifter, which converts a 16-bit signal input from I to C
It is output from the shift O according to the control signal input to.
The details of the shift are shown in Table 10. 9-12 is a bit processing circuit, which performs bit processing of the signal output from the latch 9-3 according to the SQ signal. 9-13 is a decoder for input A
And the output d is shown in Table 11. 9-14 is a selector, which responds to the SQ signal input to C by C
If = 1, the 16 signals input to A if C = 0 and B are selected and output from Y. The lower 11 of A input
The bit is connected to GND (ground potential) (that is, "0" is given). 9-15 is a shifter and is input from I 14
The bit signal is shifted according to the control signal input to C and output from O. The details of the shift are shown in Table 12. Reference numeral 9-16 denotes a multiplier, in which the A input is 12 bits in the complement notation, the B input is 10 bits in absolute value, and the output is 14 bits in the 2's complement notation. Normally, when a 12-bit x 10-bit operation is performed, the result of 22 and 22 bits is obtained. Of course, the 14-bit output of the multiplier 9-16 is the upper 14 bits of the 22-bit. Therefore, the input / output relationship in the multiplier 9-16 is as follows.

The multiplier 9-16 in MPLY2-7 uses the following method in order to further simplify the circuit.

When constructing a normal multiplier, the multiplier of 2's complement value of 12 bits × absolute value of 10 bits can obtain an accurate calculation result of 22 bits by 116 adder cells. However, in this system, only the upper 14 bits of the 22 bits originally obtained are used. That is, since the output of the lower 8 bits is not used, the arithmetic error due to the omission of the adder cell is higher in the present embodiment.
All the adder cells for the lower 7 bits that do not affect the LSB of the bit are omitted. So, in this multiplier 9-16,
The adder cell 28 for lower bit operation is omitted in FIG.
The configuration is shown in (b). In FIG. 9B, similar cells are abbreviated in broken lines. Further, each block is a full adder, the inputs are A, B, Ci (carry input), and the outputs are sum S and carry Co.

Figure 10 is a detailed view of I / O 2-10. 10-1 in FIG.
~ 10-8 are latches. Here, the latch 10-3 is a latch with a set, and the input of the latch is bit 7 to bit 9 of the D bus.
It is connected to the. Numeral 10-9 is a shifter selector, which switches between A input and B input by C input and shifts A bit by 1 bit. A bit processing circuit 10-10 is a circuit for forcibly setting the lower 3 bits to "1" or "0" according to the SQ signal. Reference numeral 10-11 is a decoder, and the relationship between the input I and the output D is shown in Table 13. Decoder 10-11 A
Bits 12 to 15 of the output of the latch 10-7 are given to the input. Reference numeral 10-12 is a selector, which selects either the signal given to A or B according to the C input and Y
Output more. Reference numeral 10-13 is a shifter which shifts the input from I according to the input of the control terminal C and outputs it from O.
10-14 is a noise circuit, which mixes noise with the input data according to the noise flag NA.

Figure 11 (a) is a detailed diagram of NSW2-11. The part surrounded by a circle is a switch. Specifically, as shown in Fig. 11 (b),
It is composed of Nch MOSFET. When the SQ signal becomes "1", the MOSFET is turned on and the vertical line and the horizontal line are conducted to transfer data. In this MSW2-11, for speeding up, all the bus lines are precharged by the ψ1 signal for each time slot immediately before the data transfer, and then the data transfer is performed. This is to prevent the level of "1" of the transferred data from dropping by the threshold voltage of the MOSFET because the switch is composed of the Nch MOSFET. Figures 11 (c) to 11 (d) show MSW2
-11 is an example of the switch pattern used in
The points of intersection surrounded by circles are connected via switches. In this example, each bus will be described as having 8 bits for convenience. In Fig. 11 (c), bn and an (n
= 0 to 7). Figure 11 (d) shows b0 to b
The four values of "3" and "0" are written to the vertical bus by a switch. Figure 11 (e) shows b0 to b3
Are written to a0 to a3 and c4 to c7 are written to a4 to a7, so that the data that appears separately on two sets of buses can be mixed and transferred to another bus. It is the one. Figure 11 (f) shows the bit positions converted and transferred from bus to bus. By arranging the switches in this way, the positions of the upper and lower 4 bits of the horizontal bus data can be changed. Transfer to the vertical bus. First
11 (g) to 11 (i) are circuit examples for setting constants in the bus, and FIG. 11 (g) is a circuit for setting all "0" s in the bus, FIG. 11 (h). Is a circuit that sets 10101010 or AA ₁₆ on the bus. This is the part without switch a7,
A5, a3, and a1 are due to the fact that "1" is written by precharging just before this switch is opened and is retained. In FIG. 11 (i), the value of the constant is changed by the flag T0. If T0 = 0, 00 ₁₆ is written in the bus, and if T0 = 1, EB ₁₆ is written in the bus. First
Data transfer from any bus to any other bus is required by arranging the switches shown in Figures 11 (c) to 11 (i) on the MSW2-11 according to the application and selectively opening / closing. It is possible to include various bit processing. For example, from HA bus to A bus,
To transfer data from HB bus to B bus and from C bus to HC bus at the same time, SW1, SW7 and SW13 should be turned on at the same time. If you want to transfer the data on the C bus to the L bus and D bus, turn on SW28, SW29, and SW30.
Data is transferred via the route from HL bus to L bus and D bus.

In MSW2-11, data transfer is performed at the timing shown in FIG. That is, the vertical and horizontal bus lines are precharged in the section of ψ = 1, data is transferred in the section from the falling edge of ψ1 to the falling edge of ψ3, and latched at the falling edge of ψ3. Here, the interval from the falling edge of ψ3 to the rising edge of ψ1 is a margin for stable latch operation.

Next, the data banks 1-6 will be described. Data bank
4 types of data are stored in 1-6. that is,
They are (1) header address data, (2) header data, (3) waveform data, and (4) envelope data. Here, the header address data is 8-bit data indicating at which address the header data is stored, and the header data is 8 bytes representing the address where the waveform data and the envelope data are stored and their attributes. Data. Next, the four types of data will be described in more detail.

(1) Header Address Data (HAD) This data is data indicating the address of the header data with the note data assigned to each tablet, each octave, and each three keys as an address. The storage location of the header address data is as shown in Table 14, bit 9 to bit 5 is tablet data TAB, bit 4 to bit 2 is octave data OCT, bit 1 to bit 0 is the upper 2 bits of note data ND, All the remaining bits contain "1". It goes without saying that the 10 bits composed of TAB, OCT and ND are called WTD, and each of them is as shown in Table 1. The header data address according to the header address data is shown in Table 15, the header address data is contained in bits 10 to 3, and the upper bits are all "1". Data of 000 to 111 are put in the lower 3 bits.

(2) Header data (HD) Header data is 8-word data of 1 word 8 bits stored in the addresses shown in Table 15, and the contents of 8 words are as shown in Table 16. In Table 16, CONT is control data and represents the attributes of the waveform data and envelope data indicated by this header data. E1 'is one of the two types of envelope data. The start address of the other envelope data E2 'is given by STE + ΔSTE. W1 and W2 are two types of waveform data, and the start address of W1 is STW
It is given by + ΔSTW.

The CONT has the structure shown in Table 17, and its meaning is as follows.

P / 0: A flag indicating whether the musical sound according to this header data has a piano type envelope or an organ type envelope. If P / 0 = 1, it means that it is a piano type.

ORG: 3-bit information indicating which musical range the pertinent musical sound data originally belonged to. The correspondence between ORG and musical range is the 18th.
As shown in the table. Therefore, it is also information indicating how many samples the waveform data actually have for one cycle.

W8: Indicates whether the waveform data has 12-bit precision or 8-bit precision. If W8 = 1, 8-bit precision is obtained. W8
When = 1, 4-bit "0" is added to the lower part of the waveform data, and the amplitude level of the waveform is maintained.

PCM: PCM = 1 indicates that the rising edge of the waveform data W1 is PCM.

NA: A 2-bit signal used when a noise signal is superimposed on a musical tone signal.

(3) Waveform data (W1, W2) As described above, the tone generator 1-5 uses two types of waveform data, 12-bit data and 8-bit data. Most of the commercially available ROMs have a word of 8 bits or less, and a word of 12 bits is rare. Therefore, in the present invention, the waveform is stored in the ROM as follows.
That is: In the case of 8 bits, 1 word is sequentially stored from the address determined by STW and ΔSTW, but 1 word
In the case of 12-bit waveform data, the upper 8 bits are stored sequentially from the address indicated by STW + ΔSTW as shown in Fig. 12, but the lower 4 bits are shifted right by 1 bit from STW + ΔSTW to MSB. Two words are sequentially stored in the lower 4 bits and the upper 4 bits of the address in which 1 is entered. For example, if the location of the lower 8 bits of the upper 8 bits of the waveform data at address 0445 ₁₆ is 12
It means that it is the upper 4 bits of 22 ₁₆ and the address 0445 ₁₆
It comes to the lower 4 bits of the address 1222 ₁₆ for.

In this way, the waveform data is efficiently stored in the ROM. That is, if the address is assumed to be ROM to 0000 ₁₆ ~FFFF _16, the upper 8 bits of the 12-bit waveform address 0000 ₁₆ ~7FFF ₁₆ is stored, the address 8000 ₁₆ ~BFFF
_{In 16} are stored the lower 4 bits of each. Address C0
12-bit waveform data cannot be stored in 00 _{16 to} FFFF ₁₆ , but if 8-bit waveform data or envelope data described later is stored, the ROM can be used almost without waste.

In this embodiment, the case where the waveform data is 12 bits is shown. However, when the waveform data is 10 bits, the upper 8 bits of the address are right-shifted by 2 bits and the upper 2 bits are set to 1 by 2 to the address. It is advisable to store the lower 2 bits of 4 words bit by bit. For example, the upper 8 bit address is 12
22 ₁₆ if the lower 2 bits are the address C488 ₁₆
Will be stored in bit 4 and bit 5. In this way, if the ROM address is 0000 ₁₆ ~
If FFFF ₁₆ , the upper 8 bits of the waveform data are addressed
Store in 0000 _{16 to} BFFF ₁₆ and lower 2 bits are address CFFF
_{Since 16 to} DFFF ₁₆ are stored, various data can be stored efficiently.

(4) Envelope data (E1 ', E2') The envelope data is 16 bits and forms one word, and its data format is as shown in Table 19. Δ
T is data that determines the update interval of the envelope address. S is a flag indicating the inclination (increase or decrease) of the envelope. Z is a flag indicating the magnitude of the inclination of the envelope, and DATA is the magnitude thereof. The data shown in Table 19 is stored in the data bank according to the address defined by STE and ΔSTE shown in Table 16.

Since the data bank is configured as described above, the tone color can be changed for every three adjacent keys, while conversely, if the same header address data is provided in the same octave, waveform data can be obtained. , Tones of the same tone color can be obtained without increasing the envelope data and the header data. Further, since arbitrary waveform data and envelope data can be specified in each header data, it is possible to generate various musical tones even with a small amount of waveform data and envelope data, depending on how they are combined.

Next, the initial processing when the key is pressed in the tone generator 1-5,
This section describes the note clock generation method, envelope generation method, and waveform generation method.

(1) Initial processing In the initial processing, various registers are initialized when a musical sound is generated by pressing a key. Since the arithmetic sequence is started from the long sequence in the initial mode by pressing the key, the PDR is initialized in the time slot 13 in the adder. This operation will be described in more detail. PDD is read from RAM5-4 in FIG. 5 and data is loaded on the HE bus. At the same time, PED is given to the HD bus from the signal processor 7-6 in FIG.
SW17 turns on, PDD rides A bus, PED rides B bus. This data is added by FA2-6 shown in FIG. 8 and the calculation result is put on the C bus. This calculation result is sent via SW23
Take the HE bus and store it in the register PDR in RAM5-4. In this calculation, the PDD and PED are transferred to the FA2-6 one time slot before the time slot when the PDD + PED calculation is actually performed, and the calculation result is stored in the PDR one time when the PDD + PED calculation is performed. Done after the slot. The same applies to the following addition operations. Then TR1, TR2, ZR1, ZR2 in time slots (15) to (18)
"0" is written in. This operation will be described by writing "0" in TR1. At time slot (15), SW33 and SW13 are turned on in MSW2-11 of FIG. 11 (a). SW33 has a structure as shown in FIG. 11 (g), and "0" is given to the C bus. At the same time, SW13 is on, so the data on the C bus is given to the HC bus, as shown in Fig. 7.
"0" is written to the register TR1 in RAM7-3.

On the other hand, the data bank reading section operates as follows. The description will be centered on FIG. 10 below. TAB, ND, OCT
The header address data HAD is read by the WRD composed of. In the initial mode in which this initial processing is performed, the latch 10-3 operates 111 by the SQ signal.
Is set to. This data is converted into the format shown in FIG. 15 by the shifter 10-13 in the I / O 2-10 and stored in the register HAD of the RAM 7-3 via the D bus SW15 and the HC bus. At the same time as this operation, the header address data HAD read from the data bank is latched by the latch 10-8 and the latch 10-6 one after another, and the data is formatted by the shifter selector 10-9 as shown in Table 15. Is converted and latched in the latch 10-4. Latch 10-4
First, the bit processing circuit 10-10 gives 000 to the lower 3 bits, and the control data CONT is read from the data bank 1-6 and the upper order of the latch 10-7 via the latch 10-8. Latched to 8 bits. The control data CONT is stored in the register CONT of the RAM 5-4 via the D bus via the selector 10-12, the shifter 10-13, the noise circuit 10-14 and the latch 10-2. On the other hand, since the upper 4 bits of the latch 10-7 are connected to the decoder 10-11, 16-bit data can be obtained according to the truth table shown in Table 14. However,
At this time, the C input of the decoder 10-11 is "1". Selector 10-12 selects this decoder output,
The shifters 10-13 shift right by 6 bits and output. Considering the output of this shifter 10-13, the latch
The data input from 10-7 to decoder 10-11 is P / 0.
And ORG 3 bits. Since the C input of the decoder 10-11 is "1" now, the output of the decoder 10-11 is determined only by the ORG 3 bit. Therefore, the value obtained by right-shifting the output of the decoder 10-11 by 6 bits by the shifter 10-13 is the value shown in Table 18. This value is given to the D bus through the noise circuit 10-14 and the latch 10-2, and in MSW2-11 via SW15.
It is stored in the register DIF1 of RAM7-3.

Next, the bit processing circuit 10-10 gives 001 and then 010 to the lower 3 bits to the output of the latch 10-4, and reads the upper 8 bits and lower 8 bits of the STE of the header data. The value of this STE is given to the D bus via the selector 10-12, shifter 10-13, noise circuit circuit 10-14 and latch 10-2, and MSW2-11 registers EA of RAM7-1 via SW5.
Store in R1.

Then enter the short sequence. The short sequence is executed twice. PDR and JD are added in time slot (1), where JD is a constant and SW32 in MSW2-11.
It is obtained by turning on. SW32 is configured as shown in FIG. 11 (h), has a JD = 45B _16.
This addition result is multiplied by the note coefficient CN to obtain FR. To explain this series of rounding operations in detail, PDR + JD is calculated in the time slot (1) and the result is given to the C bus in the time slot (2) as described above. MS here
In W2-11, SW28 and SW29 turn on, C bus → HL bus →
Data is transferred in the order of the L bus, and MP in Fig. 9 (a)
Latched to the LY2-7 latch 9-1. In the next time slot (3), note data ND is read by ROM7-5 in FIG.
The value of CN corresponding to is read and given to the HD bus. This value is given to the L bus via SW19 in MSW2-11 and latched in the latch 9-3 of MPLY2-7. Latch 9-1
Output to latch 9-2 via shifter 9-11, latch 9-3
Is output to the latch 9-4 via the bit processing circuit and is latched. Therefore, the value of PDR + JD is latched in the latch 9-2, and the value of CN is latched in the latch 9-4. Then the multiplier
9-16 calculates the product of (PDR + JD) and CN, and it is sent to latch 9-8 via shifter 9-15 and latched. Note that in these series of operations, the shifter 9-11 and the bit processing circuit 9-1
2. The shifters 9-15 operate to let data through. That is, "1" is given to the C input of the encoder 9-10. The value of the latch 9-8 is stored in the register FR of the RAM 7-2 from the L bus via the SW9 of the MSW2-11. Therefore, in time slot (2), ORG + OCT + 1 is calculated. In this operation, the operation of +1 is performed by the logic gate 8-12 in FA2-6 of FIG. That is, if the logic gate 8-12 forcibly outputs "1" in the corresponding time slot, the latch 8-5 latches "1" and gives "1" to the Ci input of the adder. The meaning of this operation is as follows. That is: ORG indicates a value indicating which tone range the waveform data originally belongs to (provisionally N) in the form of the inverse logic of the octave data OCT. Table 18 and 22 show the relationship between OCT and ORG and the number of waveform samples.
Shown in the table. Therefore, ORG +1 represents -N. In other words, ORG + OCT + 1 = OCT-N, which is the difference between the tone range of the tone signal that is currently being generated and the original tone range of the waveform data that is actually being used, that is, the amount of octave shift. Is a value indicating. That is, it indicates how many octaves higher the range waveform is to be read as sound. This value is temporarily stored in the register WE2 of the RAM7-4, then decoded by the signal processor 7-6 and stored in the register ΔWAR of the RAM7-2. ORG + O
The values of ΔWAR with respect to the value of CT + 1 are as shown in Table 20.

Hereafter, in time slot (4), EAR2, same (6), (8),
In steps (9) and (10), the WA1, ER1, WE2, WE1, and WR2 registers are initialized.

On the other hand, in the data bank reading section, the header address data HA stored in the RAM7-3 in the long sequence described above is used.
Read D, D bus → latch 10-1 → shifter selector 10
Latch to latch 10-4 via -9, bit processing circuit 10-1
When the value is 0, 001 is input to the lower 3 bits to read the header data ΔSTE from the data bank. This value is latch 10-7 →
Selector 10-12 → shifter 10-13 → noise circuit 10-14 → is given to the D bus via latch 10-2, and at MSW2-11
Input to A bus via SW26 and SW30 and EAR1 at FA2-6
Is added. Next, STE (start address of envelope data E1 ') stored in register EAR1 of RAM7-1
Is read, D bus → latch 10-1 → shifter selector 10
Latched by latch 10-4 through -9. The bit processing circuit 10-10 inputs “0” and then “1” to the LSB of the output of the latch 10-4, and outputs 2 as shown in Table 19.
Read byte envelope data. 16 bits of this value are latched into latches 10-7. According to the output of the latch 10-7, ΔT1, ΔE1, ΔZ1,
The values of ΔT2, ΔE2, and ΔZ2 are generated in the second short sequence. First, the upper 4 bits of the latch 10-7 are input to the decoder 10-11, and the upper 4 bits of the latch 10-7 contain the value of ΔT shown in Table 19.
Therefore, the decoder 10-11 decodes ΔT according to Table 13 and outputs it to the selector 10-12. At this time, in the selector 10-12, C = 1 is set and the B input is selected and the shifter 10-1 is selected.
Output to 3. This selector 10-12 output is shifter 10-13
, The noise circuit 10-14 is given to the D bus through the latch 10-2 without any bit operation being performed, and M
Stored in register ΔT1 of RAM7-2 via SW10 and HB bus in SW2-11. ΔE1, ΔZ1, ΔE2, ΔZ2 are the 19th
Shifter 10-1 according to Z, S and DATA shown in the table
Bits are manipulated in 3 and stored in each register.
What kind of bit operation is performed is as shown in FIG. It is shown that the data format differs depending on the value of Z in Table 19.

Next, the value of register HAD is read from RAM7-3 and latched in the same manner as when reading ΔSTE from data bank 1-6.
The data bank is latched at 4 and the bit processing circuit 10-10 gives 100 to the lower 3 bits of the header address data HAD in the initial mode, then 101, 110 in the second initial mode, and then 111.
Read STW and ΔSTW from 1-6 and store STW in register STW and ΔSTW of RAM7-3 in register WAR of RAM7-1.

By the above, the initial setting of all the registers is completed.

(2) Note clock generation method First, the principle of the note clock generation method used in the tone generation section 1-5 will be described with reference to FIG. In FIG. 3, 3-1 is a frequency divider, which divides the master clock input to the terminal CK and outputs a 10-bit divided output from Q. 3-2 is a comparator, A input And B input are compared, and when A = B, "1" is output from Q. 3-3
Is a flip-flop, which takes in the signal given to the D input at the rising edge of the CK input and outputs it from the Q. 3-4 is an adder, which outputs the sum of A input and B input from C. 3-5 is a constant circuit for inputting a constant M to the B input of the adder 3-4. 3-6 is an RS latch, which becomes Q = 1 when a positive pulse is input to the S input, and Q = when a positive pulse is input to the R input.
It becomes 0. 3-7 is a delay circuit, which delays the input signal and outputs it. 3-8 is an AND gate.

Next, the operation of FIG. 3 will be described. First, the Q of RS latch 3-6
If the output is "0", the output of the AND gate 3-8 is always "0", so that the Q output of the flip-flop 3-3 is constant. On the other hand, the frequency divider divides the master clock
It outputs a 10-bit Q that repeats 000 ₁₆ to 3FF ₁₆ . If the output of the flip-flop 3-3 is N,
Of course, 000 ₁₆ ≤ N ≤ 3FF ₁₆ , so be sure to someday divide by 3-1
There is a moment when Q output of N becomes N, and at this time, comparator 3-2
A coincidence pulse is output from the Q output of. Then, since the coincidence pulse is input to the S input of the RS latch 3-6, the Q output of the RS latch 3-6 becomes “1” and the write pulse is ANDed.
Output from gate 3-8. D of flip-flop 3-3
Since the C output of the adder 3-4 is given to the input, N +
The value of M is written. At the same time, the write pulse is delayed by the delay circuit 3-7 and then the Q output of the RS latch 3-6 is set to "0". Therefore, the Q output of the flip-flop 3-3 becomes constant again, but the value changes from N to N + M. Therefore, next, when the Q output of the frequency divider 3-1 becomes N + M, a coincidence pulse is generated. By repeating this, the comparator 3-2 outputs the output value of the frequency divider 3-1 as N, N +.
Generates a pulse when M, N + 2M ... That is, each time the frequency divider 3-1 counts the master clock M times, a coincidence pulse is generated. Further, when N + nM> 3FF ₁₆ , the output of the adder 3-4 becomes N + nM-3FF ₁₆ after overflow, so that it goes without saying that a coincidence pulse is generated when the master clock is counted M times. . That is, this comparator
If the coincidence pulse of 3-2 is used as a note clock and the constant M is changed, note clocks of various periods can be obtained, and the frequency thereof is (master clock frequency) / M. Also, the Q output of SR latch 3-6 is the calculation request flag CL.
Corresponds to RQ.

The above is the principle of the note clock generation method in the present invention.

Next, the details of the operation sequence of note clock generation in the musical tone generating section 1-5 shown in FIG. 1 will be described.

A key is pressed on the keyboard 1-1, and the microcomputer 1-4 generates a musical sound
When the musical tone is instructed to 1-5, the operation sequence starts from the initial mode long sequence as described above. First, in the time slot (13), PDD + PED → PDR ...... (2-1) Then, enter the short sequence and time slot (1)
… In (6), PDR + JD → LB (2-2) CB × CN → FR (2-3) is calculated. Then, the normal mode is entered, and FR + CDR → FR …… (2-4) in the short sequence time slot (9) and PDR ＋ JD → LB …… (2- 5) CB × CN → FR …… (2-6) PDD + PED → PDR …… (2-7) is calculated. Here, PDD is the PDD shown in Table 1.
That is, it is pitch detune data, and PED is the above-mentioned pitch extend data. JD is a constant and is 11 15 ₁₀ (1
A value of 45B) is set in hexadecimal. Note coefficient
CN is a value determined by the assigned note name.
The CN relationship is shown in Table 7. As described in the explanation of Table 5 and Table 6, calculation (2-2), (2-3) and calculation (2-5)
, (2-6) can be expressed as the following equation.

(PDR + JD) × CN → FR ...... (2-8) Here, since PDR is PDD + PED, the operation (2-8) is (PDD + PED + JD) × CN → FR ...... (2-9 ). The value of this FR is accumulated in CDR as shown in the operation (2-4). As described above, this accumulation is performed once every time the note clock is generated. Therefore, if the initial value of CDR is N, the value of CDR changes to N, N + FR, N + 2 × FR, .... The upper 10 bits of this CDR are compared with the 10-bit frequency-divided signal obtained by sequentially dividing the master clock, and a match pulse is generated. And the upper 10 bits of CDR are the 3rd
FR / 8 corresponds to the value M of the constant circuit 3-5 in FIG. 3. Therefore, the above (2-1) ~ (2-7)
If you perform the calculation of Becomes

(3) Waveform generation method The waveform generation method shown in Fig. 1 musical tone generator 1-5 is roughly divided into the following five steps. That is: Address generation Generates an address when waveform data is read from the data bank 1-6.

Waveform reading The waveform data specified by the above address is stored in the data bank.
Read from 1-6 and perform bit processing according to control data CONT.

 Envelope multiplication Two-wave mixing CN multiplication Each step is described in detail below.

Address generation STW (W2
Start address), ΔSTW (the number of W1 words), and DIF1 (the number of samples included in one waveform) are registered in STW, WAR, and DIF1.
Is stored in, and the register ΔWAR is determined by calculation. Addresses are generated in normal mode based on these data. In the following processing, when the waveform data has a PCM part (PCM = 1) and when it does not (PCM = 0)
Since the address generation is different, the explanation will be given separately for the case where there is a PCM part and the case where there is no PCM.

When there is no PCM part, as shown in Table 6, in the time slot (2), STW and
Calculate the sum of WAR, read waveform 1 from data bank 1-6 with this sum, and add DIF1 to the above sum at time slot (4), that is, STW + WAR + DIF1 data bank 1 Waveform 2 is being read from -6. Here, STW is the start address of waveform 2, and register WAR contains ΔSTW as an initial value, that is, a negative number of words included in waveform 1, and ΔWAR is accumulated in time slot (7). . Therefore, STW + WAR value is waveform 1
The value sequentially increases from the start address of each for each value of ΔWAR. Further, the value of ST + WAR + DIF1 is the value obtained by adding DIF1 to this value, and therefore the value increases every ΔWAR from the start address of waveform 2. Here, ΔWAR is a value that represents the skipped reading of the waveform, so waveform 1
And an address for waveform 2 can be generated.

Also, in this pronunciation generator 1-5, there is no PCM part,
In addition, when the solo flag SOL = 0 and the octave shift is not performed, the phase matching is performed. The phase matching method is
In the first time slot (7) when the operation sequence shifts from the initial mode to the normal mode, 9 bits of data having the same name in RAM8-13 as an address are stored in the register WAR as the operation result. The output of RAM8-13 is 9 bits, but the C bus is precharged so all
“1” for 7 bits higher than the 9 bits of 16 bits
Goes in. The calculation result of the time slot (7) of the second transition is stored in the register WAR as shown in Table 6 and the register whose address is the same name in RAM8-13.
Is changed to (Phase register). By doing this, even if a tone with the same name has already been generated on another channel, the register WAR for that channel
Since the value of is given to the register WAR of the channel which is about to generate a musical tone via the RAM8-13, it is possible to match the phase between these two channels.

Here, the calculation WAR + ΔWAR of the time slot (7) will be described.

When WAR + ΔWAR ≧ 0, the calculation result is given to the C bus as −512 ₁₀ (FF00 ₁₆ ) regardless of the range. When there is no on-turbe shift, ΔWAR = 1, so the value of register WAR repeats with a cycle of 512.

As described above, the registers WAR of the plurality of channels that generate the same note are always the same, so that the phases of the waveforms of the same note generated by different channels are completely matched, and phase matching is realized.

Next, the calculation STW + WAR in the time slot (2) will be described in more detail.

Data is read from the register STW of RAM7-3 and MSW2-1
Latch 8-1 of FA2-6 is latched by clock ψ3 via HC bus, SW11, and A bus shown in 1. at the same time
The value of the register WAR of RAM7-1 is latched in the latch 8-2 of FA2-6 by the clock ψ3 via the HA bus, SW2 and B bus. The output of the latch 8-1 is latched by the clock ψ1 without any bit processing in the bit processing circuit 8-10.
Latched to 3. On the other hand, the output of the latch 8-2 is subjected to bit processing as shown in Table 21 with ORG as an input in the bit processing circuit 8-11 and then latched by the clock ψ1.
Latched to 4. Adder 8-9 is latch 8-3, latch 8-
Add the output of 4 and input C through Latch 8-7 and Latch 8-8.
Given to the bus. By performing the above bit processing in the bit processing circuit 8-11, the register WAR becomes
Even though it changes with a period of 2, it changes with a period according to each octave. For example, when ORG = 5 and OCT = 2, there is no octave shift and ΔWAR = 1 as described in the initial processing section. Also, from Table 21, bits 7 and 8 of register WAR are always 1, so the calculation result of time slot (2) is STW '.
When = 0, it becomes −10, −9, ...- 1, −128, −127,… −1, −128, and repeats in 128 cycles. Also, ORG
= 4 and OCT = 5 results in 2 octave shifts and ΔWA
R = 4. In addition, according to Table 21, bits 6, 7, and 8 of register WAR are always 1, so that -40, ... -8, -4, -64, -60, -56 ... -4, -64,
It will be repeated in 16 cycles.

The repetition period of 128 when OCT = 2 and the repetition period of 16 when OCT = 5 indicate that the desired waveform points are obtained from Table 22.

Also, when ORG = 4 and OCT = 5, the register WAR is stepped by 4 means that as shown in Table 18, the data of 64 waveform samples is acquired by 1 point for every 4 samples. It shows that the octave of the data can be increased by two octaves.

When there is PCM The address generation when there is a PCM part is the same as in the case where there is no PCM part, except for the operation in time slot (2).

In time slot (2), STR + WAR is calculated. That is: Data is read from the register STW of the RAM 7-3 and latched in the latch 8-1 of the FA 2-6 by the clock ψ3 via the HC bus, SW11 and A bus. At the same time, RAM7-1 registers
The value of WAR is latched in the latch 8-2 of FA2-6 via HA bus, SW2 and B bus. Here, the output of the latch 8-1 is the bit processing circuit 8-10, and the output of the latch 8-2 is the bit processing circuit.
Input to 8-11, but both outputs are sent to Latch 8-3 and Latch 8-4 without bit processing and adder 8-
It will be added at 9.

Here, considering the value of the register WAR, if there is no PCM part, a negative number of samples included in one cycle of the waveform is written to the register WAR as an initial value, but if there is a PCM part, the register WAR As the initial value of, the negative number of all the sample numbers of the waveform used as the PCM part is written. Therefore, the calculation result of the time slot (2) is a value that is sequentially increased by ΔWAR from the PCM head address of the waveform 1 in the data bank 1-6. The end of the PCM part is detected by detecting that WAR + ΔWAR ≥ 0 in the calculation in the time slot (7), and the address generation after the end of the PCM part is exactly the same as when there is no PCM part. Bit processing by -11 is performed.

It should be noted that the address calculation in the musical tone generating section 1-5 is 16 bits, but it is naturally conceivable that a 16-bit address signal is not sufficient. Therefore, in the musical tone generating section 1-5, the address space can be expanded by using the upper 3 bits of the tablet data TAB. Latch 10-3 in I / 0 2-10 is a latch for address space expansion,
The upper 3 bits of the tablet data TAB are latched in the latch 10-3. That is: When the key is pressed to enter the initial mode, the tablet data stored in the RAM5-4 is stored in the register TAB 'of the RAM7-3 via the MSW2-11. Next, when the normal mode is entered, the value of register TAB ′ in RAM7-3 is read and MSW2-11
Latch 10-3 in I / 0 2-10 via. In this way, although the internal operation is 16 bits, the address space of 19 bits can be accessed.

Waveform reading Waveform reading is performed based on the addresses performed in the time slots (2) and (4). The calculation result of the time slot (2) is latched by the latch 10-1 of the I / O 2-10 via the C bus, SW28, HL bus, SW30, and D bus. First, the output of the latch 10-1 is latched by the latch 10-5 via the shifter selector 10-9, the latch 10-4, and the bit processing circuit 10-10, and the data by the latch 10-3 is stored in the data bank 1-6. Read, data bank 1-6 outputs are latched in latches 10-8. Next, the output of the latch 10-1 is the shifter selector 10-9.
Is shifted to the right by 1 bit, "1" is added to MSB and latched by the latch 10-4. The output of the latch 10-4 is latched by the latch 10-5 via the bit processing circuit 10-10, the data bank 1-6 is read together with the data by the latch 10-3, and the output latch 10-7 of the data bank 1-6 is read. Latched on. At this time, since the output of the latch 10-8 is given to the upper 8 bits of the latch 10-7, it is latched together with the value of the previous data bank 1-6. Where the lower 8 of latch 10-7
The data latched in the bits corresponds to the lower 4 bits and 2 words of the 12-bit wave as described in the section of the data bank. The output of the latch 10-7 is given to the shifter 10-13 via the selector 10-12, the upper 8 bits are shifted to the right by 4 bits, and if the LSB of the output of the latch 10-1 is 0, the lower 8 bits are also 4 bits. Bits are shifted right, and if LSB is 1, the lower 4 bits are not shifted and are output by the shifter 10-13. Here, when W8 = 1 in the control data CONT, that is, when an 8-bit waveform is designated, the shifter 10-13 outputs the lower 4 bits with "0". The output of the shifter 10-13 is given to the D bus via the noise circuit 10-14 and the latch 10-2, and stored in the register WA1 of the RAM 7-3 via the MSW2-11. This value is the waveform data of waveform 1.

Similar processing is performed on the address obtained by the time slot (4). However, control data
If NA = 00 at CONT, a noise signal is added at the noise circuit 10-14. Bit 9 is replaced with a noise signal when AN = 01, bit 10 is replaced with NA = 10, and bits 9 and 10 are replaced with NA = 1. In this way, the noise signal is superimposed without using the adder. This is stored in the register WA2 of the RAM 7-2 as the waveform data of waveform 2.

Envelope multiplication Two types of waveform data of waveform 1 and waveform 2 are obtained as described above, and envelope multiplication is performed on this waveform data. The envelope for waveform 1 is in register ER1 of RAM7-3 and the envelope for waveform 2 is in register ER2 of RAM7-3. Here, when describing the envelope, the envelope has an exponent part, a 4-bit mantissa part 9
13-bit floating point display of bits. The envelope multiplication is performed twice for each channel, but the respective operations are the same, so the calculation of WR1 × ER1 in time slots (7) to (9) will be described.

Data in register ER1 of RAM7-3 is MPLY via MSW2-11
It is latched by the latch 9-3 and the latch 9-5 of 2-7. Here, the lower 10 bits of the register ER1 are latched in the latch 9-3, and the bits 9-12 of the register ER1 are latched in the latch 9-5. Then, the data in the register WR1 of the RAM7-3 is latched in the latch 9-1 of the MPLY2-7 via the MSW2-11. Latch 9-
The MSB of the output of 3 is set to "1" in the bit processing circuit 9-12 and latched in the latch 9-4. That is, the latch hypothesis is latched in the latch 9-4. latch
The output of 9-1 is latched by latch 9-2 via shifter 9-11. At this time, 1 is given to the C input of the encoder 9-10 by the SQ signal and 00001 to the C input of the shifter 9-11.
Is given. Therefore, the shifter 9-11 sends the lower 12 bits of the latch 9-1, that is, the 12 bits of the waveform data of the waveform 1 read from the data bank 1-6 to the latch 9-2. Multiplier 9-16 multiplies the data in Latch 9-2 and Latch 9-4 and outputs the product 14
Bits are latched in Latch 9-7 and sent to Shifter 9-15.

On the other hand, the exponent part of the envelope is latched in the latch 9-5, decoded by the decoder 9-13 via the latch 9-6, and given as a control signal to the shifter 9-15 via the selector 9-14. To be Therefore, the output of latch 9-7 is shifted by the exponent part of the envelope and latched by latch 9-8. In this way, the fixed-point waveform data and the floating-point envelope are multiplied. Latch 9-8
Output is from the L bus via MSW2-11 to RAM7-1 register
Stored in WE1. The multiplication of the waveform data of the waveform 2 and the envelope is performed in the same manner and stored in the register WE2 of the RAM7-4.

Two-wave mixing Waveforms were stored in registers WE1 and WE2 as described above. In this step, the sum of WE1 and WE2 is calculated. The calculation in the time slot (1) corresponds to this.

Two-wave mixing is performed in the CN multiplication time slot (1).
In 1-5, depending on the characteristics of ABM2-9 and filter 1-7, the generated sound pressure level may differ depending on the note name. The correction for this is CN multiplication. Here, the node coefficient CN is used as it is as a coefficient for correction. The calculation result of WE2 + WE1 in time slot (1) is MP from the C bus via SW28, HL bus, SW29, L bus.
Latched to the LY2-7 latch 9-1. Meanwhile memory 2-5
The note coefficient CN is read from the RAM 7-3 in accordance with the note data ND and is latched by the latch 9-3 of the MPLY 2-7 via the HD bus, SW24 and L bus.

Here, WE1 + WE2 is 16-bit data,
Since the A input of 9-16 is 12 bits, MPLY2-7 performs the following processing. That is, the upper 5 bits of the latch 9-1 are input to the encoder 9-10, and the encoder 9-10 outputs the data as shown in Table 9 from both terminals A and B. That is, the number of bits of the data in the latch 9-1 is obtained, and 12 bits are taken out from the latch 9-1 by the shifter 9-11 according to this result. For example, latch 9-
If the value of 1 is 3A26 ₁₆ , this data is actually 15 bits, so shifter 9-11 takes out 12 bits below bit 14 of latch 9-1 and the output of shifter 9-11 is 744 ₁₆ Becomes In this way, the substantial part of WE2 + WE1 is multiplied by the note coefficient, returned to the original number of bits by the shifter 9-15, and latched by the latch 9-9.

As described above, data with a large number of bits is multiplied by using a multiplier with a small number of bits. The value thus obtained is output to the DAC2-8, corrected by the ABM2-9 to a predetermined cycle, and output as a musical tone signal.

By the way, in the musical tone generating section 1-5, as described above, according to the instruction of the microcomputer, by the flag VOL of Table 1,
CN multiplication can be switched to VLD multiplication. That is, in the long sequence, 8 bits of register VLD of RAM5-6 are sent to register LVD 'of RAM7-3 via MSW2-11. Bits are shifted in MSW2-11 when sending, 8-bit data is left-shifted by 2 bits and further lower 2
It is converted to 10-bit data by adding "0" to the bit. This makes the number of VLD bits the same as the number of CN bits. Multiply the value of WE2 + WE1 by the value of ROM7-5, or
Whether to multiply the value of the register VLD ′ is determined by the flag VOL in Table 1. RAM7-3 sends data to the HD bus if VOL = 0 and RAM7-3 sends data to the HD bus if VOL = 1. Send out.

With the above configuration, it becomes possible to change the level of the musical tone signal output from the musical tone generating section 1-5 by the microcomputer 1-4, and the amplitude modulation can be changed by sequentially changing the value of VLD in Table 1. It becomes possible.

VL based on at least one of pressing speed and pressure
When D is created, the touch response function is realized.

The touch response function is to change the volume, tone, etc. according to the speed and strength of keyboard operation. For example, when a piano key is strongly pressed, not only the volume is high but also the tone color is gorgeous. When the key is weakly pressed, not only the volume is low but the tone color is also muffled. Although the volume and timbre change freely according to the strength of keystrokes, in the case of a piano, even if the strength with which the keyboard is pressed after keystrokes is changed, the sound quality that is decaying cannot be changed. In this way, the piano has a touch response function only with the strength of keystrokes, and such a function is particularly called initial touch control. Percussion instruments generally belong to this category.

On the other hand, the trumpet can change the connected sound quality depending on the strength of your breath, so even when you imitate this sound and play it with the keyboard of an electronic musical instrument, you can play the trumpet sound while the trumpet sound is generated. It is necessary to change the volume and timbre by increasing or decreasing the strength. Such a function is particularly called aftertouch control. Generally, string instruments and wind instruments belong to this category.

In the embodiment of the present invention, as described above, the volume can be controlled independently for each channel by performing VLD multiplication with the VOL flag.

As an application example, the strength of keystrokes is measured and VL is calculated according to the strength.
By creating the value of D and transferring it from the microcomputer, the volume of each sound changes according to the different VLD transferred for each keystroke.

When transferring the microcomputer VLD by switching the tablet data according to the value of VLD, the tone generation unit of this embodiment can change the tone and the tone color according to the value of VLD. It is clear in the functional description.

This tone color switching will be described by taking an example in which VLD is 8 bits.

Table 23 shows an example of the VLD value range and the corresponding strong and weak names and tablet names.

Every time VLD is reduced by 1 bit, the volume is 1/2 or 6 dB
It becomes smaller and is assigned to each of the strong and weak names of musical terms. Also, since ff strength requires a gorgeous tone color, waveform data rich in harmonics is assigned to tablet 0, and a timbre tone is required at a volume lower than mp, so waveform data close to a sine wave should be assigned to tablet 3. , Prepare multiple types of waveform data in the data bank.

In this way, four tones can be switched within the VLD numerical range depending on the strength of keystrokes, and at the same time 256 tones can be specified according to the 8-bit VLD.

The above is the initial touch control, but similarly, VLD that changes momentarily according to the magnitude of key pressing pressure after keystroke.
And the tablet data that changes momentarily according to the value of VLD is sent out by the microcomputer, the musical tone generation unit of this embodiment changes the tone color and the volume momentarily according to the change of the key pressing pressure after the keystroke. be able to.

The above is the aftertouch control.

(4) Envelope generating method The envelope generating method in the musical tone generating section 1-5 is divided into the following three steps. That is, reading of address-generated envelope data and envelope calculation will be described in detail below.

Address generation By initial setting by keystroke, register E based on header data STE (start address of envelope data E1 ′) and ΔSTE (word number of envelope data E1 ′)
AR1, EAR2, TR1, TR2, ΔT1, and ΔT2 are initialized. An address calculation is performed based on these data. The calculation of the address is performed in the long sequence of the calculation sequence because the calculation frequency may be low. In addition, the envelope data can be
E1 ′ address calculation is performed evenly for envelope data
E2 'address calculation is performed.

Time slot in odd-numbered long sequence
In (13) ΔT1 + TR1 → TR1 …… (4-1) Time throat (15) ΔEAR1 ＋ EAR1 + Ci → EAR1 …… (4-2) is calculated and the value of EAR1 is used to calculate data bank 1-6. Read out. Ci of the time slot (15) corresponds to the overflow caused by the accumulation of ΔT1 performed in the time slot (13). Here, the calculation (4-1) will be described in detail.

First, the value of register ΔT1 of RAM7-2 is HB bus, MSW2-11
Latch 8-1 of FA2-6 via. at the same time,
The value of register TR1 of RAM7-3 is via HC bus, MSW2-11
It is latched by the latch 8-2 of FA2-6. Bit 3 of the output of the latch 8-1 is forced to "0" by the bit processing circuit 8-10.
(The reason for setting bit 3 to "0" will be described later), and it is latched by the latch 8-3. The output of the latch 8-2 is latched by the latch 8-4 via the bit processing circuit 8-11. Here, the bit processing circuit 8-11 does not perform processing such as bit conversion. The outputs of the latch 8-3 and the latch 8-4 are added by the adder 8-9, and the result is given to the C bus via the latch 8-7 and the latch 8-8. Store the addition result in TR1. If an overflow occurs in the addition result, "1" is output from Co of the adder 8-9. This output is latched by latch 8-6 and used for the calculation of time slot 15. However, this is for the case where the waveform data does not have a PCM part, and when the waveform data has a PCM part (flag PCM = 1), the register TR1 is forcibly set to "0" until the PCM part is read. "Is entered. Therefore, since overflow due to accumulation of ΔT1 does not occur, EAR1 until PCM is read.
The value of is never updated. ΔT1 is the value of D output at C = 0 in Table 13 as described in the section of initial processing, and register TR1 is a 16-bit register, so if ΔT1 = 4000 ₁₆ , for example, calculate (4-1 ) Is performed 4 times, the register TR1 overflows and the operation (4-2)
Ci = 1 and the address is updated. Where the operation
(4-1) and (4-2) are performed once every two long sequences. As shown in FIG. 1 (c), the long sequence of the same channel appears in the period of 388 time slots, that is, in the time period of 97 μs because one time slot is 250 ns.
Therefore, calculations (4-1) and (4-2) are performed every 194 μs, and ΔT1 =
In the case of 4000 ₁₆ , the address will be updated in 776 μs.

By the way, since the envelope data consists of 2 bytes, it must be updated by 2 when updating the address. In the time slot (15), the address is updated as follows.

First, ΔEAR1 is a value determined by ΔT1, and ΔT1 ≠ 00
When 08 ₁₆ is ΔEAR1 = 0000 ₁₆ , and when ΔT1 = 0008 ₁₆ is ΔEAR1 = FFEB ₁₆ = −21 ₁₀ . This operation is MSW2-1
It is performed by SW31 in 1. SW31 has the structure shown in Fig. 11 (i) and has a flag TO that indicates the value of bit 3 of ΔT1.
Are controlled by. And now if the ΔT1 ≠ 0008 _16,
The value of EAR ₁₆ is given to the A bus by SW31, the HA bus from the register EAR1 of RAM7-1, and the EAR1 value to the B bus via SW2 of MSW2-11. These values are FA2-6 Latch 8-1, Latch
Latched to 8-2. The output of the latch 8-1 is sent to the latch 8-3 via the bit processing circuit 8-10. Here, in the bit processing circuit 8-10, data conversion is not performed. At the same time, the output of the latch 8-2 is the bit processing circuit 8-
It is given to 11 and the LSB of the data is forced to "1" and sent to the latch 8-4. That is, 1 is added in advance in the bit processing circuit 8-11. In addition, the overflow due to the operation (4-1) stored in the latch 8-6 described above will not occur in the latch 8--
Latched to 5. Therefore, when the values of Latch 8-3, Latch 8-4 and Latch 8-5 are added, the value of Latch 8-5 becomes "1".
In that case, "2" will be added to the value of EAR1. On the other hand, when the value of latch 8-5 is "0", the value of EAR1 remains incremented by 1. Since "0" and "1" are given, no inconvenience occurs.

By the way, when ΔT1 = 0008 ₁₆ , ΔEAR1 becomes FFEB ₁₆ (−
21 ₁₀ ). Therefore, 21 _{10 is} subtracted from the value of EAR1, and the envelope data 10 words before is read. As a result, the address of the envelope data is looped, and a repeating envelope like a mandrel can be generated. It was mentioned earlier that bit 3 is set to "0" in the bit processing circuit 8-10 in the operation (4-1). The reason is that bit 3 sets ΔEAR1 = FFEB ₁₆ and this operation is performed. This is to prevent adding 0008 ₁₆ to the register TR1.

ΔT2, TR2, ΔEA in the even sequence of long sequence
R2 and EAR2 are calculated in the same way.

It is needless to say that completely different envelope signals can be generated for the waveform 1 and the waveform 2 because the calculations regarding EAR1 and EAR2 are performed independently. Further, since it is easy to make the repetition cycle different for the repetition of EAR1 or EAR2, various effects can be obtained.

Reading Envelope Data Envelope data is read in a long sequence, and the envelope data of waveform 1 is read at an even number of times.
The envelope data of the waveform 2 at the odd number is read.

How to read the envelope data based on the values of the registers EAR1 and EAR2 is exactly the same as that described in the section of the initial processing.
The data read from 6 is stored in registers ΔT1, ΔT2, ΔZ1, ΔZ2, ΔE1, and ΔE2 while performing format conversion.

Envelope calculation By reading the envelope data, ΔZ1, ΔZ2, Δ
Data is stored in E1 and ΔE2, and initial values are given to ER1, ER2, ZR1, and ZR2 by initial processing. The envelope is calculated according to these values.

The basis of envelope calculation is the time slot of the adder
(3), (5), (6), and (8). Time slot (3),
The envelope of waveform 1 is calculated by (5), and the envelope of waveform 2 is calculated by time slots (6) and (8). Here, Ci of the time slots (5) and (8) is an overflow caused by the calculation by the time slots (3) and (6). Which overflow is caused by the time slots (3) and (6)? How to add in time slots (5) and (8)
The same as described in (13) and (15). The ER1 and ER2 values obtained in this way are the envelope data.

By the way, envelope calculation differs depending on various modes. The various modes are: 1) When the waveform has PCM and when it does not. (PCM = 1 /
0) 2) For piano type envelope and organ type envelope. (P / 0 = 1/0) 3) When the damper flag is turned on and when it is turned off. (DMP
= 1/0). The individual cases will be described below.

PCM = 0 and P / 0 = 0 The initial setting is "0" for ER1, ER2, ZR1, and ZR2.
Registers ΔE1, ΔE2, ΔZ1, and Δ when the key is pressed
The envelope is calculated according to the value of Z2. When the key is released, the time slot (3), (5), (6), (8) ΔZ1,
As the values of ΔE1, ΔZ2, and ΔE2, the signal processor of UCIF2-3 5-
Release data is generated from 6 and registers ΔZ1 and ΔE
It is used instead of the values of 1, ΔZD, and ΔE2.

In this mode, the damper flag DMP has no effect on the operation.

PCM = 0 and P / 0 = 1 The initial setting is “0” for ER1, ER2, ZR1 and ZR2.
Registers ΔE1, ΔE2, ΔZ1, and Δ when the key is pressed
The envelope is calculated according to the value of Z2. When the key is released, if the damper flag DMP = 1, the envelope calculation is continued according to the values of the registers ΔE1, ΔE2, ΔZ1, and ΔZ2. When the damper flag DMP0, PCM = 0 and P / 0.
The same as when = 0.

PCM = 1 and P / 0 = 0 The initial settings are EA1 = 1FFF ₁₆ , ER2 = 0, ZR1 = 0, ZR2
= 0. When the key is pressed and waveform 1 is reading the PCM part, the initial value is held, and when the PCM part is read, the envelope is calculated according to the values of registers ΔE1, ΔE2, ΔZ1, and ΔZ2. When the key is released, waveform 1 is on the PC
Calculation is performed based on the release data from the signal processor 5-6 of UCIF2-3 regardless of whether the M part is read. That is, it results when PCM = 0 and P / 0 = 0.

In this mode, the damper flag DMP has no effect on the operation.

PCM = 1 and P / 0 = 1 The initial setting is ER1 = 1FFF ₁₆ , ER2 = 0, ZR1 = 0, ZR2
= 0. When the amper flag DMP =, once the key is pressed, the calculation is performed regardless of the key release timing. That is, when the waveform 1 is reading the PCM part, the initial values of the registers ER1, ER2, ZR1 and ZR2 are held, and the PCM
After reading, the calculation is started according to the values of the registers ΔE1, ΔE2, ΔZ1, and ΔZ2. When the damper flag DMP = 1, it is exactly the same as when PCM = 1 and P / 0 = 0.

As described above, the envelope signal can be freely generated according to various modes. Also, ΔE1, ΔZ1
, ΔE2, and ΔZ2 can be set independently, and the data are updated at the time determined by ΔT1 and ΔT2, as is clear in the section of address generation. Can occur.

(Effect of the Invention) As described above, according to the present invention, the number of bits of one word of waveform data is N, the number of bits of one word of the data bank is M, and the relationship between M and N is , The total number of words in the data bank is W, the upper M bits of the data of the i-th word of the waveform data and the lower (N-
If the addresses whose M) bits are stored in the data bank are Ai and Bi, respectively. However, [] is a Gaussian symbol and represents the integer part of the numerical value in [].

By having a data bank in which the relationship of
Since the ROM usage efficiency is improved, more timbre can be generated with less memory area.

[Brief description of drawings]

FIG. 1 (a) is a block diagram of an embodiment of an information processing apparatus according to the present invention, FIG. 1 (b) is a timing diagram of data transfer by a microcomputer, and FIG. 1 (c) is used in the present invention. FIG. 2 is a diagram showing a calculation time slot, FIG. 2 is a block diagram of a musical tone generating section 1-5 according to the present invention, and FIG.
Fig. 5 shows the principle of note clock generation, Fig. 4 is a detailed diagram of SEQ2-2 in the tone generator 1-5, and Fig. 5 is UC.
Detailed drawing of IF2-3, Fig. 6 is also detailed drawing of CDR2-4, 7
The same figure shows the details of memory 2-5, and the same figure shows FA2-6.
Fig. 9 (a) is a detailed view of MPLY2-7.
Figure (b) is a detailed view of the multiplier 9-16 used in MPLY2-7, Figure 10 is a detailed view of I / 0 2-10 in the tone generator 1-5, and Figure 11 (b). Is also a detailed view of MSW2-11, Fig. 11 (b)
~ Fig. 11 (i) is the pattern diagram of the switch used in MSW2-11, Fig. 11 (nu) is the timing diagram of data transfer in MSW2-11, and Fig. 12 is the data format in data bank 1-6. Fig. 13 is a diagram showing the data format of envelope data in the data banks 1-6, Fig. 14 is a block diagram of a conventional electronic musical instrument, and Fig. 15
The figure is a block diagram of the tone synthesis data ROM. 1-1: Keyboard, 1-2: Tablet, 1-3: Effect switch, 1-4: Microcomputer, 1-5: Musical tone generator, 1-6 ...
… Data bank, 1-7 …… Filter, 2-1 …… Master clock, 2-2 …… Sequencer (SEQ), 2-3 …… Microcomputer interface (UCIF), 2-4 …… Comparison register ( C
DR), 2-5 ...... Memory, 2-6 ...... Full adder (FA), 2-
7 …… Multiplying part (MPLY), 2-8 …… Digital-analog converter (DAC), 2-9 …… Analog buffer memory part (AB
M), 2-10 ... Input / output circuit section (I / O), 2-11 ... Matrix switch section (MSW).

Claims (2)

[Claims] 1. An electronic musical instrument in which the waveform data is sequentially read from a data bank storing waveform data consisting of a plurality of words, and a predetermined process is performed to produce the waveform data. The number of bits in one word of a data bank is M, and the relationship between M and N is , The total number of words in the data bank is W, the upper M bits of the data of the i-th word of the waveform data, the lower M bits (N−M)
If the addresses whose bits are stored in the above data bank are Ai and Bi respectively However, [] is a Gaussian symbol and represents the integer part of the numerical value in []. An electronic musical instrument characterized in that the relationship is established. 2. The address Bi is the same as the address Ai. At least 1 including the highest bit shifted right by one bit
An electronic musical instrument having means for creating by adding 1 to a bit.