JPH065677A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a wafer on which individual semiconductor devices can be screened. CONSTITUTION:A semiconductor wafer 10 has a passive device region 12 that includes a resistor 17, a capacitor 19, a fuse 18, and a power supply-only pad 13. The individual semiconductor chips 11 on the semiconductor wafer 10 are electrically connected to the resistor 17, the capacitor 19, and the fuse 18. By this setup, semiconductor chips can be subjected to a burn-in test at a wafer stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device which enables burn-in screening at a semiconductor wafer level.

[0002]

2. Description of the Related Art A wafer manufactured and completed through a series of manufacturing processes such as oxidation and metallization becomes a final product through an assembly process which is the next stage.

Conventionally, a burn-in test, which is conventionally carried out as a screening, is performed at this stage for the first time. this is,
This is because at the wafer stage or the chip stage, there was no electrical contact technology for the product under test that could be used for mass production.

[0004]

When burn-in is carried out, a poorly-finished product becomes an initial defect and is screened. However, depending on the product, the package price is extremely high. It was a waste of money for generations and was directly linked to high costs, which was a problem.

Further, recently, the demand for chip supply has been generalized by the user side, but since an appropriate screening method has not been established at the wafer level in the related art,
As a manufacturer, quality assurance was impossible, which was a major obstacle to the development of the chip business.

The present invention has been made in view of the above conventional circumstances, and therefore an object of the present invention is to provide a novel semiconductor device capable of solving the above problems inherent in the conventional art. It is in.

[0007]

In order to achieve the above object, the semiconductor device according to the present invention has a passive device such as a resistor, a capacitor and a fuse so that a burn-in test can be carried out in a semiconductor wafer at the wafer stage. It has a region provided with a device and is provided with a wiring and a pad dedicated to power supply for electrically connecting to the passive device.

In the semiconductor device according to the present invention, a fuse and a resistor are connected in series between a power supply terminal in a semiconductor chip in a wafer and a power supply dedicated pad, and a capacitor is connected in series between the power supply dedicated pads. It is characterized by

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings with reference to the accompanying drawings.

FIG. 1 is a front view showing an embodiment of a semiconductor wafer according to the present invention.

Referring to FIG. 1, in a semiconductor wafer 10, individual semiconductor chips 11 and passive device areas 1 are provided.
2 and a pad 13 dedicated to power supply are provided. Reference numerals 14, 15 and 16 denote a power (Vcc) pad 14, an input pad 15, and a power (GND) pad 16 in the semiconductor chip 11, respectively.

FIG. 2 is a front view showing a state in which the resistor 17, the fuse 18, and the capacitor 19 are provided in the passive device area 12 and are electrically connected to the power supply dedicated pad 13. The fuse 18 has a capacity that blows when a current more than twice the maximum power supply current design value of the semiconductor chip flows. Further, in the figure, the resistor 17, the fuse 18,
All the capacitors 19 are also shown by electric symbols.

To carry out burn-in at the wafer stage,
Power is supplied to the wafer by mechanically contacting an external probe with a pad on the wafer. During the burn-in, the semiconductor wafer 10 thermally expands due to self-heating of the semiconductor chip 11 in the wafer and external heating.

Conventionally, since the pad of the chip that is burned in is small, this thermal expansion causes the plug used for bias application to shift, resulting in contact failure. Therefore, mass production application of burn-in at the wafer level is not possible. It was possible.

According to the present invention, as shown in FIG. 1, since a large power supply dedicated pad 13 having a chip area or more is provided,
Such a problem in the burn-in implementation does not occur.

Further, at the wafer stage, the semiconductor chip 11 in the semiconductor wafer 10 probably contains defects. If a short circuit between power supplies is included among these problems, the conventional method causes overload of an external power supply and burnout of the semiconductor chip 1. However, in the case of the present invention, Since the fuse 18 is inserted in the wiring connected in series to the power supply (Vcc) pad 14 of the chip 11, even if a short circuit occurs between the power supplies in the chip, the fuse 18 operates and the current to the corresponding chip is increased. Supply will be cut off, so there will be no problems in implementing burn-in.

Further, the input pad 1 of the semiconductor chip 11
5, the power is supplied via a resistor, and the capacitor 19 is inserted between the power (Vcc) pad 14 and the power (GND) pad 16 of the semiconductor chip 11.
Since these act as a protective element for the semiconductor chip 1 during burn-in, it is possible to prevent destruction of the individual semiconductor chips 11 due to burn-in.

The fuse 18, the capacitor 19, the resistor 17 and the power supply dedicated pad 13 can be formed at the same time as the semiconductor chip 11 is manufactured. Regarding the wiring from the individual semiconductor chips 11 to the passive device area 12, , Wiring cutting with a laser before the functional test at the wafer level, or after the PR process after burn-in,
The wiring may be removed and the individual chips may be electrically separated.
These techniques are techniques that are generalized as the current LSI manufacturing process, and do not hinder the implementation of the present invention.

[0019]

As described above, according to the present invention,
Since the semiconductor device has a passive device region and wiring for electrically connecting to the passive device and a dedicated power supply pad, and a resistor, a capacitor, and a fuse are connected in series between the dedicated power supply pad and the semiconductor chip, Burn-in becomes possible at the wafer stage.

[Brief description of drawings]

FIG. 1 is a surface view showing an embodiment of the present invention.

2 is a plan view showing a semiconductor wafer shown in FIG.
It is a front view of the semiconductor wafer which shows the state which wired.

[Explanation of symbols]

 10 ... Semiconductor wafer 11 ... Semiconductor chip 12 ... Passive device area 13 ... Power supply dedicated pad 14 ... Power supply (Vcc) pad 15 ... Input pad 16 ... Power supply (GND) pad 17 ... Resistor 18 ... Fuse 19 ... Capacitor

Claims (4)

[Claims] 1. A semiconductor wafer having a semiconductor chip composed of a resistor, a capacitor, a transistor and a wiring layer formed through processes such as oxidation, diffusion and metallization, and having a region separated from the semiconductor chip region, A semiconductor device comprising a passive device such as a resistor, a capacitor, and a fuse in this region, and a wiring electrically connected to the passive device and a pad dedicated to power supply. 2. A fuse is further connected in series between the power supply terminal in the semiconductor chip and the dedicated pad for power supply, which fuses when a current more than twice the design value of the maximum power supply current of the semiconductor chip flows. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 3. The semiconductor device according to claim 1, wherein a resistor is connected in series between an input / output terminal in the semiconductor chip and the power supply dedicated pad. 4. The semiconductor device according to claim 1, further comprising a capacitor connected in series between the pads dedicated to power supply.