JPH065747A - Mounting structure for semiconductor device - Google Patents

Mounting structure for semiconductor device

Info

Publication number
JPH065747A
JPH065747A JP4184451A JP18445192A JPH065747A JP H065747 A JPH065747 A JP H065747A JP 4184451 A JP4184451 A JP 4184451A JP 18445192 A JP18445192 A JP 18445192A JP H065747 A JPH065747 A JP H065747A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
resin material
conductor pattern
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4184451A
Other languages
Japanese (ja)
Inventor
Yuichi Takagi
祐一 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4184451A priority Critical patent/JPH065747A/en
Publication of JPH065747A publication Critical patent/JPH065747A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】 【目的】 きわめて安価に半導体装置の発熱を抑えるこ
とができる半導体装置の実装構造を提供する。 【構成】 複数の導体パターン2が積層された回路基板
1と、それら各導体パターン2に接続して回路基板1に
穿設されたスルーホール4と、このスルーホール4と対
向する状態で回路基板1の導体パターン2上に実装され
た半導体装置5とからなるもので、半導体装置5の下面
5aと回路基板1の導体パターン2とに接触する状態で
高熱伝導性の樹脂材7を装填した。
(57) [Summary] [Object] To provide a mounting structure of a semiconductor device capable of suppressing heat generation of the semiconductor device at an extremely low cost. A circuit board 1 in which a plurality of conductor patterns 2 are laminated, a through hole 4 connected to each of the conductor patterns 2 and formed in the circuit board 1, and a circuit board in a state of facing the through hole 4 The semiconductor device 5 is mounted on the conductor pattern 2 of No. 1 and the resin material 7 having a high thermal conductivity is loaded in a state of being in contact with the lower surface 5a of the semiconductor device 5 and the conductor pattern 2 of the circuit board 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の実装構造
に係わり、特に、回路基板上に実装された半導体装置の
発熱を抑えた構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure, and more particularly to a structure for suppressing heat generation of a semiconductor device mounted on a circuit board.

【0002】[0002]

【従来の技術】図2は従来構造を示す側面概略図であ
る。図示した半導体装置の実装構造において、50は半
導体装置であり、この半導体装置50の側部には外部リ
ード51が植設されている。一方、図中52は回路基板
であり、この回路基板52の表面には導体パターン53
が形成されている。そして、回路基板52に対して半導
体装置50は、外部リード51を介して導体パターン5
3上に実装されている。
2. Description of the Related Art FIG. 2 is a schematic side view showing a conventional structure. In the mounting structure of the semiconductor device shown in the figure, 50 is a semiconductor device, and an external lead 51 is implanted on the side portion of the semiconductor device 50. On the other hand, reference numeral 52 in the drawing denotes a circuit board, and a conductor pattern 53 is provided on the surface of the circuit board 52.
Are formed. Then, with respect to the circuit board 52, the semiconductor device 50 has the conductor pattern 5 via the external lead 51.
It is implemented on 3.

【0003】ところで、種々の半導体装置の回路でも、
特にC(Complementary)MOSタイプの
場合は消費電力が少ないことから発熱量も小さく、よっ
てパッケージの素材としては樹脂製のもので十分である
とされていた。
By the way, even in the circuits of various semiconductor devices,
In particular, in the case of the C (Complementary) MOS type, the amount of heat generated is small because the power consumption is small, and therefore, it has been said that a resin material is sufficient as the material of the package.

【0004】[0004]

【発明が解決しようとする課題】しかしながら最近で
は、パッケージ内に納められるチップのゲート数が膨大
なものとなり、それに伴う消費電力の増加によって発熱
量も増大し、樹脂パッケージの熱容量だけでは半導体装
置50の温度上昇を抑えることが困難になってきた。す
なわち、上記従来の実装構造において、半導体装置50
が樹脂パッケージで構成されている場合は、パッケージ
の熱容量で吸収できない熱が半導体装置50の内部に蓄
熱され、これが半導体装置50の温度を上げる要因とな
っていた。
However, in recent years, the number of gates of chips contained in a package has become enormous, and the amount of heat generated also increases due to the increase in power consumption, and the semiconductor device 50 is obtained only by the heat capacity of the resin package. It has become difficult to control the temperature rise in the. That is, in the above conventional mounting structure, the semiconductor device 50
In the case where is made up of a resin package, heat that cannot be absorbed by the heat capacity of the package is stored inside the semiconductor device 50, which causes the temperature of the semiconductor device 50 to rise.

【0005】そこで上記問題の対応策としては、例えば
半導体装置50にセラミックパッケージを用いたり、或
いは半導体装置50にヒートシンクを接続させたりし
て、半導体装置50の放熱性を高める方法が考えられ
る。しかし、前者の場合は半導体装置の価格を大幅に上
昇させてしまうことになり、後者の場合は回路基板全体
が大型化するうえに、部品点数の増加や製造工程の煩雑
化に伴って大幅な価格上昇を招いてしまう。
Therefore, as a countermeasure against the above-mentioned problem, for example, a method of using a ceramic package for the semiconductor device 50 or connecting a heat sink to the semiconductor device 50 to improve the heat dissipation of the semiconductor device 50 can be considered. However, in the case of the former, the price of the semiconductor device will be greatly increased, and in the case of the latter, the entire circuit board becomes large, and the number of parts increases and the manufacturing process becomes complicated. This will lead to price increases.

【0006】本発明は、上記問題を解決するためになさ
れたもので、きわめて安価に半導体装置の発熱を抑える
ことができる半導体装置の実装構造を提供することを目
的とする。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a mounting structure of a semiconductor device which can suppress heat generation of the semiconductor device at a very low cost.

【0007】[0007]

【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、複数の導体パターンが積
層された回路基板と、それら各導体パターンに接続して
回路基板に穿設されたスルーホールと、このスルーホー
ルと対向する状態で回路基板の導体パターン上に実装さ
れた半導体装置とからなるものであって、半導体装置の
下面と回路基板の導体パターンとに接触する状態で高熱
伝導性の樹脂材を装填した半導体装置の実装構造であ
る。
SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and a circuit board having a plurality of conductor patterns laminated thereon and a circuit board connected to each of the conductor patterns and drilled in the circuit board. And a semiconductor device mounted on the conductor pattern of the circuit board in a state of facing the through hole, in a state of being in contact with the lower surface of the semiconductor device and the conductor pattern of the circuit board. It is a mounting structure of a semiconductor device loaded with a resin material having high thermal conductivity.

【0008】[0008]

【作用】本発明の実装構造においては、半導体装置の下
面と回路基板の導体パターンとに接触する状態で高熱伝
導性の樹脂材が装填されることで、半導体装置と回路基
板とが樹脂材を介して熱的に接続され、これにより、半
導体装置の発熱に対する全体の熱容量が従来よりも大き
く確保される。
In the mounting structure of the present invention, the resin material having a high thermal conductivity is loaded in a state of contacting the lower surface of the semiconductor device and the conductor pattern of the circuit board, so that the semiconductor device and the circuit board are made of the resin material. The semiconductor device is thermally connected to the semiconductor device through the connection, so that the total heat capacity for heat generation of the semiconductor device is secured to be larger than the conventional one.

【0009】[0009]

【実施例】以下、本発明に係わる実施例を図面に基づい
て説明する。図1は、本発明の一実施例を示す側面概略
図である。図示した半導体装置の実装構造において、1
は回路基板であり、この回路基板1には複数(図例では
4枚)の導体パターン2が積層されている。この回路基
板1は、例えばガラスエポキシ基材3と導体パターン2
とを順次積層して、一体化したものである。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic side view showing an embodiment of the present invention. In the mounting structure of the illustrated semiconductor device, 1
Is a circuit board, and a plurality of (four in the illustrated example) conductor patterns 2 are laminated on the circuit board 1. The circuit board 1 includes, for example, a glass epoxy base material 3 and a conductor pattern 2.
And are sequentially laminated and integrated.

【0010】また、回路基板1の所定位置には、各導体
パターン2に接続してスルーホール4が穿設されてい
る。ここで、回路基板1に積層された各導体パターン2
は、厚さ0.1mm程度の薄い銅箔で形成されている。
これに対してスルーホール4の孔壁には銅メッキが施さ
れており、これによって各導体パターン2とスルーホー
ル4とが電気的且つ熱的に接続されている。
Through holes 4 are formed at predetermined positions on the circuit board 1 so as to be connected to the conductor patterns 2. Here, each conductor pattern 2 laminated on the circuit board 1
Is formed of a thin copper foil having a thickness of about 0.1 mm.
On the other hand, the hole walls of the through holes 4 are plated with copper, so that the conductor patterns 2 and the through holes 4 are electrically and thermally connected to each other.

【0011】上記構成の回路基板1に対して、半導体装
置5は、その側部に植設された外部リード6を介して回
路基板1の導体パターン2上に実装され、且つスルーホ
ール4と対向する状態に配置される。
With respect to the circuit board 1 having the above-described structure, the semiconductor device 5 is mounted on the conductor pattern 2 of the circuit board 1 through the external leads 6 implanted on the side thereof, and faces the through hole 4. It is placed in a state to do.

【0012】このような実装状態の下で本実施例の実装
構造においては、半導体装置5の下面5aと回路基板1
の導体パターン2とに接触する状態で高熱伝導性の樹脂
材7が装填されている。ここで、高熱伝導性の樹脂材7
としては、例えばエポキシ系の熱伝導性樹脂に二酸化珪
素を加えたものや、或いは熱伝導率の大きな金属粉末
(例えばAg粉末)やセラミック粉末を添加したものな
どが考えられる。
Under such a mounting state, in the mounting structure of this embodiment, the lower surface 5a of the semiconductor device 5 and the circuit board 1 are
The resin material 7 having high thermal conductivity is loaded so as to be in contact with the conductor pattern 2. Here, the resin material 7 having high thermal conductivity
For example, an epoxy-based thermally conductive resin to which silicon dioxide is added, or a metal powder (for example, Ag powder) or a ceramic powder having a high thermal conductivity is added.

【0013】また、樹脂材7の装填方法としては、回路
基板1に半導体装置5を実装した後に、スルーホール4
を通して樹脂材7を注入する方法や、半導体装置5の外
部リード6の隙間から樹脂材7を注入する方法が考えら
れる。しかし、発熱源となるチップが半導体装置5の中
央に配置されることや、樹脂材7を注入する際の作業性
等を考慮すると、後者の方が好適である。
As a method of loading the resin material 7, after mounting the semiconductor device 5 on the circuit board 1, the through hole 4 is formed.
A method of injecting the resin material 7 through the through-hole or a method of injecting the resin material 7 through the gap between the external leads 6 of the semiconductor device 5 can be considered. However, the latter is more preferable in consideration of the fact that the chip that is a heat source is arranged in the center of the semiconductor device 5 and the workability when the resin material 7 is injected.

【0014】上記構成からなる本実施例の実装構造にお
いては、半導体装置5の下面5aと回路基板1の導体パ
ターン2とに接触する状態で高熱伝導性の樹脂材7が装
填されることで、半導体装置5と回路基板1とが樹脂材
7を介して熱的に接続される。すなわち、半導体装置5
のパッケージ内に発生した熱は、樹脂材7、スルーホー
ル4、さらには導体パターン2を通して回路基板1全体
に伝熱される。これにより、半導体装置5の発熱に対す
る全体の熱容量としては、半導体装置5自体の持つ熱容
量に回路基板1全体の熱容量を加えたものとなるため、
従来構造に比較して格段に大きく確保されるようにな
り、この構造をもって半導体装置5の発熱が抑えられ
る。
In the mounting structure of this embodiment having the above structure, the resin material 7 having high thermal conductivity is loaded in a state of contacting the lower surface 5a of the semiconductor device 5 and the conductor pattern 2 of the circuit board 1, The semiconductor device 5 and the circuit board 1 are thermally connected via the resin material 7. That is, the semiconductor device 5
The heat generated in the package is transferred to the entire circuit board 1 through the resin material 7, the through holes 4, and the conductor pattern 2. As a result, the total heat capacity of the semiconductor device 5 for heat generation is the sum of the heat capacity of the semiconductor device 5 itself and the heat capacity of the entire circuit board 1,
The structure is remarkably large compared with the conventional structure, and the heat generation of the semiconductor device 5 is suppressed by this structure.

【0015】なお、図1に示す実装構造においては、高
熱伝導性の樹脂材7がスルーホール4にまで充填されて
いるが、本発明はこれに限らず、樹脂材7の注入量とし
ては半導体装置5の下面5aと回路基板1の導体パター
ン2との間に充填される程度で十分である。なぜなら、
各導体パターン2とスルーホール4とは、あらかじめ熱
伝導率のきわめて大きな導体(本例では銅)によって熱
的に接続されているからである。
In the mounting structure shown in FIG. 1, the resin material 7 having a high thermal conductivity is filled up to the through hole 4, but the present invention is not limited to this, and the injection amount of the resin material 7 is a semiconductor. It is sufficient to fill the space between the lower surface 5a of the device 5 and the conductor pattern 2 of the circuit board 1. Because
This is because each conductor pattern 2 and the through hole 4 are thermally connected in advance by a conductor (copper in this example) having an extremely high thermal conductivity.

【0016】[0016]

【発明の効果】以上、説明したように本発明によれば、
通常の回路基板の製造工程で形成されるスルーホールを
利用して、半導体装置の下面と回路基板の導体パターン
とに接触させた高熱伝導性の樹脂材で、半導体装置と回
路基板とを熱的に接続させることにより、半導体装置の
発熱に対する全体の熱容量が従来構造に比べて格段に大
きく確保される。これにより、大幅な価格上昇を犠牲に
して、半導体装置にセラミックパッケージを採用した
り、ヒートシンクを接続させたりすることなく、簡単な
構造上の改良によって、きわめて安価に半導体装置の温
度上昇を抑えることが可能となる。
As described above, according to the present invention,
Using a through hole formed in a normal circuit board manufacturing process, the semiconductor device and the circuit board are thermally insulated with a highly heat-conductive resin material that is in contact with the lower surface of the semiconductor device and the conductor pattern of the circuit board. By connecting to the semiconductor device, the overall heat capacity for heat generation of the semiconductor device can be ensured to be much larger than that of the conventional structure. As a result, the temperature rise of the semiconductor device can be suppressed at an extremely low cost by adopting a simple structural improvement without adopting a ceramic package for the semiconductor device or connecting a heat sink at the cost of a large price increase. Is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す側面概略図である。FIG. 1 is a schematic side view showing an embodiment of the present invention.

【図2】従来構造を示す側面概略図である。FIG. 2 is a schematic side view showing a conventional structure.

【符号の説明】[Explanation of symbols]

1 回路基板 2 導体パターン 4 スルーホール 5 半導体装置 5a 下面 7 樹脂材 1 circuit board 2 conductor pattern 4 through hole 5 semiconductor device 5a lower surface 7 resin material

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数の導体パターンが積層された回路基
板と、前記各導体パターンに接続して前記回路基板に穿
設されたスルーホールと、前記スルーホールと対向する
状態で前記回路基板の導体パターン上に実装された半導
体装置とからなるものであって、 前記半導体装置の下面と前記回路基板の導体パターンと
に接触する状態で高熱伝導性の樹脂材を装填したことを
特徴とする半導体装置の実装構造。
1. A circuit board on which a plurality of conductor patterns are laminated, through holes formed in the circuit board by connecting to the conductor patterns, and conductors of the circuit board facing the through holes. A semiconductor device mounted on a pattern, wherein a resin material having high thermal conductivity is loaded in a state of being in contact with a lower surface of the semiconductor device and a conductor pattern of the circuit board. Implementation structure of.
JP4184451A 1992-06-17 1992-06-17 Mounting structure for semiconductor device Pending JPH065747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4184451A JPH065747A (en) 1992-06-17 1992-06-17 Mounting structure for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4184451A JPH065747A (en) 1992-06-17 1992-06-17 Mounting structure for semiconductor device

Publications (1)

Publication Number Publication Date
JPH065747A true JPH065747A (en) 1994-01-14

Family

ID=16153383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4184451A Pending JPH065747A (en) 1992-06-17 1992-06-17 Mounting structure for semiconductor device

Country Status (1)

Country Link
JP (1) JPH065747A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723388A1 (en) * 1995-01-20 1996-07-24 Matsushita Electric Industrial Co., Ltd Printed circuit board
US6335862B1 (en) 1999-11-17 2002-01-01 Nec Corporation Multilayer printed wiring board provided with injection hole for thermally conductive filler
JP2022155786A (en) * 2021-03-31 2022-10-14 日立Astemo株式会社 electronic device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723388A1 (en) * 1995-01-20 1996-07-24 Matsushita Electric Industrial Co., Ltd Printed circuit board
US5817404A (en) * 1995-01-20 1998-10-06 Matsushita Electric Industrial Co., Ltd. Printed circuit board
US5960538A (en) * 1995-01-20 1999-10-05 Matsushita Electric Industrial Co., Ltd. Printed circuit board
US6335862B1 (en) 1999-11-17 2002-01-01 Nec Corporation Multilayer printed wiring board provided with injection hole for thermally conductive filler
JP2022155786A (en) * 2021-03-31 2022-10-14 日立Astemo株式会社 electronic device

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