JPH066043A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH066043A
JPH066043A JP4183054A JP18305492A JPH066043A JP H066043 A JPH066043 A JP H066043A JP 4183054 A JP4183054 A JP 4183054A JP 18305492 A JP18305492 A JP 18305492A JP H066043 A JPH066043 A JP H066043A
Authority
JP
Japan
Prior art keywords
circuit pattern
layer
printed wiring
wiring board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4183054A
Other languages
Japanese (ja)
Inventor
Tamotsu Onodera
保 小野寺
Hiroshi Katsushima
宏 勝島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
UMC Japan Co Ltd
Original Assignee
Tanaka Kikinzoku Kogyo KK
Nippon Steel Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Kikinzoku Kogyo KK, Nippon Steel Semiconductor Corp filed Critical Tanaka Kikinzoku Kogyo KK
Priority to JP4183054A priority Critical patent/JPH066043A/en
Publication of JPH066043A publication Critical patent/JPH066043A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】 【目的】 基板の外形寸法を大きくすることなく、実装
するチップ部品の搭載面積を拡大し、ICメモリーモジ
ュール基板の高密度化を図ったプリント配線基板を提供
する。 【構成】 多層基板の表面より座ぐり穴を形成して内層
回路パターンを露出し、座ぐり穴内にチップ部品を収納
搭載して、内層回路パターンと導通させ、座ぐり穴の開
口縁上に別のチップ部品を搭載して表層回路パターンと
導通させてなるプリント配線基板。
(57) [Summary] [Object] To provide a printed wiring board in which the mounting area of chip components to be mounted is expanded and the density of an IC memory module board is increased without increasing the external dimensions of the board. [Structure] A counterbore hole is formed from the surface of the multilayer board to expose the inner layer circuit pattern, and the chip parts are housed and mounted in the counterbore hole to conduct with the inner layer circuit pattern and separate on the opening edge of the counterbore hole. The printed wiring board on which the chip parts of above are mounted and electrically connected to the surface layer circuit pattern.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント配線基板に係
り、詳しくは部品搭載密度を向上させたICメモリーモ
ジュール基板を代表とする各種モジュール基板に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly to various module boards typified by an IC memory module board having an improved component mounting density.

【0002】[0002]

【従来の技術】従来、ICメモリーモジュール基板に搭
載されるチップ部品(TSOP(薄くて小さいパッケー
ジ)、SOJ(リードがJ型の小さいパッケージ)、チ
ップコンデンサー等)は、同一基板表面に密に配置設計
されてきたが、最近高密度薄型化の要求が高い。ICメ
モリーモジュール基板は、或る程度の高密度化の要求に
は対応できるが、「JEDEC(ジェデェック)規格」
等により基板の外形寸法に一定の規制があり、基板の表
面積に限度がある。従って、実装するチップ部品の搭載
面積にも限度がある。
2. Description of the Related Art Conventionally, chip components (TSOP (thin and small package), SOJ (small lead type J package), chip capacitors, etc.) mounted on an IC memory module substrate are densely arranged on the same substrate surface. It has been designed, but recently there is a strong demand for high-density thinning. The IC memory module substrate can meet the demand for higher density to some extent, but it is "JEDEC standard"
There are certain restrictions on the external dimensions of the substrate due to factors such as the above, and the surface area of the substrate is limited. Therefore, the mounting area of the chip components to be mounted is also limited.

【0003】[0003]

【発明が解決しようとする課題】そこで本発明は、基板
の外形寸法を大きくすることなく、実装するチップ部品
の搭載面積を拡大し、ICメモリーモジュール基板等の
各種モジュール基板の高密度化を図ったプリント配線基
板を提供しようとするものである。
Therefore, the present invention aims to increase the mounting area of chip components to be mounted and increase the density of various module substrates such as IC memory module substrates without increasing the outer dimensions of the substrate. The present invention is intended to provide a printed wiring board.

【0004】[0004]

【課題を解決するための手段】上記課題を解決するため
の本発明のプリント配線基板は、多層基板の表面より座
ぐり穴を形成して内層回路パターンを露出し、座ぐり穴
内にチップ部品を収容搭載して、内層回路パターンと導
通させ、座ぐり穴の開口縁上に別のチップ部品を搭載し
て表層回路パターンを導通させてなるものである。
In the printed wiring board of the present invention for solving the above-mentioned problems, a counterbore is formed from the surface of a multilayer board to expose an inner layer circuit pattern, and a chip component is placed in the counterbore. It is accommodated and mounted to be electrically connected to the inner layer circuit pattern, and another chip component is mounted on the opening edge of the counterbore hole to electrically connect the surface layer circuit pattern.

【0005】[0005]

【作用】上記のように本発明のプリント配線基板は、多
層基板の表面より座ぐり穴を形成して内層回路パターン
を露出しているので、基板の外形寸法を大きくすること
なく、実装するチップ部品を搭載する回路パターン面積
が拡大する。そして座ぐり穴内にチップ部品を収容搭載
して内層回路パターンと導通させ、座ぐり穴の開口縁上
に別のチップ部品を搭載して表層回路パターンと導通さ
せているので、ICメモリーモジュール基板が高密度化
する。
As described above, in the printed wiring board of the present invention, the inner layer circuit pattern is exposed by forming the counterbore from the surface of the multilayer board, so that the chip to be mounted can be mounted without increasing the outer dimension of the board. The circuit pattern area on which the parts are mounted is expanded. Then, the chip component is housed and mounted in the counterbore hole to conduct with the inner layer circuit pattern, and another chip component is mounted on the opening edge of the counterbore hole to conduct with the surface circuit pattern. Increase the density.

【0006】[0006]

【実施例】本発明のプリント配線基板の一実施例を図に
よって説明すると、図1に示す4層基板1を通常のサブ
トラクティブ法により積層成形して製作した後、表層つ
まり1層と4層の回路パターン2、3を形成し、SR
(ソルダレジスト)塗布を行った。次いで、表面よりド
リリングにより座ぐり穴4を形成して内層、本例では3
層目の回路パターン5を露出させた。そして座ぐり穴4
に防錆処理及びプリフラックス塗布を行った後、図2に
示すように直かにチップコンデンサー6を収容搭載し
て、3層目の回路パターン5と半田付けして導通させ
た。然る後、図3に示すように座ぐり穴4の開口縁上に
別のチップ部品、本例ではTSOP7を搭載して1層目
の回路パターン2と半田付けして導通させた。なお、各
層間の導通は通常のスルーホール形成により行うものと
する。
EXAMPLE An example of a printed wiring board according to the present invention will be described with reference to the drawings. After the four-layer board 1 shown in FIG. 1 is laminated and formed by an ordinary subtractive method, the surface layer, that is, one layer and four layers are formed. Forming circuit patterns 2 and 3 of
(Solder resist) was applied. Next, a counterbore 4 is formed from the surface by drilling to form an inner layer, 3 in this example.
The circuit pattern 5 of the layer was exposed. And counterbore 4
After rust prevention treatment and pre-flux coating, the chip capacitor 6 was directly housed and mounted as shown in FIG. 2, and was soldered to the circuit pattern 5 of the third layer for electrical connection. Then, as shown in FIG. 3, another chip component, TSOP7 in this example, was mounted on the opening edge of the counterbore hole 4 and soldered to the circuit pattern 2 of the first layer for electrical conduction. It should be noted that the conduction between the layers is performed by forming a normal through hole.

【0007】このように構成した実施例のプリント配線
基板8は、4層基板1の表面より座ぐり穴4が形成され
て3層目の回路パターン5が露出されているので、4層
基板1の外形寸法を大きくすることなく、実装するチッ
プ部品を搭載する回路パターン面積が拡大している。そ
して座ぐり穴4内にチップコンデンサー6が収容搭載さ
れて3層目の回路パターン5と導通され、座ぐり穴4の
開口縁上にTSOP7が搭載されて1層目の回路パター
ン2と導通されているので、ICメモリーモジュール基
板の高密度化が達成される。
In the printed wiring board 8 of the embodiment thus constructed, the counterbore hole 4 is formed from the surface of the four-layer board 1 and the circuit pattern 5 of the third layer is exposed. The area of the circuit pattern on which the chip components to be mounted is mounted is expanding without increasing the outer dimensions of the device. Then, the chip capacitor 6 is accommodated and mounted in the counterbore 4 and electrically connected to the circuit pattern 5 of the third layer, and the TSOP 7 is mounted on the opening edge of the counterbore 4 and electrically connected to the circuit pattern 2 of the first layer. Therefore, high density of the IC memory module substrate is achieved.

【0008】尚、上記実施例は、4層基板1の表面から
座ぐり穴4を形成して3層目の回路パターン5を露出さ
せているが、別途座ぐり穴を形成して2層目の回路パタ
ーンを露出させ、超小型のチップ部品を収容搭載して導
通させても良いものである。また、上記実施例は、4層
基板1に適用した場合であるが、6層基板、8層基板、
10層基板・・・等にも適用できるものであり、その場合
も座ぐり穴を形成して露出させる内層回路パターンは任
意に選択できるものである。さらに座ぐり穴を形成して
露出させる内層回路パターンは、チップ部品と導通させ
るものであるから、予め設計されたパターンでもって多
層基板の製作時に形成されるものである。また、ICメ
モリーモジュール以外の各種モジュール基板にも実施で
きる。
In the above embodiment, the counterbore 4 is formed from the surface of the four-layer substrate 1 to expose the circuit pattern 5 of the third layer, but a counterbore is separately formed to form the second layer. It is also possible to expose the circuit pattern of (1) and accommodate and mount an ultra-small chip component for electrical conduction. Further, although the above-mentioned embodiment is applied to the 4-layer substrate 1, a 6-layer substrate, an 8-layer substrate,
It can also be applied to a 10-layer substrate, etc., and even in that case, the inner layer circuit pattern to be exposed by forming the counterbore can be arbitrarily selected. Further, since the inner layer circuit pattern formed by forming the counterbore is exposed to the chip component, the inner layer circuit pattern is formed at the time of manufacturing the multilayer substrate with a predesigned pattern. It can also be applied to various module substrates other than the IC memory module.

【0009】[0009]

【発明の効果】以上の通り本発明のプリント配線基板
は、基板の外形寸法を大きくすることなく、実装するチ
ップ部品の搭載面積が拡大するので、ICメモリーモジ
ュール基板等の各種モジュール基板の高密度化が達成で
きる。また、チップ部品搭載時のモジュール全体厚を薄
くすることも可能である。
As described above, in the printed wiring board of the present invention, the mounting area of the chip components to be mounted is expanded without increasing the outer dimensions of the board, so that high density of various module boards such as IC memory module boards can be achieved. Can be achieved. It is also possible to reduce the overall thickness of the module when mounting chip components.

【図面の簡単な説明】[Brief description of drawings]

【図1】4層基板の表面から座ぐり穴を形成して3層目
の回路パターンを露出させた状態を示す要部断面図であ
る。
FIG. 1 is a cross-sectional view of essential parts showing a state in which a counterbore is formed in the surface of a four-layer substrate to expose a circuit pattern of a third layer.

【図2】図1の4層基板の座ぐり穴内にチップコンデン
サーを収容搭載して3層目の回路パターンと導通させた
状態を示す要部断面図である。
FIG. 2 is a cross-sectional view of essential parts showing a state in which a chip capacitor is housed and mounted in a counterbore hole of the four-layer substrate of FIG. 1 and is electrically connected to the circuit pattern of the third layer.

【図3】図2の4層基板の座ぐり穴の開口縁上にTSO
Pを搭載して1層目の回路パターンと導通させた状態を
示す要部断面図である。
FIG. 3 shows TSO on the opening edge of the counterbore hole of the four-layer substrate of FIG.
It is a principal part sectional view which shows the state which mounted P and was made to conduct with the circuit pattern of the 1st layer.

【符号の説明】[Explanation of symbols]

1 4層基板(多層基板) 2 1層目の回路パターン 3 4層目の回路パターン 4 座ぐり穴 5 3層目の回路パターン 6 チップコンデンサー 7 TSOP 8 プリント配線基板 1 4 layer board (multilayer board) 2 1st layer circuit pattern 3 4th layer circuit pattern 4 Counterbore hole 5 3rd layer circuit pattern 6 Chip capacitor 7 TSOP 8 Printed wiring board

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 多層基板の表面より座ぐり穴を形成して
内層回路パターンを露出し、座ぐり穴内にチップ部品を
収容搭載して、内層回路パターンと導通させ、座ぐり穴
の開口縁上に別のチップ部品を搭載して表層回路パター
ンと導通させてなるプリント配線基板。
1. A counterbore hole is formed from the surface of a multi-layer substrate to expose an inner layer circuit pattern, and a chip component is housed and mounted in the counterbore hole so as to be electrically connected to the inner layer circuit pattern and on an opening edge of the counterbore hole. A printed wiring board that has another chip component mounted on it and is electrically connected to the surface circuit pattern.
JP4183054A 1992-06-17 1992-06-17 Printed wiring board Pending JPH066043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4183054A JPH066043A (en) 1992-06-17 1992-06-17 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4183054A JPH066043A (en) 1992-06-17 1992-06-17 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH066043A true JPH066043A (en) 1994-01-14

Family

ID=16128933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4183054A Pending JPH066043A (en) 1992-06-17 1992-06-17 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH066043A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
US6043987A (en) * 1997-08-25 2000-03-28 Compaq Computer Corporation Printed circuit board having a well structure accommodating one or more capacitor components

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0774888A3 (en) * 1995-11-16 1998-10-07 Matsushita Electric Industrial Co., Ltd Printing wiring board and assembly of the same
US6324067B1 (en) 1995-11-16 2001-11-27 Matsushita Electric Industrial Co., Ltd. Printed wiring board and assembly of the same
US6043987A (en) * 1997-08-25 2000-03-28 Compaq Computer Corporation Printed circuit board having a well structure accommodating one or more capacitor components

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