JPH0660558A - Phase synchronizing oscillating device - Google Patents

Abstract

PURPOSE:To always execute phase synchronizing except when a sector pulse is logical '1', at the time of selecting a head, and at the time of seeking in the case a phase synchronizing oscillation circuit phase-synchronizes with a readout signal from a storing medium. CONSTITUTION:A sector pulse signal 3, a seeking signal 4 and a head selecting signal 5 are connected to a 1st control circuit 9 to express a phase-synchronizing condition. A signal outputted from the circuit 9 and a byte clock signal 6 where rectangular waves are continued are counted by a counter circuit 10 and outputted as an internal phase synchronizing control signal 1c. The signal 1c and a phase synchronizing control signal 2 are connected to a 2nd control circuit 11. The circuit 11 is connected to a phase synchronizing oscillation circuit 12 and judges based on the signals 1c and 2 whether or not the phase synchronizing with the storing medium can be possible, and outputs a phase synchronizing control rise signal 1a and a phase synchronizing control fall signal 1b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used for phase-locked oscillation used in magnetic disks and the like. According to the present invention, phase synchronization is not performed if the sector pulse is logical 1 with respect to the start of data reading, or if any one of the three conditions at the time of seek or head selection is applicable, and phase synchronization is not performed. In this case, the present invention relates to a phase-locked oscillator that can always be phase-locked with a read signal.

[0002]

2. Description of the Related Art A conventional phase-locked oscillator is constructed as shown in FIG. 6, and a reference clock is used for a read signal from a storage medium in the state of logic 1 of sector pulse, seek, or head select. The state of being in phase synchronization with was continued for a long time.

[0003]

As described above, in the conventional phase-locked oscillator, the phase-locked oscillator circuit synchronizes with the reference clock for conditions other than the above three conditions when starting data reading. There was a drawback that the state of staying for a long time.

The present invention solves such a problem, in which the state of the logic 1 of the sector pulse is set so that the time in phase synchronization with the reference clock does not last long.
An object of the present invention is to provide a device capable of not being phase-synchronized with a read signal when in a seek or head select state, and being able to be phase-synchronized with a read signal under conditions other than the above. To do.

[0005]

According to the present invention, a phase synchronization control signal, a sector pulse signal, a seek signal, and a head select signal are input from a storage medium, and a sector pulse logic 1 state, a seek state, and A first control circuit that determines whether or not to perform phase synchronization from the state at the time of head selection, and a phase synchronization that inputs the output signal from this first control circuit and performs the phase synchronization of the read signal from the storage medium. In a phase-locked oscillating device having an oscillating circuit, the distance from the storage medium to the write splice of the read signal based on the information from the first control circuit as to whether the phase synchronization is possible or not A counter circuit that counts with a clock signal, distance information from the counter circuit to the light splice, and a phase synchronization control signal from the storage medium. A second control circuit that outputs an internal phase synchronization control signal to the phase synchronization oscillation circuit as a phase synchronization instruction, and stores the phase synchronization oscillation circuit in accordance with the internal phase synchronization control signal from the second control circuit. It is characterized in that it includes means for performing phase synchronization of a read signal from the medium.

The counter circuit includes a phase synchronization detection circuit that receives a read signal from a storage medium and detects the end of phase synchronization, and the phase synchronization oscillation circuit includes a phase synchronization completion detection circuit that detects the end of phase synchronization. be able to.

[0007]

When the first control circuit inputs any one of the sector pulse signal, seek signal, and head select signal,
Whether or not to perform phase synchronization is determined depending on whether the sector pulse is in the logic 1 state, the seek state, or the head select state. When the phase synchronization is performed, the counter circuit outputs and The byte clock signal counts the distance from the storage medium to the write splice of the read signal. Then, the second control circuit outputs an internal phase synchronization control signal to the phase synchronization oscillation circuit as a phase synchronization command according to the information and the read signal from the storage medium. The phase-locked oscillator circuit phase-locks the read signal from the storage medium according to the signal.

As a result, when one of the three conditions of the logic 1 state, the seek state, and the head select state is satisfied with respect to the input condition of the storage medium, the phase synchronization is stopped and the next phase synchronization can be performed. It is possible to wait until the state and follow the data more quickly by performing the phase synchronization under the conditions other than the three conditions.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention. The first embodiment of the present invention is
A sector pulse signal 3, a seek signal 4, and a head select signal 5 are input from a storage medium (not shown), and a phase is determined depending on whether the sector pulse is in a logic 1 state, a seek state, or a head select state. A first control circuit 9 for determining whether or not to perform synchronization, and a phase-locked oscillation circuit 12 for performing phase synchronization of the read signal 1 from the storage medium are provided. Further, as a feature of the present invention, the first control is provided. A counter circuit 10 for counting the distance from the storage medium to the write splice of the read signal 1 from the storage medium by the byte clock signal 6 having a continuous rectangular wave on the basis of the information on whether the phase synchronization is possible from the circuit 9, and the counter circuit 10. The internal phase synchronization control signal 1c is issued as a phase synchronization command according to the distance information from the optical disk to the light splice and the read signal 1 from the storage medium. A second control circuit 11 for outputting to the circuit 12, and the phase-locked oscillator circuit 12 outputs a read signal from the storage medium according to the phase-locked control rising or falling signal 1a or 1b from the second control circuit 11. 1 means for performing phase synchronization.

The sector pulse signal 3, the seek signal 4, and the head select signal 5 are connected to the first control circuit 9, and the signal output from the first control circuit 9 and the byte clock signal 6 are connected to the counter circuit 10. It Further, the internal phase synchronization control signal 1c and the phase synchronization control signal 2 output from the counter circuit 10 are connected to the second control circuit 11, and the read signal 1 and the phase synchronization control output from the second control circuit 11 are connected. The rising signal 1a and the phase synchronization control falling signal 1b are connected to the phase synchronization oscillation circuit 12.

When data reading is started from the storage medium, when any one of the sector pulse signal 3, seek signal 4 and head select signal 5 is input to the first control circuit 9, the counter circuit 10 immediately responds to the read signal 1. The second control circuit 11 is instructed to cancel the phase synchronization. The byte clock signal 6 counts the position of the light splice on the storage medium and supplies it to the counter circuit 10 as information. The phase synchronization control signal 2 and the internal phase synchronization control signal 1c output from the counter circuit 10 are input to the second control circuit 11 to determine whether to activate the phase synchronization control signal 2. The read signal 1 and the second control circuit 11 supply the phase synchronization information to the phase synchronization oscillation circuit 12. The standard data pulse signal 7 and the standard data clock 8 are output as output signals.

FIG. 5 is a flow chart showing the flow of the above-mentioned phase synchronization in the embodiment of the present invention.

(Second Embodiment) FIG. 2 is a block diagram showing the configuration of the second embodiment of the present invention. The second embodiment of the present invention includes a phase synchronization detection circuit 24 for inputting the read signal 1 from the storage medium to the counter circuit 10a and detecting the end of the phase synchronization, and is otherwise configured similarly to the first embodiment.

In the second embodiment, the sector pulse signal 3, the seek signal 4, and the head select signal 5 are input to the first control circuit 9 and the counter circuit 10a is output from the first control circuit 9. Also, the byte clock signal 6 is input and the internal phase synchronization control signal 1c is output to the second control circuit 11. From the second control circuit 11, the phase synchronization control rising signal 1a or the phase synchronization control falling signal 1 is output.
b is output to the phase-locked oscillator circuit 12 to supply phase-locked information. The phase-locked oscillator circuit 12 outputs a standard data pulse signal 7 and a standard data clock signal 8 as in the first embodiment.

Phase synchronization detection circuit 2 of counter circuit 10a
A read signal 1 from the storage medium is input to the second control circuit 4, and when the end of the phase synchronization is detected, the second control circuit 11
To the phase-locked oscillator circuit 12 via the.

(Third Embodiment) FIG. 3 is a block diagram showing the configuration of the third embodiment of the present invention. The third embodiment of the present invention includes a phase-locking completion detecting circuit 36 for detecting the end of phase-locking in the phase-locked oscillator circuit 12a, and the other parts are configured similarly to the first embodiment.

In the third embodiment, the sector pulse signal 3,
The seek signal 4 and the head select signal 5 are input to the first control circuit 9, and the counter circuit 10 inputs the signal output from the first control circuit 9 and the byte clock signal 6. The second control circuit 11 inputs the internal phase synchronization control signal 1c and the phase synchronization control signal 2 from the counter circuit 10, and outputs the phase synchronization control rising signal 1a or the phase synchronization control falling signal 1b to the phase synchronization oscillator circuit 12a. Output. The phase synchronization completion detection circuit 36 detects the phase synchronization completion by the read signal 1 from the storage medium.

(Fourth Embodiment) FIG. 4 is a block diagram showing the configuration of the fourth embodiment of the present invention. The fourth embodiment of the present invention includes a phase synchronization detection circuit 24 for inputting the read signal 1 from the storage medium to the counter circuit 10a to detect the end of the phase synchronization as shown in the second embodiment, and further, the third embodiment. As shown in FIG. 3, the phase-locked oscillator circuit 12a includes a phase-locking completion detecting circuit 36 for detecting the end of phase-locking.

In the fourth embodiment, the sector pulse signal 3,
The seek signal 4 and the head select signal 5 are input to the first control circuit 9, and the signal output from the first control circuit 9, the read signal 1 from the storage medium, and the byte clock signal 6 are input to the counter circuit 10. To enter. The second control circuit 11 inputs the internal phase synchronization control circuit 1c and the phase synchronization control signal 2 from the counter circuit 10a, and inputs the phase synchronization control rising signal 1a or the phase synchronization control falling signal 1b to the phase synchronization oscillator circuit 12a. To do. The phase synchronization detection circuit 24 and the phase synchronization completion detection circuit 36 detect the phase synchronization completion by the read signal 1 from the storage medium.

[0021]

As described above, according to the present invention, the phase synchronization is achieved when any one of the three conditions of the input condition of the storage medium, that is, the state of logic 1, seek, and head select is satisfied. It is possible to stop and wait until the next phase synchronization is possible, and under the conditions other than the above three conditions, there is an effect that the read signal can always be phase-synchronized to follow the data faster.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a third embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of a fourth embodiment of the present invention.

FIG. 5 is a timing chart showing a process of phase synchronization in the embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 read signal 1a phase synchronization control rising signal 1b phase synchronization control falling signal 1c internal phase synchronization control signal 2 phase synchronization control signal 3 sector pulse signal 4 seek signal 5 head select signal 6 byte clock signal 7 standard data pulse signal 8 standard data Clock signal 9 First control circuit 10, 10a Counter circuit 11 Second control circuit 12, 12a Phase synchronization oscillator circuit 24 Phase synchronization detection circuit 36 Phase synchronization completion detection circuit

Claims (1)

[Claims] 1. A phase synchronization control signal, a sector pulse signal, a seek signal, and a head select signal are input from a storage medium, and phase synchronization is performed from a logic 1 state of a sector pulse, a seek state, and a head select state. Phase synchronization including a first control circuit that determines whether or not to perform a phase synchronization oscillation circuit that inputs the output signal from the first control circuit and synchronizes the phase of the read signal from the storage medium. In the oscillator, a counter circuit that counts the distance to the write splice of the read signal from the storage medium by a continuous byte clock signal of a rectangular wave based on the information from the first control circuit as to whether the phase synchronization is possible or not. Internally as a phase synchronization command by the distance information to the light splice from this counter circuit and the phase synchronization control signal from the storage medium. A second control circuit for outputting a phase synchronization control signal to the phase synchronization oscillation circuit, wherein the phase synchronization oscillation circuit outputs a read signal from a storage medium according to an internal phase synchronization control signal from the second control circuit. A phase-locked oscillation device including means for performing phase synchronization of