JPH0666984B2 - Electronic exchange initialization method - Google Patents

Electronic exchange initialization method

Info

Publication number
JPH0666984B2
JPH0666984B2 JP59170181A JP17018184A JPH0666984B2 JP H0666984 B2 JPH0666984 B2 JP H0666984B2 JP 59170181 A JP59170181 A JP 59170181A JP 17018184 A JP17018184 A JP 17018184A JP H0666984 B2 JPH0666984 B2 JP H0666984B2
Authority
JP
Japan
Prior art keywords
control circuit
initialization
terminal
circuit
terminal control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP59170181A
Other languages
Japanese (ja)
Other versions
JPS6148292A (en
Inventor
幸一郎 籔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59170181A priority Critical patent/JPH0666984B2/en
Publication of JPS6148292A publication Critical patent/JPS6148292A/en
Publication of JPH0666984B2 publication Critical patent/JPH0666984B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54516—Initialization, software or data downloading
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13376—Information service, downloading of information, 0800/0900 services

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、分散制御型電子交換機の初期化方式の改良に
関する。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement in an initialization system of a distributed control type electronic exchange.

〔発明の技術的背景〕[Technical background of the invention]

従来、この種の電子交換機として次のようなものが知ら
れている。第５図はその構成を示す回路ブロック図であ
る。すなわちこの交換機は、中央制御回路１と、それぞ
れ電話機やデータ伝送機器等の複数の端末１０が接続さ
れた複数の端末制御回路２１〜２ｎとを備えている。こ
の制御回路１，２１〜２ｎはそれぞれ主制御部としてマ
イクロコンピュータを有するもので、このマイクロコン
ピュータにより中央制御回路１は交換動作に係わる全体
的な制御を行ない、一方各端末制御回路２１〜２ｎは端
末１０に対する各種接続制御を行なう。Conventionally, the following is known as this type of electronic exchange. FIG. 5 is a circuit block diagram showing its configuration. That is, this exchange includes a central control circuit 1 and a plurality of terminal control circuits 21 to 2n to which a plurality of terminals 10 such as telephones and data transmission devices are connected. The control circuits 1, 21 to 2n each have a microcomputer as a main control unit, and the microcomputer controls the central control circuit 1 as a whole, while the terminal control circuits 21 to 2n respectively. Various connection controls for the terminal 10 are performed.

例えば、端末制御回路２１に接続されている端末１０が
発呼すると、端末制御回路２１はこの発呼を検出してそ
の旨および呼出し先の番号を表わす制御信号を制御信号
路３に出力する。このとき、上記制御信号路３は各端末
制御回路２１〜２ｎからの制御信号を時分割でシリアル
伝送するように構成されており、これにより伝送された
上記端末制御回路２１の制御信号は制御信号送受信回路
４でパラレル信号に変換されたのち共通バス５を介して
中央制御回路１に導入される。そうすると中央制御回路
１は、呼出し相手端末が接続されている端末制御回路、
例えば２ｎに対し上記と逆の経路で制御信号を送り、こ
れにより端末制御回路２ｎに呼出し相手端末に対する接
続制御を行なわせる。そしてこの接続制御が完了して端
末制御回路２ｎからその旨の制御信号が到来すると、中
央制御回路１は共通バス５を介して通話路制御回路６へ
制御信号を送出し、これにより通話回路７を切換制御し
て前記端末制御回路２１と端末制御回路２ｎとの間を通
話バス８を介して接続させる。かくして端末相互間で通
話が可能となる。尚、９は接続制御動作に必要な各種デ
ータを格納した主記憶回路である。For example, when the terminal 10 connected to the terminal control circuit 21 makes a call, the terminal control circuit 21 detects this call and outputs a control signal indicating the fact and the called number to the control signal line 3. At this time, the control signal path 3 is configured to serially transmit the control signals from the terminal control circuits 21 to 2n in a time-division manner, and the control signal of the terminal control circuit 21 transmitted by this is the control signal. After being converted into a parallel signal by the transmission / reception circuit 4, it is introduced into the central control circuit 1 via the common bus 5. Then, the central control circuit 1 causes the call control terminal to be connected to the terminal control circuit,
For example, a control signal is sent to 2n through a route reverse to that described above, thereby causing the terminal control circuit 2n to perform connection control for the calling partner terminal. When this connection control is completed and a control signal to that effect arrives from the terminal control circuit 2n, the central control circuit 1 sends a control signal to the speech path control circuit 6 via the common bus 5, whereby the speech circuit 7 The terminal control circuit 21 and the terminal control circuit 2n are connected via the communication bus 8 by switching control. Thus, it becomes possible to talk between the terminals. Reference numeral 9 is a main memory circuit that stores various data necessary for the connection control operation.

ところで、この様な構成の電子交換機において、端末制
御回路２１〜２ｎのマイクロコンピュータが何等かの原
因、例えば外来ノイズ、回路の誤動作あるいはプログラ
ムバグ等により暴走したとすると、一般に端末制御回路
には暴走検出回路が設けてあるため、上記マイクロコン
ピュータの暴走はこの暴走検出回路で検出され、端末制
御回路はその検出出力により通話中の端末を強制的に切
断するとともに自身の回路の動作状態を初期化する。と
ころが、この様にマイクロコンピュータが暴走を起こし
た場合、該当する端末制御回路ばかりでなく、この端末
制御回路に接続された端末と通話中であった相手端末も
強制的に切断する必要がある。In the electronic exchange having such a configuration, if the microcomputers of the terminal control circuits 21 to 2n are out of control due to some cause, for example, external noise, circuit malfunction or program bug, the terminal control circuits generally run out of control. Since a detection circuit is provided, the runaway of the above microcomputer is detected by this runaway detection circuit, and the terminal control circuit forcibly disconnects the terminal in the call by the detection output and initializes the operating state of its own circuit. To do. However, when the microcomputer goes out of control in this way, it is necessary to forcibly disconnect not only the corresponding terminal control circuit but also the other terminal that is in a call with the terminal connected to this terminal control circuit.

そこで従来では、暴走が発生したときその端末制御回路
２１〜２ｎから中央制御回路１へ初期化要求信号を送
り、中央制御回路１はこの初期化要求信号が到来した時
点で即時初期化制御モードに移行して、上記暴走を起こ
した端末制御回路およびこの端末制御回路に接続された
端末と通話中の端末がある端末制御回路に対し、それぞ
れ初期化指示信号を送出し、これにより各端末および端
末制御回路を初期化するようにしている。Therefore, conventionally, when a runaway occurs, the terminal control circuits 21 to 2n send an initialization request signal to the central control circuit 1, and the central control circuit 1 enters the immediate initialization control mode when the initialization request signal arrives. An initialization instruction signal is sent to each of the terminal control circuit that has made a transition and has caused the runaway, and the terminal connected to this terminal control circuit and the terminal in communication with each other. The control circuit is initialized.

〔背景技術の問題点〕[Problems of background technology]

しかるに、この様な従来の初期化方式は、初期化要求信
号が発生された時点で中央制御回路に初期化制御を行な
わせるものであるため、中央制御回路１で実行中又は実
行しようとしている他の制御動作が有る場合に、これら
の制御動作が中断又は遅延されて他の正常な通話制御動
作に悪影響を与える欠点があった。However, such a conventional initialization method causes the central control circuit to perform the initialization control at the time when the initialization request signal is generated, and therefore the central control circuit 1 is performing or is about to execute the initialization control. However, there is a drawback that these control operations are interrupted or delayed and adversely affect other normal call control operations.

〔発明の目的〕[Object of the Invention]

本発明は、端末制御回路が暴走を起こした場合などに、
中央制御回路が実行中または実行しようとしている他の
制御動作に影響を及ぼすことなく、所定のすべての初期
化制御を行なえ、しかもこの制御を小容量の共通メモリ
を用いるだけで実行できる電子交換機の初期化方式を提
供することを目的とする。The present invention, when the terminal control circuit has runaway,
An electronic exchange that can perform all predetermined initialization controls without affecting other control operations being executed or being executed by the central control circuit, and that can be executed only by using a small-capacity common memory. The purpose is to provide an initialization method.

〔発明の概要〕[Outline of Invention]

本発明は、上記目的を達成するために、各端末制御回路
側と中央制御回路側とが各別にアクセス可能で、かつ複
数の端末制御回路が共用する初期化用記憶領域を有した
共通メモリを設けている。そして、端末制御回路の暴走
発生時などの所望時に、端末制御回路において初期化要
求と自己の端末制御回路の識別番号とを一組とした情報
を発生して上記共通メモリの初期化用記憶領域に書き込
み、中央制御回路において空き時間に上記共通メモリの
初期化用記憶領域をアクセスして初期化要求の有無を判
定し、初期化要求があった場合に上記空き時間に所定の
初期化制御動作を行なうようにしたものである。In order to achieve the above object, the present invention provides a common memory that is accessible to each terminal control circuit side and the central control circuit side and has a storage area for initialization shared by a plurality of terminal control circuits. It is provided. Then, at the desired time such as occurrence of runaway of the terminal control circuit, the terminal control circuit generates information including a pair of the initialization request and the identification number of its own terminal control circuit to generate the initialization storage area of the common memory. In the free time, the central control circuit accesses the initialization storage area of the common memory to determine the presence / absence of an initialization request, and if there is an initialization request, performs a predetermined initialization control operation in the free time. It was designed to do.

〔発明の実施例〕Example of Invention

第１図は、本発明の初期化方式を適用した電子交換機の
回路ブロック図である。尚同図において、前記第５図と
同一部分には同一符号を付して詳しい説明は省略する。FIG. 1 is a circuit block diagram of an electronic exchange to which the initialization method of the present invention is applied. In the figure, the same parts as those in FIG. 5 are designated by the same reference numerals and detailed description thereof will be omitted.

本実施例の初期化方式の従来方式と構成を異にするとこ
ろは、中央制御回路１１の共通バス５に、中央制御回路
１１と制御信号送受信回路１２とからそれぞれアクセス
可能な共通メモリ２０を接続し、端末制御回路２１〜２
ｎから発生された初期化要求信号を制御信号送受信回路
１２により上記共通メモリ２０に書き込むとともに、こ
の共通メモリ２０に記憶された初期化信号を中央制御回
路１１により制御動作の空き時間に読み出して所定の初
期化処理を行なうようにした点である。ここで、上記共
通メモリ２０は、例えば各端末制御回路２１〜２ｎ分の
記憶ビットを有するレジスタからなる。The difference between the initialization method of the present embodiment and the conventional method is that a common memory 20 accessible from the central control circuit 11 and the control signal transmitting / receiving circuit 12 is connected to the common bus 5 of the central control circuit 11. The terminal control circuits 21 to 2
The initialization request signal generated from n is written in the common memory 20 by the control signal transmission / reception circuit 12, and the initialization signal stored in the common memory 20 is read by the central control circuit 11 in the idle time of the control operation. This is the point that the initialization process of is performed. Here, the common memory 20 is composed of, for example, a register having storage bits for the respective terminal control circuits 21 to 2n.

すなわち、制御信号送受信回路１２は、例えば第２図に
示す如く通常の送受信制御動作（ステップ２ａ）を１回
実行する毎に、ステップ２ｂで初期化要求信号の到来の
有無を監視している。そして、この状態で端末制御回路
のマイクロコンピュータが暴走を起こし、これにより端
末制御回路から初期化要求信号が送られると、制御信号
送受信回路１２は上記ステップ２ｂで初期化要求信号の
到来を検出してステップ２ｃに移行し、ここで先ず上記
初期化要求信号が挿入されているタイムスロットの位置
から初期化要求信号を発生した端末制御回路を判別す
る。そして、続いてステップ２ｄに移行し、ここで共通
メモリ２０の各記憶ビットのうち上記ステップ２ｃで判
別した端末制御回路に対応する記憶ビットに“１”を書
き込む。That is, the control signal transmission / reception circuit 12 monitors the presence or absence of the initialization request signal in step 2b every time the normal transmission / reception control operation (step 2a) is performed once as shown in FIG. 2, for example. When the microcomputer of the terminal control circuit runs out of control in this state and the initialization request signal is sent from the terminal control circuit, the control signal transmitting / receiving circuit 12 detects the arrival of the initialization request signal in step 2b. Then, the process proceeds to step 2c, and first, the terminal control circuit which has generated the initialization request signal is discriminated from the position of the time slot in which the initialization request signal is inserted. Then, subsequently, the process proceeds to step 2d, where "1" is written in the memory bit corresponding to the terminal control circuit determined in step 2c among the memory bits of the common memory 20.

一方中央制御回路１１は、通常時に、ステップ３ａで通
常の通話制御動作を実行する毎にステップ３ｂで制御動
作に空き時間ができたか否かを監視しており、空き時間
ができる毎にステップ３ｃに移行してここで共通メモリ
２０をアクセスし、しかるのちステップ３ｄで共通メモ
リ２０に初期化要求信号が発生したことを示す“１”が
記憶されているか否かを判定している。そして、このス
テップ３ｄで“１”有りと判定すると中央制御回路１１
は、先ずステップ３ｅで上記“１”の記憶位置から初期
化要求を発生した端末制御回路を認識し、ステップ３ｆ
でこの認識した端末制御回路に対しリセット要求信号を
送出する。また、続いてステップ３ｇで、上記初期化要
求の有った端末制御回路の端末と通話中の端末が有るか
否かを検出し、有ればステップ３ｈに移行してここで上
記通話中の端末が接続されている端末制御回路に対し、
リセット要求信号を送出する。この結果、上記初期化要
求を発した端末制御回路、つまり暴走を起こした端末制
御回路のマイクロコンピュータとこれに接続される端末
とがそれぞれ初期化されるとともに、この暴走を起こし
た端末制御回路に接続された端末と通話していた端末が
強制的に初期化される。そしてこれらの初期化を終了す
ると中央制御回路１１は、最終にステップ３ｉで交換機
内の初期化を必要とする各部分の初期化を実行し、ステ
ップ３ａに戻る。かくして一連の初期化制御が終了す
る。On the other hand, in the normal operation, the central control circuit 11 monitors whether or not there is an idle time in the control operation in step 3b every time the normal call control operation is executed in step 3a, and in step 3c each time the idle time is available. Then, the common memory 20 is accessed here, and then it is determined in step 3d whether or not "1" indicating that the initialization request signal is generated is stored in the common memory 20. Then, when it is determined that "1" is present in step 3d, the central control circuit 11
First, in step 3e, the terminal control circuit which has issued the initialization request is recognized from the storage position of "1", and in step 3f
Then, a reset request signal is sent to the recognized terminal control circuit. Further, subsequently, in step 3g, it is detected whether or not there is a terminal in communication with the terminal of the terminal control circuit for which the initialization request has been made. For the terminal control circuit to which the terminal is connected,
Send a reset request signal. As a result, the terminal control circuit that issued the initialization request, that is, the microcomputer of the terminal control circuit that caused the runaway and the terminal connected thereto are initialized, respectively, and the terminal control circuit that caused the runaway is initialized. The terminal that was talking to the connected terminal is forcibly initialized. When these initializations are completed, the central control circuit 11 finally executes the initialization of each part in the exchange that requires initialization in step 3i, and returns to step 3a. Thus, a series of initialization control ends.

このように本実施例であれば、端末制御回路２１〜２ｎ
から初期化要求信号が発生されたときにその旨を制御信
号送受信回路１２により共通メモリ２０に記憶してお
き、中央制御回路１１の通常制御動作の空き時間に上記
共通メモリの記憶内容を判定して初期化要求が有った場
合に所定の初期化処理を行なうようにしたことによっ
て、中央制御回路１１の通常制御動作には何等悪影響を
与えることなく、所定の全ての初期化を行なうことがで
きる。従って、別の正常な通話制御動作が中断された
り、また遅延する等の不具合は生じず、この結果安定な
通話制御動作を行なうことができる。In this way, according to the present embodiment, the terminal control circuits 21 to 2n
When the initialization request signal is generated from the control signal transmitting / receiving circuit 12, the control signal transmitting / receiving circuit 12 stores the fact in the common memory 20, and the stored content of the common memory is determined during the idle time of the normal control operation of the central control circuit 11. By performing the predetermined initialization processing when there is a request for initialization, it is possible to perform all the predetermined initialization without adversely affecting the normal control operation of the central control circuit 11. it can. Therefore, a trouble such as another normal call control operation being interrupted or delayed does not occur, and as a result, a stable call control operation can be performed.

また、本実施例では、新たにレジスタからなる共通メモ
リ２０を設け、かつ制御信号送受信回路１２および中央
制御回路１１の制御手順を多少変更するだけで実施でき
るので、電子交換機の構成が複雑化することがない。Further, in the present embodiment, since the common memory 20 including a register is newly provided and the control procedure of the control signal transmission / reception circuit 12 and the central control circuit 11 can be slightly changed, the configuration of the electronic exchange becomes complicated. Never.

尚、本発明は上記実施例に限定されるものではない。例
えば、各端末制御回路２１′〜２ｎ′と中央制御回路１
１′とがバッファ回路１３を介してＣＰＵバス結合され
ている場合には、共通バス５′に共通メモリ２０を接続
してこの共通メモリ２０を各端末制御回路２１′〜２
ｎ′および中央制御回路１１′により直接アクセスすれ
ばよい。また、共通メモリは、初期化要求信号が発生し
た旨とこの信号を発生した端末制御回路の識別番号とを
一組として記憶するようにしたものでもよい。このよう
にすれば、共通メモリの記憶領域を各端末制御回路の分
だけ設ける必要がなく、２，３回路分だけ設ればよくな
るので、これにより記憶容量を低減することができる。
またこのようにしても、一般に多数の端末制御回路が同
時に初期化要求を発生する確率は極めて少ないので、記
憶領域がオーバフローする不具合はほとんど生じない。
その他、共通メモリの構成、書込み手段および読出し手
段等についても、本発明の要旨を逸脱しない範囲で種々
変形して実施できる。The present invention is not limited to the above embodiment. For example, each terminal control circuit 21 'to 2n' and the central control circuit 1
When 1'is connected to the CPU bus via the buffer circuit 13, the common memory 20 is connected to the common bus 5'and the common memory 20 is connected to each of the terminal control circuits 21'-2.
It may be directly accessed by n'and the central control circuit 11 '. Further, the common memory may store the fact that the initialization request signal is generated and the identification number of the terminal control circuit that generated this signal as a set. With this configuration, it is not necessary to provide the storage area of the common memory for each terminal control circuit, and it is sufficient to provide only a few circuits, so that the storage capacity can be reduced.
Even in this case, the probability that a large number of terminal control circuits will simultaneously issue initialization requests is generally very small, so that the problem of overflow of the storage area hardly occurs.
In addition, the configuration of the common memory, the writing unit, the reading unit, and the like can be variously modified and implemented without departing from the scope of the present invention.

〔発明の効果〕〔The invention's effect〕

以上詳述したように本発明は、各端末制御回路側と中央
制御回路側とが各別にアクセス可能で、かつ複数の端末
制御回路が共用する初期化情報記憶領域を有した共通メ
モリを設けている。そして、端末制御回路の暴走発生時
などの所望時に、端末制御回路において初期化要求と自
己の端末制御回路の識別番号とを一組とした情報を発生
して上記共通メモリの初期化情報記憶領域に書き込み、
中央制御回路において空き時間に上記共通メモリの初期
化情報記憶領域をアクセスして初期化要求の有無を判定
し、初期化要求があった場合に上記空き時間に所定の初
期化制御動作を行なうようにしたものである。As described in detail above, according to the present invention, a common memory having an initialization information storage area which is accessible to each terminal control circuit side and the central control circuit side and which is shared by a plurality of terminal control circuits is provided. There is. Then, at the desired time such as occurrence of runaway of the terminal control circuit, the terminal control circuit generates information including a pair of the initialization request and the identification number of its own terminal control circuit to generate the initialization information storage area of the common memory. Write to
In the central control circuit, the initialization information storage area of the common memory is accessed in the idle time to determine whether or not there is an initialization request, and when there is the initialization request, a predetermined initialization control operation is performed in the idle time. It is the one.

したがって本発明によれば、端末制御回路が暴走を起こ
した場合などに、中央制御回路が実行中または実行しよ
うとしている他の制御動作に影響を及ぼすことなく、所
定のすべての初期化制御を行なうことができる。Therefore, according to the present invention, when the terminal control circuit runs out of control, all the predetermined initialization control is performed without affecting other control operations being executed or being executed by the central control circuit. be able to.

また、共通メモリの初期化情報記憶領域を複数の端末制
御回路が共用する構成とし、端末制御回路にて暴走等が
発生した場合に、その初期化要求と端末制御回路の識別
番号とを一組とした情報を上記共通メモリの初期化情報
記憶領域に書き込むようにしたので、共通メモリに各端
末制御回路の数に対応する分だけ記憶領域を設ける必要
がなくなり、これにより共通メモリの記憶容量を低減す
ることができる。Further, the initialization information storage area of the common memory is configured to be shared by a plurality of terminal control circuits, and when a runaway or the like occurs in the terminal control circuit, a set of the initialization request and the identification number of the terminal control circuit is set. Since the above information is written in the initialization information storage area of the common memory, it is not necessary to provide as many storage areas in the common memory as the number of each terminal control circuit, thereby increasing the storage capacity of the common memory. It can be reduced.

【図面の簡単な説明】[Brief description of drawings]

第１図乃至第３図は本発明の一実施例における初期化方
式を説明するためのもので、第１図は同方式を適用した
電子交換機の回路ブロック図、第２図および第３図は制
御手順を示すフローチャート、第４図は本発明の他の実
施例における初期化方式を適用した電子交換機の回路ブ
ロック図、第５図は従来の初期化方式を適用した電子交
換機の回路ブロック図である。 ２１〜１ｎ，２１′〜２ｎ′……端末制御回路、３……
制御信号路、５，５′……共通バス、６……通話路制御
回路、７……通話回路、８……通話バス、９……主記憶
回路、１０……端末、１１……中央制御回路、１２……
制御信号送受信回路、１３……バッファ回路、２０……
共通メモリ。1 to 3 are for explaining an initialization method in one embodiment of the present invention. FIG. 1 is a circuit block diagram of an electronic exchange to which the same method is applied, and FIGS. FIG. 4 is a flow chart showing a control procedure, FIG. 4 is a circuit block diagram of an electronic exchange to which an initialization method according to another embodiment of the present invention is applied, and FIG. 5 is a circuit block diagram of an electronic exchange to which a conventional initialization method is applied. is there. 21-1n, 21'-2n '... Terminal control circuit, 3 ...
Control signal path, 5, 5 '... common bus, 6 ... call path control circuit, 7 ... call circuit, 8 ... call bus, 9 ... main memory circuit, 10 ... terminal, 11 ... central control Circuit, 12 ...
Control signal transmitting / receiving circuit, 13 ... Buffer circuit, 20 ...
Common memory.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】各々端末が接続される複数の端末制御回路
と、中央制御回路とを備え、これらの制御回路により各
端末間の通話動作を分散制御する電子交換機において、 前記各端末制御回路側と中央制御回路側とが各別にアク
セス可能で、かつ前記複数の端末制御回路が共用する初
期化用記憶領域を有した共通メモリを設け、 前記各端末制御回路は、所望時に初期化要求と自己の端
末制御回路の識別番号とを一組とした情報を発生して前
記共通メモリの初期化用記憶領域に書き込み、 前記中央制御回路は、空き時間に、前記共通メモリの初
期化用記憶領域から記憶情報を読み出して初期化要求の
有無を判定するとともに、初期化要求があった場合に所
定の初期化制御動作を行なうことを特徴とする電子交換
機の初期化方式。1. An electronic exchange, comprising: a plurality of terminal control circuits to which each terminal is connected; and a central control circuit, wherein these control circuits decentralize and control call operations between the terminals. And a central control circuit side are separately accessible, and a common memory having a storage area for initialization shared by the plurality of terminal control circuits is provided. And generates the information including a pair of the identification number of the terminal control circuit of the terminal control circuit, and writes the information in the initialization storage area of the common memory. An initialization method for an electronic exchange characterized by reading stored information to determine whether there is an initialization request and performing a predetermined initialization control operation when an initialization request is made.
JP59170181A 1984-08-15 1984-08-15 Electronic exchange initialization method Expired - Fee Related JPH0666984B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59170181A JPH0666984B2 (en) 1984-08-15 1984-08-15 Electronic exchange initialization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59170181A JPH0666984B2 (en) 1984-08-15 1984-08-15 Electronic exchange initialization method

Publications (2)

Publication Number Publication Date
JPS6148292A JPS6148292A (en) 1986-03-08
JPH0666984B2 true JPH0666984B2 (en) 1994-08-24

Family

ID=15900185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59170181A Expired - Fee Related JPH0666984B2 (en) 1984-08-15 1984-08-15 Electronic exchange initialization method

Country Status (1)

Country Link
JP (1) JPH0666984B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117891A (en) * 1982-12-24 1984-07-07 Fujitsu Ltd Initializing system of failed terminal

Also Published As

Publication number Publication date
JPS6148292A (en) 1986-03-08

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