JPH0667748A - Clock control system - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to a clock control system for controlling a clock of a controller, and in order to save power of a controller operating by the clock, sleep / stop of an external clock or an internal clock is made simple. It is intended to be shared. [Configuration] A setting port 3 for setting an input state of an external clock or a connection state of an oscillator 4 is provided in a controller 1 operating with a clock, and when the setting port 3 is in an input state of an external clock (for example, H level) , It takes in an external clock and operates by using it to save power in response to the low frequency or stoppage of the external clock, while the setting port 3 is in the connection state of the oscillator 4 (for example, L level). In addition, the clock is taken from the oscillator 4 and operated by using the clock, and the internal clock is configured to operate at a low frequency or stopped to save power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control system for controlling a clock of a controller.

[0002]

2. Description of the Related Art Conventionally, a keyboard controller 21 as shown in FIG. 4A, which is composed of a microcomputer operating in synchronization with a clock, receives a clock from an external system gate array 22. The system gate array 22 switches the keyboard clock to the LOW clock or stops the keyboard clock to save power. At this time, the keyboard controller 21 changes the system gate array 22.
In response to sending the clock control signal to
Switching the keyboard clock to LOW clock,
You have stopped the keyboard clock.

Further, as shown in FIG. 4B, when the oscillator 26 is directly connected to the keyboard controller 24 to supply a clock, the keyboard controller 2 is connected.
4 controls the oscillator 26 to turn on the keyboard clock
Power was saved by controlling N / OFF.

[0004]

Conventionally, as shown in FIG.
4A, the keyboard controller 21 receives the keyboard clock as an external clock from the external system gate array 22, and the keyboard controller 24 is directly connected to the keyboard controller 24 as shown in FIG. 4B. If the oscillator 26 is used to generate the KU keyboard clock as the internal clock, the keyboard controllers 21 and 24 need to be designed and replaced.

The present invention solves these problems.
The purpose of this invention is to enable sleep / stop of an external clock and an internal clock to be shared with a simple configuration in order to save power of a controller that operates on a clock.

[0006]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, a controller 1 is a circuit that operates using a clock,
It has a setting port 3, a connection terminal for the vibrator 4, and the like.

The setting port 3 is for setting the input state of the external clock (for example, H level) and the connection state of the vibrator 4 (for example, L level). The oscillator 4 generates an internal clock.

[0008]

According to the present invention, as shown in FIG. 1, the setting port 3 is provided in the controller 1 which operates with a clock, and when the setting port 3 is in the input state (for example, H level) of the external clock, the external clock is taken in. Works using this,
On the other hand, when the setting port 3 is in the connected state of the vibrator 4 (for example, L level), the clock from the vibrator 4 is fetched and used to operate.

At this time, when the setting port 3 is in the input state (for example, H level) of the external clock, the external clock is taken in and used to operate, and the low frequency clock or the clock is stopped from the setting port 3. A signal is transmitted, and a circuit which receives the signal stops the clock transmitted to the controller 1 at a low frequency or stops so as to save power.

Further, the controller 1 is composed of CMOS. Therefore, it becomes possible to share sleep / stop of the external clock and the internal clock with a simple configuration in order to save power of the controller 1 that operates on the clock.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a block diagram of an embodiment of the present invention.
FIG. 1A shows an example of operation by an internal clock, and FIG. 1B shows an example of operation by an external clock.

In FIGS. 1A and 1B, a controller 1 is a circuit that operates by using a clock, and is a microcomputer or the like composed of CMOS. Here, a keyboard incorporating the microcomputer is used. The controller. The controller 1 has a terminal for connecting the setting port 3 and the vibrator 4 here.

The setting port 3 is used to set the input state of the external clock (for example, H level) and the connection state of the vibrator 4 (for example, L level), and send the clock control signal 12. . For example, the external clock is supplied to the controller 1 when the setting port 3 is at the H level, and the oscillator 4 is connected when the setting port 3 is at the L level. When the setting port 3 is at H level,
An L level signal (a low frequency clock or a signal to stop the clock) is transmitted. In response to the transmission of this L level signal, the system gate array 2
May set the keyboard clock 11 to a low frequency (for example, 1
Low frequency from 0 MHz to 1 MHz, sleep mode), stop (stop mode).

The resistor R1 is a resistor for pulling down the setting port 3, is held at the L level, is connected to the oscillator 4, and is set to use the internal clock.

The resistor R2 is a resistor that pulls up the setting port 3 and holds the H level to set that the external clock is used. The system gate array 2 includes a keyboard clock 11 for the controller 1.
The keyboard clock 11 is set to a low frequency or stopped in response to the L-bell clock control signal 12 from the controller 1 to save power in the controller 1. .

The oscillator 4 is a crystal oscillator or the like which is connected to the controller 1 and generates an internal clock. Oscillator 5
Is a crystal oscillator or the like which is connected to the system gate array 2 and generates an external clock (keyboard clock 11).

The external clock flag 6 is used by the controller 1
Is a flag for storing that an external clock is used.
The internal clock flag 7 is a flag that stores that the controller 1 uses the internal clock.

The keyboard clock 11 is a clock generated by the system gate array 2 and supplied to the controller 1. The keyboard clock 11 is set such that the controller 1 sets the level of the setting port 3 to, for example, the L level so that the system gate array 2 stops or stops the low frequency clock.

The clock control signal 12 is supplied to the controller 1
Is a signal to be sent to the system gate array 2, and is a signal for setting the keyboard clock 11 to a low frequency or stopping it.

The keyboard data 13 is data in which the controller (keyboard) 1 scans a matrix-shaped keyboard (not shown) to detect a pressed key.
The keyboard reset 14 is a signal for resetting the controller 1.

Next, the operation will be described. (1) Operation by internal clock of FIG. 1 (a): (1-1) As shown in the figure, the resistor R1 is connected to the setting port 3 of the controller 1 to set it to the L level and the oscillator 4 is connected. . A signal line for transmitting keyboard data 13 and keyboard reset 14 is connected between the controller 1 and the system gate array 2.

(1-2) The keyboard reset 14 of the controller 1 is turned on to reset. The reset controller 1 recognizes that the setting port 3 detects the L level here, the oscillator 4 is connected, and operates using the internal clock.

(1-3) The controller 1 uses (1-
Since it is recognized in 2) that the internal clock is used, the clock generated by the oscillator 4 is used for operation. (1-4) The controller 1 saves power by switching the clock to a low frequency or stopping the clock as necessary.

(1-5) When an interrupt is notified during power saving, the clock is restored and the operation is resumed. As described above, by setting the setting port 3 to the L level here, the controller 1 automatically recognizes the internal clock and uses the clock from the oscillator 4 directly connected to save power. Becomes

(2) Operation by external clock of FIG. 1 (b): (2-1) As shown in the figure, the resistor R2 is connected to the setting port 3 of the controller 1 to set it to the H level and the system gate array A signal line for transmitting the keyboard clock 11 and the clock control signal 12 is connected between the two.

(2-2) The keyboard reset 14 of the controller 1 is turned on to reset. The reset controller 1 detects that the setting port 3 is at H level, is connected to the keyboard clock 11, and recognizes that it operates by using the external clock.

(2-3) The controller 1 (2-
Since it is recognized in 2) that the external clock is used, the keyboard clock 11 is used for operation. (2-4) The controller 1 sets the clock control signal here to the L level as needed, and causes the system gate array 2 to switch the keyboard clock 11 to a low frequency or stops the clock to save power. .

(2-5) When an interrupt is notified during power saving, the system gate array 2 restores the keyboard clock 11 to its original value. As described above, by setting the setting port 3 to the H level here, the controller 1 automatically recognizes the external clock and uses the keyboard clock 11 supplied from the system gate array 2 to save power. It will be possible.

Next, the operation of the configuration of FIG. 1 will be described in detail in the order shown in the flowchart of FIG. In FIG. 2, S1 sets the setting port 3 to the input port state. This corresponds to the controller 1 in FIGS. 1 (a) and 1 (b).
Sets the setting port 3 to the input port state in order for the setting port 3 to read either the H level or the L level.

At S2, the state of the setting port 3 is read. This is because the controller 1 reads the setting port 3 from either the H level or the L level. In S3, it is determined whether the H level. In the case of YES, it is determined that it is an external clock at the H level, and this is an example of the operation by the external clock of FIG. 1B, so the process proceeds from S4 to S9. On the other hand, in the case of NO, it is determined that the internal clock is at the L level, and this is an example of the operation by the internal clock of FIG.
The process proceeds from 0 to S15.

In S4, since it is determined that the operation is performed by the external clock with YES in S3, the external clock flag 6 is set to ON and the operation is stored by the external clock. At this time, the internal clock flag 7 is set to OFF.

In step S5, it is determined whether the mode is the power saving mode. For example, it is determined whether there is a key input indicating that the power saving mode has been input from the keyboard, or whether there has been no key input for a predetermined time or more and there has been a decision to enter the power saving mode. YE
If S, go to S6. If NO, the determination of the power saving mode in S5 is repeated.

In S6, the clock control signal is set to L level. As a result, the controller 1 changes the clock control signal 12 from the H level to the L level and notifies the system gate array 2 of the power saving mode.

In step S7, the sleep / stop mode is set. This causes the system gate array 2 which has received the clock control signal of L level in S6 to set the sleep mode in which the frequency of the keyboard clock 11 is set to a low frequency or the stop mode in which the keyboard clock 11 is stopped. As a result, the controller 1 uses the clock (keyboard clock) at a low frequency (for example, 10 MHz to 1 M).
Hz) or the clock is stopped to save power.

At S8, an interrupt occurs. This is S7
In the sleep / stop state of 1, the interrupt is input to the controller 1 and the system gate array 2. S9
In the interrupt of S8, sets the clock control signal to the H level, restores the original clock (keyboard clock 11), and starts the operation.

As described above, when the external clock is used when the setting port 3 is at the H level, the controller 1 automatically recognizes the clock control signal at the L level to save power, and the clock can be restored to the original clock by an interrupt. Becomes

In S10, since the operation of the internal clock is found to be NO in S3, the internal clock flag 7 is set to ON and the operation of the internal clock is stored. At this time, the external clock flag 6 is set to OFF.

In step S11, it is determined whether the mode is the power saving mode. For example, it is determined whether there is a key input indicating that the power saving mode has been input from the keyboard, or whether there has been no key input for a predetermined time or more and there has been a decision to enter the power saving mode. YE
In the case of S, the process proceeds to S12. If NO, S11
The determination as to whether or not the power saving mode is repeated.

In S12, the vibrator 4 is stopped.
In this case, the controller 1 stops the generation of the clock by the vibrator 4 or makes the frequency low. In S13, the sleep / stop mode is set. This corresponds to the sleep / stop mode in response to the low frequency or stopping of the clock generated by the oscillator 4 in S12.

At S14, an interrupt occurs. This is S
In the sleep / stop state of 13, the interrupt is input to the controller 1 and the system gate array 2. S
In the interrupt of S14, 15 restores the internal clock generated by the oscillator 4 to start the operation.

As described above, when the internal clock is used when the setting port 3 is at the L level, the controller 1 automatically recognizes it and at the same time lowers the frequency of the clock by the oscillator 4 to stop the power to save power, and restores the original clock. It is possible to put it back.

FIG. 3 shows a time chart of the present invention.
FIG. 3A shows the case of the internal clock and shows a time chart of the circuit configuration of FIG.

In FIG. 3A, keyboard reset is a signal for resetting the controller 1. As for the setting port / clock control signal, the controller 1 reads the H level / L level from the setting port 3,
It also sends an L level clock control signal.

The oscillator is the oscillator 4 for generating an internal clock. In the setting port check, after the controller 1 is reset by a keyboard reset, the controller 1 recognizes the state of the setting port 3, here, the L level (to use the internal clock).

The sleep / stop mode is S in FIG.
Since the power saving mode is instructed by YES in 11, the clock by the vibrator 4 is stopped at a low frequency or the sleep / sleep mode is set.
Transition to stop mode.

As for the interruption, in the sleep / stop mode, the interruption is generated in the controller 1 and the clock of the oscillator 4 is returned to the original state. FIG. 3B shows a time chart of the circuit configuration of FIG. 1B in the case of an external clock.

In FIG. 3B, 'keyboard reset is a signal for resetting the controller 1. 'Set port / clock control signal is controller 1
To read the H level / L level from the setting port 3 and to send the L level clock control signal.

The keyboard clock is an external clock supplied from the system gate array 2 to the controller 1. 'Checking the set port' recognizes the state of the'set port 3 ', that is, the H level here (external clock is used), after the controller 1 is reset by the keyboard reset.

In the sleep / stop mode, since the power saving mode is instructed by YES in S5 of FIG. 2, the keyboard clock 11 by the system gate array 2 is stopped at a low frequency or the sleep / stop mode is entered.

The interrupt causes the system gate array 2 and the controller 1 to be interrupted in the sleep / stop mode, and restores the keyboard clock 11 by the system gate array 2.

[0052]

As described above, according to the present invention,
The setting port 3 is provided in the controller 1 that operates with a clock, and the setting port 3 receives the external clock input state (for example, H
Level), an external clock is taken in and used to operate, and power is saved in response to the low frequency or stoppage of the external clock, while the setting port 3 causes the oscillator 4 to operate.
In the connected state (for example, L level), the clock from the oscillator 4 is taken in and operated by using the clock, and the low frequency or stop of the internal clock is adopted to save power. Controller 1 that operates with clock
In order to save power, the sleep / stop of the external clock and the internal clock can be shared with a simple configuration. Thus, for example, the controller 1 of the present invention can be applied to both a system in which the clock for the keyboard controller is an external clock and a system in which the clock is an internal clock, and it is not necessary to develop the controller 1 for each system. At this time, since the setting port 3 for discriminating the external clock from the internal clock and the signal line for transmitting the clock control signal for stopping / stopping the low frequency of the external clock at the time of the external clock are shared, the port of the controller 1 ( Signal lines) can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart explaining the operation of the present invention.

FIG. 3 is a time chart of the present invention.

FIG. 4 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 1: Controller 2: System gate array 3: Setting port 4, 5: Oscillator 6: External clock flag 7: Internal clock flag 11: Keyboard clock 12: Clock control signal 13: Keyboard data 14: Keyboard reset

Claims (3)

[Claims] 1. A clock control system for controlling a clock of a controller, wherein a setting port (3) for setting an input state of an external clock or a connection state of an oscillator (4) is provided in a clock-operated controller (1). , When the setting port (3) is in the input state (for example, H level) of the external clock, it takes in the external clock and operates by using it, and saves power in response to the low frequency or stop of the external clock. On the other hand, when the setting port (3) is in the connection state (for example, L level) of the oscillator (4), the clock is fetched from the oscillator (4) and the clock is used to operate to lower the internal clock. A clock control method characterized by being configured to save power by stopping the frequency or stopping. 2. When the setting port (3) is in the input state (for example, H level) of the external clock, the external clock is fetched and operated by using the external clock, and the low frequency clock is output from the setting port (3). Alternatively, the circuit that sends the signal to stop the clock and receives this signal is the controller (1).
2. The clock control system according to claim 1, wherein the clock sent to the device is configured to save power by stopping at a low frequency or stopped. 3. The clock control system according to claim 1 or 2, wherein the controller (1) is composed of a CMOS.