JPH0668694A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To surely relieve a defective part by connecting a power line connected to every row or column of a memory cell to a common power line through the serial connection of a switch which executes opening and closing according to specified information and a fuse. CONSTITUTION:A power line 23 corresponding to each row of a memory cell 10 is connected to a main power line 26 through a fuse 25 and a transistor 24 switched by prescribed timing. The prescribed data are written in the respective memory cells 10 with the voltage VA of the power line. At this time, a voltage Vx is not applied on a control circuit 30 and the transistor 24 is turned on. After writing data, the voltage Vx is applied so as to turn off the transistor 24 and the line 23 is temporally made to be a floating state. Next, the transistor 24 is again made to turn on, data in the cell 10 are read and a defective cell is decided by comparing with the written data. The line 23 corresponding to the defective cell is cut off by the fuse 25. Consequently, the leakage current is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundancy means capable of repairing a defective portion.

[0002]

2. Description of the Related Art Conventional static RAM (SRA
The memory cell of M) is a complete CM consisting of 6 transistors.
There are two types, an OS type and a high resistance load type composed of 4 transistors and 2 resistors. Of these, the complete CMOS type cell has a flip-flop configuration in which a pair of CMOS inverters are cross-coupled, and is superior to the high resistance load type cell in terms of storage stability and power consumption in a stationary state. There is.

FIG. 6 is a circuit diagram showing the structure of a complete CMOS type cell. The memory cell 10 includes a pair of CMOS inverters 1 and 2 and two access transistors 3 and 4. The output of the CMOS inverter 1 is connected to the input of the CMOS inverter 2, and the output of the CMOS inverter 2 is the output of the CMOS inverter 1. A bistable flip-flop is formed by being connected to the input. These CMOs
The respective outputs of the S inverters 1 and 2 are connected to a pair of bit lines 6 via the access transistors 3 and 4 having the word line 5 as a gate input, whereby the memory cell 10 and the bit are connected through the access transistors 3 and 4. Line 6
Read and write data transfer is performed between and. As shown in FIG. 7, a plurality of memory cells 10 are arranged in rows and columns, and word lines 5 and bit lines 6 are provided so as to correspond to the respective rows and columns. A power supply line 7 for supplying power to the memory cell 10 is arranged corresponding to each row of the memory cell 10, and a main power supply line 8 connected to each power supply line 7 is arranged in the peripheral portion of the memory cell 10. It The above plurality of word lines 5 and bit lines 6 are selectively activated based on the designation of address data, and are configured to select the memory cell 10 at a specific address.

By the way, as the capacity and integration of the device are increased, the probability of occurrence of a defective portion becomes high, and therefore a redundant means for relieving the defective portion is indispensable. This redundant means includes a spare memory cell having the same structure as the original memory cell, and a bit line and a word line connected to this spare memory cell. The generated bit line or word line is inactivated and at the same time the spare bit line or word line is activated. A memory device having such redundancy means is disclosed in, for example, Japanese Patent Laid-Open No. 63-235.
It is proposed in Japanese Patent No.

FIG. 8 is a circuit diagram showing a redundant circuit portion of a conventional memory device. The selection circuits 11a and 11b, to which the address data A1 and A2 are applied, include a fuse 12, an inverter 13, and two MOS transistors 14 and 15.
Selection transistors 16a, 1 connected to the bit lines 6a, 6b based on the address data A1, A2.
6b is alternatively turned on to connect the bit lines 6a and 6b to the data line 17. The address data A1 and A2 given to the selection circuits 11a and 11b are given to the input of the inverter 13 through the fuse 12, and the inverter 13
Is connected to the gates of the selection transistors 16a and 16b connected to the bit lines 6a and 6b. Further, the output of the inverter 13 is passed through the MOS transistor 15 whose gate inputs are the address data A1 and A2, and is also passed through the inverter 18 to the gate of the selection transistor 20 connected to the bit line 19 corresponding to the spare memory cell. Connected. A power supply voltage is applied to the input side of the inverter 13 through a MOS transistor 14 having a ground voltage as a gate input, and the input voltage of the inverter 13 is fixed when the fuse 12 is blown.

Therefore, when the fuse 12 is blown, the input of the inverter 13 is fixed to the low level and the selection transistor 16 connected to the bit lines 6a and 6b.
Since a and 16b remain off, the bit line 6
Instead of a and 6b, the selection transistor 20 connected to the spare bit line 19 is turned on and the spare bit line 19 is connected to the data line 17 and activated. still,
When the fuse 12 is in the entangled state, the output of the inverter 13 is directly output to the selection transistors 16a and 16b.
And the predetermined bit lines 6a and 6b are applied to the data line 17
Is connected to and activated.

In the memory device provided with the redundant circuit as described above, when the defective portion is detected, the bit lines 6a and 6b (in some cases, the word line 5) are replaced by the spare bit line 19 (word line). By replacing the memory cell 10 in one column or row in which the defective portion exists with a spare memory cell, the defective portion is relieved. That is, when a defective portion is detected by a function test in which writing and reading of data are repeated with respect to each memory cell 10 and the fuse 12 is blown corresponding to the address of the defective portion, the bit line of that address is cut. At the same time that 6a and 6b are fixed to the inactive state, the bit line 19 connected to the spare memory cell is selectively replaced.

[0008]

However, when a leak occurs due to insulation failure or the like, even if the defective bit lines 6a and 6b are fixed in an inactive state, a leak current from the power supply line 5 to the memory cell 10 is generated. May flow, and this leakage current may cause a defect. That is, in the complete CMOS type in which almost no current flows when each memory cell 10 is in the stopped state (standby state), if a slight current flows in the stopped state, it is determined that the standby current is defective in the function test. Because
Although the defective portion is repaired by the redundant circuit, the result of the test does not become a non-defective product, resulting in a decrease in yield.

Therefore, it is an object of the present invention to reliably repair a defective portion when the defective portion is replaced by a redundant circuit.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a first feature in that a pair of CMOS inverter circuits are connected in a flip-flop configuration. A static memory cell in which a plurality of selection transistors are connected to the output side of the inverter circuit, and a plurality of memory cells are arranged in a matrix, and a plurality of first signals connected to the selection transistors in association with each column of the memory cell Lines, a plurality of second signal lines associated with each row of the memory cells and connected to the gates of the selection transistors, and connected to the power supply side of the inverter circuit for each row or column of the memory cells. A semiconductor memory device comprising: a plurality of first power lines; and at least one second power line to which the plurality of first power lines are commonly connected The first power line is connected to the second power line through a first switch element that opens and closes according to specific information and a second switch element that can be disconnected by physical means in series. .

A second characteristic is that in the semiconductor memory device, the first power line has the rectifier element in the reverse direction and the switch element which can be disconnected by a physical means in series and the second power line. It is connected to the power line.

[0012]

According to the present invention, a memory cell having a defective portion is formed by cutting the first switch element (fuse) connected between the first power line and the second power line as necessary. The supply of the voltage to the memory cell is stopped, and the current flowing from the power line to the memory cell disappears when the memory cell is in the stopped state.

Further, the first switch element or the rectifying element is connected in series with the second switch element, and a predetermined voltage is once supplied from the second power line to the first power line and then the second switch element is rectified.
When the supply of the potential from the power line is stopped, and the leak current flows in the memory cell, the potential of the first power line corresponding to the memory cell decreases, so that the presence or absence of a defective portion is detected from the decrease in the potential. To be done.

[0014]

1 is a circuit diagram showing a main part of a semiconductor memory device according to the present invention. In this figure, the memory cell 10 is of the complete CMOS type and is the same as FIG. A pair of bit lines 21 is associated with each column of the memory cells 10 arranged in rows and columns.
The outputs of the inverters 1 and 2 are connected to the memory cell 10
Each row is associated with a word line 22 and connected to the gates of the access transistors 3 and 4 of the memory cell 10. In addition, a power supply line 2 that is a power supply for each memory cell
3 are arranged corresponding to each row of the memory cells 10, and the power supply lines 23 are connected to the inverters 1 and 2 of the memory cells 10, respectively. The power supply line 23 is connected to the main power supply line 26 via a switch transistor 24 that performs a switch operation at a predetermined timing and a fuse 25 that is cut according to the result of an operation test. Therefore, the voltage V _A of the main power supply line 26 is applied to each memory cell 10 through the power supply line 23 while the transistor 24 is on.

A control circuit for controlling the operation of the transistor 24.
Path 30 has its drain grounded and, if necessary, its source
Power supply voltage level voltage V_XMOS transistor that is given
A star 31 and a transistor connected in parallel with the transistor 31.
Receives the source potentials of the capacitor 32 and the transistor 31.
An inverter 33 and an input receiving the output of the inverter 33
It consists of a converter 34, and the source of the transistor 31 (in
Voltage V to the input of the barter 33)_XWith or without
Configured to turn transistor 24 on or off
Be done. That is, the voltage V_XIs not applied, the
Output of transistor 34 is fixed to low level and transistor 2
4 is turned on, the voltage V _XIs applied
And the output of the inverter 34 is fixed at high level.
The transistor 24 is turned off.

In the above memory device, when a defective portion is detected by a predetermined operation test, the fuse 25 corresponding to the defective portion is blown and the voltage supply to the defective portion is cut off. Subsequently, a method of detecting a defective portion will be described. First, as shown in FIG.
Voltage V _A of each memory cell 10 is raised to the power supply voltage.
Write predetermined data to. At this time, the voltage V _X is not applied to the control circuit 30, and the transistor 24 is on. After the data writing to the memory cell 10 is completed, the voltage V _X is applied to the control circuit 30 to turn off the transistor 24, and the power lines 23 are temporarily set in the floating state. Then, the application of the voltage V _X to the control circuit 30 is stopped, the transistor 24 is turned on again, and the data previously written in each memory cell 10 is read. Therefore, the quality of the memory cell 10 is judged by comparing the read data with the written data. Once the power supply line 23 is brought into a floating state, in the normal memory cell 10, the written data is held as it is because the voltage V _B of the power supply line 23 is kept substantially constant as shown by the broken line in FIG. As for the memory cell 10 through which the leak current flows, as shown by the solid line in FIG. 2, since the voltage V _B of the power line 23 cannot be maintained and the data written in the memory cell 10 cannot be held,
If the read data is different from the written data, it is determined that there is a defective portion. Therefore, according to the judgment result,
For the memory cell 10 that is determined to have a defective portion, the fuse 25 corresponding to that row is blown and the supply of voltage to the power supply line 23 is cut off. There is no current flowing in.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. In this figure, the memory cell 10 and the bit line 21 and word line 22 associated therewith have the same configuration as in FIG. The feature here is that the power supply line 23 arranged corresponding to each row of the memory cells 10
Are connected to the main power supply line 26 via the diode 27 and the fuse 28, respectively. That is, by connecting the diode 27 in series with the fuse 28 and connecting from the main power supply line 26 in the direction of the power supply line 23, the power supply line 2 is reduced when the voltage V _A of the main power supply line 26 is lowered.
It is possible to prevent the voltage V _{B of} 3 from decreasing at the same time. Therefore, when the voltage V _A of the main power supply line 26 is lowered from the power supply voltage to the ground voltage, the diode 27 is reversely biased, so that the power supply line 23 is temporarily in a floating state.

Therefore, as shown in FIG. 4, after writing predetermined data in each memory cell 10, the main power supply line 2
The voltage V _A of 7 is once lowered to the ground voltage, the voltage V _A is again raised to the power supply voltage, the data of each memory cell 10 is read, and the read data and the previously written data are compared to each memory. It is possible to determine the presence / absence of a leak current in the cell 10. Also in this case, as in the case of FIG. 1, when the leak current flows in the memory cell 10 when the power supply line 23 once becomes the floating state, the voltage V _B of the power supply line 23 decreases as shown by the solid line in FIG. Then, since the data written in the memory cell 10 is no longer held, the read data does not match the written data, and it can be determined that there is a defective portion. Then, when the fuse 28 corresponding to the memory cell 10 determined to have the leakage current is blown,
The supply of voltage from the main power supply line 26 to the power supply line 23 is stopped.

By the way, the power supply line 2 as shown in FIG.
In case of 3, the voltage V of the power supply line 23 _BIs the main power line 2
6 voltage V_AFor the threshold voltage of diode 27
Since the voltage becomes low, the voltage supplied to each memory cell 10
May run short. Therefore, as shown in FIG.
Switch transistor 29 that works as a bypass
The power line 23 is connected in parallel to the
The transistor 29 is turned on only when the
If it is turned off, the voltage of the diode 27
Can prevent lowering. It controls the operation of this transistor 29.
The control circuit 30 shown in FIG. 1 is used as a circuit for
It is possible to connect the first power line 23 to the float
The voltage V is applied to the control circuit 30 during the period of the switching state._Xgive
To do so.

In the above embodiments, the case where the power supply line is arranged along each row of the memory cell 10 has been illustrated, but the case where the power supply line is arranged along each column of the memory cell 10 is similar. Then, the supply of voltage to each power supply line can be stopped.

[0021]

According to the present invention, by stopping the supply of the voltage to the defective portion, almost no current flows when the memory cell is in the stopped state even if there is a leak at the defective portion, and the operation test is performed. At that time, the standby current is not determined to be defective. Therefore, when the defective portion is relieved by various redundant means, the defective portion can be surely eliminated, and the reduction of the manufacturing yield can be prevented.

Further, since an address having a defective portion can be easily detected during the operation test, the throughput of the operation test is increased and the productivity can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a timing diagram illustrating an operation of the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram of another embodiment of the semiconductor memory device of the present invention.

FIG. 4 is a timing diagram illustrating an operation of the semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a static RAM.

FIG. 7 is a circuit diagram of a conventional semiconductor memory device.

FIG. 8 is a circuit diagram of a redundant circuit used in a conventional semiconductor memory device.

[Explanation of symbols]

 1, 2 CMOS inverter 3, 4 Access transistor 5, 22 Word line 6, 21 Bit line 7, 23 Power supply line 8, 26 Main power supply line 10 Memory cell 11 Selection circuit 12, 25, 28 Fuse 13, 33, 34 Inverter 14 , 15, 31 MOS transistors 16a, 16b, 20 Selection transistor 17 Data line 19 Spare bit line 24, 29 Switch transistor 27 Diode 30 Control circuit

Claims (6)

[Claims] 1. A static type memory cell in which a pair of CMOS inverter circuits are connected in a flip-flop configuration and a selection transistor is connected to the output side of each inverter circuit, and a plurality of static memory cells are arranged in a matrix, and each of the memory cells is formed. A plurality of first signal lines associated with columns and connected to the selection transistors, and a plurality of second signal lines associated with each row of the memory cells and connected to gates of the selection transistors; A plurality of first power lines connected to the power source side of the inverter circuit for each row or column of the memory cells, and at least one second power line commonly connected to the plurality of first power lines; Equipped with
The first power line is opened and closed according to specific information.
2. A semiconductor memory device characterized in that the switch element and the second switch element which can be disconnected by a physical means are connected in series to the second power line. 2. A predetermined voltage is applied to the first power line from the second power line to close the first switch element, and then the first power line is changed in response to a change in each voltage of the first power line. 2. The semiconductor memory device according to claim 1, wherein the two switch elements are selectively cut off. 3. A static memory cell in which a pair of CMOS inverter circuits are connected in a flip-flop configuration and a selection transistor is connected to the output side of each inverter circuit, and a plurality of static memory cells are arranged in rows and columns, and each of these memory cells. A plurality of first signal lines associated with columns and connected to the selection transistors, and a plurality of second signal lines associated with each row of the memory cells and connected to gates of the selection transistors; A plurality of first power lines connected to the power source side of the inverter circuit for each row or column of the memory cells, and at least one second power line commonly connected to the plurality of first power lines; Equipped with
The first power line is configured such that the rectifying element in the opposite direction and the switch element that can be disconnected by physical means are connected in series to the second power line.
A semiconductor memory device characterized in that it is connected to the power line. 4. The switch element is temporarily supplied with a predetermined voltage from the second power line and then the supply of the voltage is stopped, and the switch element is responsive to each potential fluctuation of the first power line. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is selectively disconnected. 5. The second rectifying element between the first power line and the second power line is connected in parallel with a second switch element that opens and closes according to specific information. 3. The semiconductor memory device according to item 3. 6. The semiconductor memory device according to claim 5, wherein the second switch element is opened during a period in which a predetermined voltage is supplied from the second power line to the first power line.