JPH0669331A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0669331A JPH0669331A JP21593192A JP21593192A JPH0669331A JP H0669331 A JPH0669331 A JP H0669331A JP 21593192 A JP21593192 A JP 21593192A JP 21593192 A JP21593192 A JP 21593192A JP H0669331 A JPH0669331 A JP H0669331A
- Authority
- JP
- Japan
- Prior art keywords
- region
- single crystal
- wiring
- semiconductor single
- breakdown voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000013078 crystal Substances 0.000 claims abstract description 26
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000926 separation method Methods 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000005498 polishing Methods 0.000 abstract description 3
- 230000008719 thickening Effects 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、絶縁層分離基板を用い
た高耐圧の半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device using an insulating layer separation substrate.
【０００２】[0002]
【従来の技術】図３は、誘電体分離基板を利用した集積
回路内の一つの半導体単結晶領域に形成された高耐圧素
子の断面図を示している。端子間に高電圧がかかった場
合、高耐圧素子から他の素子への配線（図３のアノード
電極１１）によって側面に形成された高不純物領域の境
界部１４に電界が集中してしまい、本来の高耐圧素子の
耐圧より大きく低下してしまう。尚、１２は電極であ
る。2. Description of the Related Art FIG. 3 is a sectional view of a high breakdown voltage element formed in one semiconductor single crystal region in an integrated circuit using a dielectric isolation substrate. When a high voltage is applied between the terminals, the electric field concentrates on the boundary portion 14 of the high impurity region formed on the side surface by the wiring (the anode electrode 11 in FIG. 3) from the high breakdown voltage element to another element, and originally Of the high withstand voltage element. In addition, 12 is an electrode.
【０００３】従来、この配線による耐圧の低下を減らす
ために、配線下の酸化膜厚１３を厚くし、配線の影響を
小さくしていた。Conventionally, in order to reduce the decrease in breakdown voltage due to the wiring, the oxide film thickness 13 under the wiring is made thick to reduce the influence of the wiring.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
方法では、酸化膜厚１３を厚くする必要があり、新しく
工程開発が必要である。また、段差が大きくなるので、
配線の断線の危険性が大きくなるという問題があった。
本発明は上述の点に鑑みて提供したものであって、配線
下の酸化膜厚を厚くすることなく、素子の耐圧低下を小
さくすることを目的とした半導体装置を提供するもので
ある。However, in the conventional method, it is necessary to increase the oxide film thickness 13 and new process development is required. Also, since the step becomes large,
There is a problem that the risk of wire breakage increases.
The present invention has been made in view of the above points, and provides a semiconductor device for reducing the breakdown voltage of an element without increasing the oxide film thickness under the wiring.
【０００５】[0005]
【課題を解決するための手段】本発明は、支持体層上に
絶縁層で電気的に分離された半導体単結晶領域が複数設
けられ、上記半導体単結晶領域の底面及び側面部に半導
体単結晶領域と同種で濃度の高い不純物領域を有する絶
縁層分離基板上の素子において、半導体単結晶領域の端
部に該半導体単結晶領域と同種で濃度の高い不純物領域
を設けたものである。According to the present invention, a plurality of semiconductor single crystal regions electrically isolated by an insulating layer are provided on a support layer, and the semiconductor single crystal region is provided on the bottom surface and side surface portion of the semiconductor single crystal region. In an element on an insulating layer separation substrate having an impurity region of the same type as the region and having a high concentration, an impurity region of the same type as the semiconductor single crystal region and having a high concentration is provided at an end of the semiconductor single crystal region.
【０００６】[0006]
【作用】而して、配線下の酸化膜厚を厚くすることな
く、素子の耐圧低下を小さくすることができる。Therefore, it is possible to reduce the breakdown voltage of the device without increasing the oxide film thickness under the wiring.
【０００７】[0007]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図２（ａ）に示すように、ｎ- 型シリコン単結晶
ウエハ１上に、ＳｉＯ2 ２を形成し、パターニング後、
上記ＳｉＯ2 ２をエッチングし、シリコン単結晶部を異
方性エッチングする。次に、図２（ｂ）に示すように、
表面に残ったＳｉＯ2 ２をエッチング後、ｎ形不純物３
を表面より拡散する。さらに、図２（ｃ）に示すよう
に、絶縁層４を形成後、支持体層５を形成する。Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 2A, after SiO 2 2 is formed on the n − type silicon single crystal wafer 1 and patterned,
The SiO 2 2 is etched, and the silicon single crystal portion is anisotropically etched. Next, as shown in FIG.
After etching SiO 2 2 remaining on the surface, n-type impurities 3
Diffuse from the surface. Further, as shown in FIG. 2C, after forming the insulating layer 4, the support layer 5 is formed.
【０００８】その後、図２（ｄ）に示すように、シリコ
ン単結晶ウエハ１側から、絶縁層４が現れるまで研磨を
行い、通常の誘電体分離基板６ができる。この誘電体分
離基板６上に図１に示すような素子を形成する。シリコ
ン単結晶ウエハ１が研磨されて形成された単結晶島領域
７内にダイオードのアノードとなるＰ領域９、カソード
となるｎ+ 領域１０、それぞれの電極１１，１２に加え
て本発明であるｎ領域（不純物領域）８をアノードの配
線（電極１１）の下部に図１に示すように構成する。
尚、１３は酸化膜厚である。After that, as shown in FIG. 2D, polishing is performed from the silicon single crystal wafer 1 side until the insulating layer 4 appears, whereby a normal dielectric isolation substrate 6 is formed. An element as shown in FIG. 1 is formed on this dielectric isolation substrate 6. In addition to the P region 9 serving as the anode of the diode, the n + region 10 serving as the cathode, and the respective electrodes 11 and 12 in the single crystal island region 7 formed by polishing the silicon single crystal wafer 1, the present invention includes n. A region (impurity region) 8 is formed below the anode wiring (electrode 11) as shown in FIG.
Incidentally, 13 is an oxide film thickness.
【０００９】このｎ領域８は、ＭＯＳトランジスタのた
めのウエルと同程度の濃度でも良いので、ウエルと同時
に形成しても構わない。このような構成とすることによ
り、配線（電極１１）の下の電界がｎ領域８の部分で分
散され、配線（電極１１）による電界集中のために引き
起こされる耐圧低下を低く抑えることができる。The n region 8 may have the same concentration as that of the well for the MOS transistor, and therefore may be formed simultaneously with the well. With such a configuration, the electric field under the wiring (electrode 11) is dispersed in the n region 8 and the decrease in breakdown voltage caused by the electric field concentration by the wiring (electrode 11) can be suppressed low.
【００１０】また、単結晶島領域７内に形成される素子
はダイオード以外のトランジスタ等でも構わない。ま
た、単結晶島領域７がｐ型ならばｎ領域８をｐ型とすれ
ば、同様のものが得られる。The element formed in the single crystal island region 7 may be a transistor other than a diode or the like. If the single crystal island region 7 is p-type and the n region 8 is p-type, the same result can be obtained.
【００１１】[0011]
【発明の効果】本発明は上述のように、支持体層上に絶
縁層で電気的に分離された半導体単結晶領域が複数設け
られ、上記半導体単結晶領域の底面及び側面部に半導体
単結晶領域と同種で濃度の高い不純物領域を有する絶縁
層分離基板上の素子において、半導体単結晶領域の端部
に該半導体単結晶領域と同種で濃度の高い不純物領域を
設けたものであるから、配線下の酸化膜厚を厚くするこ
となく、素子の耐圧低下を小さくすることができる効果
を奏するものである。As described above, according to the present invention, a plurality of semiconductor single crystal regions electrically isolated by an insulating layer are provided on a support layer, and the semiconductor single crystal regions are provided on the bottom surface and side surface portion of the semiconductor single crystal region. In an element on an insulating layer separation substrate having an impurity region of the same type as the region and having a high concentration, an impurity region of the same type as the semiconductor single crystal region and having a high concentration is provided at the end of the semiconductor single crystal region. It is possible to reduce the breakdown voltage of the device without increasing the thickness of the underlying oxide film.
【図１】本発明の半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.
【図２】同上の半導体装置を形成する場合の工程を示す
図である。FIG. 2 is a diagram showing a step in the case of forming the semiconductor device of the same.
【図３】従来例の半導体装置の断面図である。FIG. 3 is a sectional view of a conventional semiconductor device.
１ シリコン単結晶ウエハ ２ ＳｉＯ2 ３ ｎ形不純物 ４ 絶縁層 ５ 支持体層 ６ 誘電体分離基板 ７ 単結晶島領域 ８ ｎ領域（不純物領域） １１ 電極 １３ 酸化膜厚1 Silicon Single Crystal Wafer 2 SiO 2 3 n-type Impurity 4 Insulating Layer 5 Support Layer 6 Dielectric Separation Substrate 7 Single Crystal Island Region 8 n Region (Impurity Region) 11 Electrode 13 Oxide Thickness
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ▲松▼本 多津彦 大阪府門真市大字門真1048番地松下電工株 式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Matsu ▼ Tatsuhiko Moto 1048, Kadoma, Kadoma-shi, Osaka Matsushita Electric Works Co., Ltd.
Claims (1)
た半導体単結晶領域が複数設けられ、上記半導体単結晶
領域の底面及び側面部に半導体単結晶領域と同種で濃度
の高い不純物領域を有する絶縁層分離基板上の素子にお
いて、半導体単結晶領域の端部に該半導体単結晶領域と
同種で濃度の高い不純物領域を設けたことを特徴とする
半導体装置。1. A plurality of semiconductor single crystal regions electrically isolated by an insulating layer are provided on a support layer, and impurities having the same type and a high concentration as the semiconductor single crystal region are provided on the bottom surface and side surfaces of the semiconductor single crystal region. A semiconductor device having an element on an insulating layer separation substrate having a region, wherein an impurity region of the same kind as the semiconductor single crystal region and having a high concentration is provided at an end of the semiconductor single crystal region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21593192A JPH0669331A (en) | 1992-08-13 | 1992-08-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21593192A JPH0669331A (en) | 1992-08-13 | 1992-08-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0669331A true JPH0669331A (en) | 1994-03-11 |
Family
ID=16680635
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21593192A Withdrawn JPH0669331A (en) | 1992-08-13 | 1992-08-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669331A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7296561B2 (en) | 2004-12-27 | 2007-11-20 | Nissan Motor Co., Ltd. | Engine control apparatus |
-
1992
- 1992-08-13 JP JP21593192A patent/JPH0669331A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7296561B2 (en) | 2004-12-27 | 2007-11-20 | Nissan Motor Co., Ltd. | Engine control apparatus |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991102 |