JPH0669397A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH0669397A
JPH0669397A JP4219864A JP21986492A JPH0669397A JP H0669397 A JPH0669397 A JP H0669397A JP 4219864 A JP4219864 A JP 4219864A JP 21986492 A JP21986492 A JP 21986492A JP H0669397 A JPH0669397 A JP H0669397A
Authority
JP
Japan
Prior art keywords
solder
resin
external
external leads
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4219864A
Other languages
Japanese (ja)
Inventor
Yoichi Tsunoda
洋一 角田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP4219864A priority Critical patent/JPH0669397A/en
Publication of JPH0669397A publication Critical patent/JPH0669397A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】樹脂封止後の半導体装置において、後工程のタ
イバー切断工程,外部リードの付着樹脂除去及び半田め
っき工程を無くすと共に外部リード成形後の外部リード
の変形を防止する。 【構成】外部リード5間の少くとも一部を半田6で埋め
込み、それぞれの外部リード5を半田6で連結すること
により樹脂封止の際の樹脂漏れを防ぐと共に、加熱する
ことで半田6を溶融切断することが可能である為、タイ
バー切断工程及び外部リード5の付着樹脂除去工程が不
要となり、生産性向上及び品質向上ができる。さらに、
半田6への加熱を外部リード5成形工程後に行なうこと
により、半田6が成形時の外部リード5の補強となり、
外部リード5先端の平坦性を向上させ、生産性及び品質
の向上ができる。
(57) [Abstract] [Purpose] In a semiconductor device after resin encapsulation, the post-process tie bar cutting process, the resin removal of the external leads and the solder plating process are eliminated, and the deformation of the external leads after the external leads are molded is prevented. . [Structure] At least a part between external leads 5 is filled with solder 6, and each external lead 5 is connected with solder 6 to prevent resin leakage at the time of resin sealing and to heat solder 6 by heating. Since melt cutting is possible, the tie bar cutting step and the step of removing the resin adhered to the external leads 5 are not required, and productivity and quality can be improved. further,
By heating the solder 6 after the external lead 5 molding step, the solder 6 serves as a reinforcement for the external lead 5 during molding,
The flatness of the tips of the external leads 5 can be improved, and the productivity and quality can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置用リードフレ
ームに関し、特に樹脂封止型の半導体装置に用いられる
半導体装置用リードフレームに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device lead frame, and more particularly to a semiconductor device lead frame used in a resin-sealed semiconductor device.

【0002】[0002]

【従来の技術】図10は従来の半導体装置用リードフレ
ームの一例の平面図、図11は図10の半導体装置用リ
ードフレームを用いた樹脂封止後の平面図、図12は図
11の断面図、図13は図11の外部リードの部分拡大
平面図、図14は図13のタイバー切断後の外部リード
の平面図である。
10 is a plan view of an example of a conventional semiconductor device lead frame, FIG. 11 is a plan view after resin sealing using the semiconductor device lead frame of FIG. 10, and FIG. 12 is a cross section of FIG. 13 is a partially enlarged plan view of the external lead of FIG. 11, and FIG. 14 is a plan view of the external lead of FIG. 13 after cutting the tie bar.

【0003】従来、この種の半導体装置用リードフレー
ムは図10〜図12に示すように、全て同一素材で構成
されており、外部リード5はタイバー12によりそれぞ
れ連結されていた。
Conventionally, as shown in FIGS. 10 to 12, this type of semiconductor device lead frame is made of the same material, and the external leads 5 are connected to each other by tie bars 12.

【0004】樹脂封止後の半導体装置は、その後の工程
にて図13及び図14に示すように、タイバー12がカ
ットされ、続いて、外部リード5の半田めっき工程及び
成形工程を経て完成されていた。
The semiconductor device after resin encapsulation is completed in the subsequent steps, as shown in FIGS. 13 and 14, after the tie bar 12 is cut, and subsequently, the external lead 5 is subjected to a solder plating step and a molding step. Was there.

【0005】この際、タイバーカット工程では外部リー
ド5に部分的に付着樹脂11が付着するため、その後の
半田めっき工程前に付着樹脂11の除去工程を追加する
必要があった。
At this time, since the adhered resin 11 partially adheres to the outer leads 5 in the tie bar cutting step, it is necessary to add a step of removing the adhered resin 11 before the subsequent solder plating step.

【0006】[0006]

【発明が解決しようとする課題】上述した従来のリード
フレームは、その外部リード5の間にタイバー12を有
する構造である為、モールド封止後の工程においてその
タイバー12を切断し、それぞれの外部リード5の間の
電気的導電をカットする必要があった為、品質及び生産
性が低下するという問題点があった。
Since the above-mentioned conventional lead frame has a structure in which the tie bar 12 is provided between the external leads 5, the tie bar 12 is cut in a step after the mold sealing, and each external lead 5 is cut. Since it is necessary to cut the electrical conductivity between the leads 5, there is a problem that the quality and productivity are reduced.

【0007】また、モールド封止時の樹脂が外部リード
5の側面および表面に付着する為、その付着樹脂11を
除去する必要があり除去する工程が必要であると共に生
産性が低下するという問題点があった。
Further, since the resin at the time of mold sealing adheres to the side surface and the surface of the external lead 5, it is necessary to remove the adhered resin 11 and a step of removing the resin 11 is required, and the productivity is lowered. was there.

【0008】さらに、タイバー12切断後に外部リード
5の成形を行なうことにより、外部リード5の強度が低
下しているために、外部リード5成形時に外部リード5
が変形し易く、変形不良を誘発するという問題点があっ
た。
Further, since the strength of the outer lead 5 is lowered by forming the outer lead 5 after cutting the tie bar 12, the outer lead 5 is formed when the outer lead 5 is formed.
However, there is a problem that it is easily deformed and induces deformation failure.

【0009】加えて、従来の技術では外部リード5に半
田めっきを行なう為にめっき工程が必要であると共に生
産性が低下するという問題点があった。
In addition, in the conventional technique, there is a problem that a plating step is required to perform solder plating on the external leads 5 and productivity is reduced.

【0010】本発明の目的は、外部リードの変形不良が
なく、高品質で生産性の高い半導体装置が得られる半導
体装置用リードフレームを提供することにある。
An object of the present invention is to provide a lead frame for a semiconductor device which can obtain a semiconductor device of high quality and high productivity without deformation defects of external leads.

【0011】[0011]

【課題を解決するための手段】本発明は、半導体素子を
搭載するアイランドと、該アイランドの周囲に配置され
た内部リードと、該内部リードに接続する外部リードと
を有する樹脂封止型の半導体装置用リードフレームにお
いて、前記外部リード間の少くとも一部に半田を埋め込
みそれぞれの前記外部リードを前記半田にて連結する。
According to the present invention, there is provided a resin-encapsulated semiconductor having an island on which a semiconductor element is mounted, internal leads arranged around the island, and external leads connected to the internal lead. In a device lead frame, solder is embedded in at least a part between the external leads, and the external leads are connected by the solder.

【0012】[0012]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0013】図1は本発明の第1の実施例の平面図、図
2は図1の第1の実施例を用いた樹脂封止後の平面図、
図3は図2の断面図、図4は図2の外部リードの部分拡
大平面図、図5は図4の半田溶融切断後の外部リードの
平面図である。
FIG. 1 is a plan view of a first embodiment of the present invention, FIG. 2 is a plan view after resin sealing using the first embodiment of FIG.
3 is a sectional view of FIG. 2, FIG. 4 is a partially enlarged plan view of the external lead of FIG. 2, and FIG. 5 is a plan view of the external lead of FIG.

【0014】第1の実施例は、図1〜図5に示すよう
に、外部リード5は半導体装置の樹脂封止部8の外側で
電気的導通を行なう部分であり、その外部リード5の間
の一部に半田6が埋め込まれ、それぞれの外部リード5
間が半田6にて連結されている。外部リード5間に連結
された半田6は、外部リード5間の半田6が樹脂封止の
際に、樹脂封止部8から漏れる樹脂を塞ぎ止める図11
に示す従来の半導体装置でのタイバー12の役割を果た
すことが可能である。さらに、この半田6は熱を受ける
ことにより、図5に示すように、溶融切断可能である。
In the first embodiment, as shown in FIGS. 1 to 5, the external lead 5 is a portion for electrically conducting outside the resin encapsulation portion 8 of the semiconductor device. Solder 6 is embedded in a part of each of the external leads 5
The spaces are connected by solder 6. The solder 6 connected between the external leads 5 blocks the resin leaking from the resin sealing portion 8 when the solder 6 between the external leads 5 is resin-sealed.
It is possible to play the role of the tie bar 12 in the conventional semiconductor device shown in FIG. Further, the solder 6 can be melted and cut by receiving heat as shown in FIG.

【0015】図6は本発明の第2の実施例の平面図、図
7は図6の第2の実施例を用いた樹脂封止後の断面図、
図8は図6の外部リードの部分拡大平面図、図9は図8
の半田溶融切断後の平面図である。
FIG. 6 is a plan view of a second embodiment of the present invention, FIG. 7 is a sectional view after resin sealing using the second embodiment of FIG. 6,
8 is a partially enlarged plan view of the external lead shown in FIG. 6, and FIG. 9 is shown in FIG.
FIG. 6 is a plan view after melting and cutting the solder of FIG.

【0016】第2の実施例は、図6〜図9に示すよう
に、外部リード5間全部に半田6が埋め込まれ、外部リ
ード5間に埋め込まれた半田6は樹脂封止の際の樹脂漏
れを防ぐことが可能である。加えて、半田6は図9に示
すように熱を受けることにより溶融切断されると同時に
外部リード5への半田6のコートを行なうことが可能で
ある。
In the second embodiment, as shown in FIGS. 6 to 9, the solder 6 is embedded in the entire space between the external leads 5, and the solder 6 embedded between the external leads 5 is a resin for resin encapsulation. It is possible to prevent leakage. In addition, the solder 6 can be melted and cut by receiving heat as shown in FIG. 9, and at the same time, the external lead 5 can be coated with the solder 6.

【0017】さらに、上述した半田6は、外部リード5
成形工程での外部リード5の補強を行なうことが可能で
あり、成形後に半田6を溶融切断することで成形後のそ
れぞれの外部リード5を分離できる。
Further, the above-mentioned solder 6 is the external lead 5
It is possible to reinforce the external leads 5 in the molding step, and by melting and cutting the solder 6 after molding, the respective external leads 5 after molding can be separated.

【0018】[0018]

【発明の効果】以上説明したように本発明は、樹脂封止
型の半導体装置用リードフレームにおいて、外部リード
間の少くとも一部に半田を埋め込みそれぞれの外部リー
ドを連結している為、従来リードフレームのタイバーが
行なっていた樹脂封止の際の樹脂漏れを防ぐことが可能
である。この半田は熱を受けることにより溶融切断可能
である為、樹脂封止後のタイバー切断工程及びタイバー
切断時に生じる付着樹脂の除去工程が不要となり、生産
性ならびに品質を向上できる効果がある。
As described above, according to the present invention, in the resin-encapsulated lead frame for a semiconductor device, solder is embedded in at least a part between the external leads to connect the respective external leads. It is possible to prevent resin leakage during resin sealing performed by the tie bar of the lead frame. Since this solder can be melted and cut by receiving heat, the step of cutting the tie bar after resin sealing and the step of removing the adhered resin generated at the time of cutting the tie bar are unnecessary, and there is an effect that productivity and quality can be improved.

【0019】尚、熱を与える工程は、樹脂封止後から外
部リード成形後の任意の工程に設置できる柔軟性を有し
ている。
The step of applying heat has the flexibility that it can be installed in any step after resin molding and after external lead molding.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例の平面図である。FIG. 1 is a plan view of a first embodiment of the present invention.

【図2】図1の第1の実施例を用いた樹脂封止後の平面
図である。
FIG. 2 is a plan view after resin sealing using the first embodiment of FIG.

【図3】図2の断面図である。3 is a cross-sectional view of FIG.

【図4】図2の外部リードの部分拡大平面図である。4 is a partially enlarged plan view of the external lead shown in FIG.

【図5】図4の半田溶融切断後の外部リードの平面図で
ある。
5 is a plan view of the external lead after the melting and cutting of the solder in FIG. 4;

【図6】本発明の第2の実施例の平面図である。FIG. 6 is a plan view of the second embodiment of the present invention.

【図7】図6の第2の実施例を用いた樹脂封止後の断面
図である。
7 is a cross-sectional view after resin sealing using the second embodiment of FIG.

【図8】図6の外部リードの部分拡大平面図である。8 is a partially enlarged plan view of the external lead of FIG.

【図9】図8の半田溶融切断後の平面図である。FIG. 9 is a plan view after melting and cutting the solder of FIG. 8;

【図10】従来の半導体装置用リードフレームの一例の
平面図である。
FIG. 10 is a plan view of an example of a conventional semiconductor device lead frame.

【図11】図10の半導体装置用リードフレームを用い
た樹脂封止後の平面図である。
11 is a plan view after resin sealing using the lead frame for a semiconductor device of FIG.

【図12】図11の断面図である。12 is a cross-sectional view of FIG.

【図13】図11の外部リードの部分拡大平面図であ
る。
FIG. 13 is a partially enlarged plan view of the external lead shown in FIG.

【図14】図13のタイバー切断後の外部リードの平面
図である。
14 is a plan view of the external lead after cutting the tie bar of FIG.

【符号の説明】[Explanation of symbols]

1 リードフレーム 2 枠リードフレーム 3 アイランド 4 内部リード 5 外部リード 6 半田 7 半導体素子 8 樹脂封止部 9 金線 10 ダム部 11 付着樹脂 12 タイバー 1 lead frame 2 frame lead frame 3 island 4 internal lead 5 external lead 6 solder 7 semiconductor element 8 resin sealing part 9 gold wire 10 dam part 11 adhered resin 12 tie bar

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載するアイランドと、該
アイランドの周囲に配置された内部リードと、該内部リ
ードに接続する外部リードとを有する樹脂封止型の半導
体装置用リードフレームにおいて、前記外部リード間の
少くとも一部に半田を埋め込みそれぞれの前記外部リー
ドを前記半田にて連結したことを特徴とする半導体装置
用リードフレーム。
1. A resin-encapsulated lead frame for a semiconductor device, comprising: an island on which a semiconductor element is mounted; internal leads arranged around the island; and external leads connected to the internal leads. A lead frame for a semiconductor device, characterized in that solder is embedded in at least a part between the leads to connect the respective external leads with the solder.
JP4219864A 1992-08-19 1992-08-19 Lead frame for semiconductor device Pending JPH0669397A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4219864A JPH0669397A (en) 1992-08-19 1992-08-19 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4219864A JPH0669397A (en) 1992-08-19 1992-08-19 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0669397A true JPH0669397A (en) 1994-03-11

Family

ID=16742257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4219864A Pending JPH0669397A (en) 1992-08-19 1992-08-19 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0669397A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525547A (en) * 1992-12-16 1996-06-11 Hitachi, Ltd. Method of fabricating a molded semiconductor device having blocking banks between leads
JP2012043882A (en) * 2010-08-17 2012-03-01 Denso Corp Method of manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152485A (en) * 1991-11-29 1993-06-18 Hitachi Ltd Semiconductor devices and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152485A (en) * 1991-11-29 1993-06-18 Hitachi Ltd Semiconductor devices and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525547A (en) * 1992-12-16 1996-06-11 Hitachi, Ltd. Method of fabricating a molded semiconductor device having blocking banks between leads
JP2012043882A (en) * 2010-08-17 2012-03-01 Denso Corp Method of manufacturing semiconductor device

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