JPH0671253B2 - Synchronous data transfer method - Google Patents

Description

The present invention relates to a synchronous data transfer system between logic devices sharing a clock source.

[Conventional technology]

Conventionally, in synchronous data transfer between logical devices of this type,
If the delay time due to the line length of the connecting wire used as the transmission line between the transmission register and the reception register is shorter than the delay time that can be received in one clock cycle, data transfer at one clock rate is performed and data can be received in one clock cycle. If the delay time is longer than the specified delay time, insert a relay register between these registers so that the delay time between registers is always shorter than the delay time that can be received in one clock cycle.
Data is being transferred at the clock rate.

[Problems to be solved by the invention]

In the above-described conventional data transfer method, when the delay time due to the line length of the connecting wire material is one clock cycle or more, the number of relay registers provided so as to transfer at one clock rate increases, and as a result, the amount of hardware is reduced. It has the disadvantage of increasing.

[Means for solving problems]

The synchronous data transfer method of the present invention is a data transfer method between a first logic device and a second logic device that uses clocks distributed from the same clock source, and is provided in the first logic device. A transmission register that performs an update operation in synchronization with the clock signal, a reception register that is provided in the second logic device and that performs an update operation in synchronization with a clock signal from the clock source, and the reception register from the transmission register. A transmission line is provided between the registers for transferring data to the registers and has a length that guarantees a minimum delay time that cannot be received in one clock cycle and a maximum delay time that can be received in two clock cycles.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the data processing system of this embodiment, the same clock is supplied from the clock unit 1 to the logic units 2 and 3 (here, the case of two units is shown). The clock device 1 includes a clock oscillator 10 and a clock distributor 11. The logic device 2 (3) includes a clock distributor 21 (31) and a transmission register 20 (reception register 30), and the transmission register 20 and the reception register 30 are connected by a transmission line 4. (The logic unit 2 includes a reception register and others, and the logic unit 3 includes a transmission register and others.
For the sake of convenience, the illustration is omitted here.) The transmission line 4 is shown in the notation of a delay element in order to cooperate that it has a delay time αt. The transmission register 20, the reception register 30, and the clock oscillator 10 are used as a common clock source and are supplied with the same clock by the clock distributors 11, 21, and 31. The clock cycle is Tc, the clock skew of the transmission register 20 and the reception register 30 is T _S , and the delay time per 1 m of the transmission line 4 is
t _W (1 ± δ). δ indicates variation due to material and environment. The output rise time of the transmission register 20 is t _F , the setup time of the reception register 30 is T _SU , and the hold time is T _HD.
And

As shown in FIG. 2, transfer data is set in the transmission register 20 every clock. The output of the transmission register 20 has a delay time of T _F ± T _S with reference to the clock of the reception register 30. If the length of the transmission line is Lm, the delay time is L
t _W · (1 ± δ), Tmin = T _F min-T _S + L · t _W (1-δ) T _C + T _HD (1) Tmax = T _F max + T _S + L · t _W (1 + δ) <2・ If T _C −T _SU (2), transmit register at clock 1 as shown in FIG.
The data D ₁ set to 20 is received by the reception register 30 after 2 clocks.

For example, if T _C = 8ns, T _S = 1ns, t _W = 4ns / m, δ = 0.1, T _F min = 0, T _F max = 1ns, T _SU ＝ T _HD = 1ns, Therefore, it is understood that the line length should be selected from 2.77m to 2.99m.

〔The invention's effect〕

As described above, according to the present invention, if the delay time of the transmission line is long enough to be received in two clock cycles, data can be transferred at one clock rate without using an interruption register. It is possible to reduce the cost and the associated low price.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart explaining the operation of the embodiment. 1 ... Clock device, 2, 3 ... Logic device, 4 ... Transmission line, 10 ... Clock oscillator, 20 ... Transmission register, 30 ...
… Reception registers, 11,21,31 …… Clock distributor.

Claims (1)

[Claims] 1. A data transfer method between first and second logic devices using clocks distributed from the same clock source, wherein the data transfer system is provided in the first logic device and synchronized with a clock signal from the clock source. And a transmission register for performing an update operation, a reception register provided in the second logic device for performing an update operation in synchronization with a clock signal from the clock source, and data transferred from the transmission register to the reception register. In order to achieve this, a synchronous line characterized by having a transmission line provided between these registers and having a length that guarantees a minimum delay time that cannot be received in one clock cycle and a maximum delay time that can be received in two clock cycles Data transfer method.