JPH0677252A - Thin film-shaped semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to manufacture an active matrix circuit having a high ON/OFF ratio and a peripheral drive circuit to need a complicated wiring in the same process at a high yield by a method wherein an anode oxide layer is formed on the surface of a metal film, the metal film and the anode oxide layer are selectively removed to form gate electrodes and the like. CONSTITUTION:Insular semiconductor regions 103 and 104 are formed on an insulating substrate 101, an insulating film 105 to function as a gate insulating film is formed on the semiconductor films 103 and 104 and a film 16 containing a metallic element as its main component is formed on the film 15. Then, a current is made to flow through the film 106 in an electrolyte to form an anode oxide layer 107 of a thickness of 100nm or thicker on the surface of the film 106 and the film 106 and the layer 107 are selectively removed to form gate electrodes 108 to 110. Then, after an impurity element is introduced in a self- alignment manner using the electrodes 108 and 110 as main masks, a laser beam or the like is emitted using the electrodes 108 to 110 as main masks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating gate type semiconductor device on an insulating substrate and an integrated circuit in which a large number of them are formed with a high yield, and a semiconductor device formed by such a method. The semiconductor device according to the present invention is used as a drive circuit such as an active matrix such as a liquid crystal display or an image sensor, or as a thin film transistor in an SOI integrated circuit or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor memory, etc.). It is what is done.

Further, according to the present invention, an active matrix in a broad sense (a circuit in which wirings are arranged in a matrix form and a circuit including one or more transistors for selection is provided at an intersection thereof) and it is driven. The present invention relates to an integrated semiconductor device having a peripheral circuit for operating. Specifically, an active matrix liquid crystal display (AM-L
CD), DRAM, SRAM, EPROM, EEPR
A semiconductor integrated circuit such as an OM or a mask ROM, which is formed on an insulating substrate.

[0003]

2. Description of the Related Art Recently, much research has been done on forming an insulating gate type semiconductor device (MOSFET) on an insulating substrate. Forming the semiconductor integrated circuit on the insulating substrate in this manner is advantageous for high-speed driving of the circuit. Because
This is because the speed of the conventional semiconductor integrated circuit is limited mainly by the capacitance (stray capacitance) between the wiring and the substrate, but such stray capacitance does not exist on the insulating substrate. A MOSFET having a thin film-like active layer formed on an insulating substrate in this manner is called a thin film transistor (TFT). Even in the conventional semiconductor integrated circuit, for example, SRA
A TFT is used as the M load transistor.

Further, recently, a product requiring the formation of a semiconductor integrated circuit on a transparent substrate has appeared. For example, it is a drive circuit for an optical device such as a liquid crystal display or an image sensor. A TFT is also used here. Since these circuits are required to be formed in a large area, it is required to lower the temperature of the TFT manufacturing process. Further, for example, in a device having a large number of terminals on an insulating substrate, even when it is necessary to connect the terminals to the semiconductor integrated circuit, in order to reduce the mounting density, the first stage of the semiconductor integrated circuit, Alternatively, it is considered that the semiconductor integrated circuit itself is monolithically formed on the same insulating substrate.

Conventionally, a TFT is provided with an amorphous, semi-amorphous, or microcrystalline semiconductor film 450.
It has been attempted to improve the crystallinity and improve the quality of the semiconductor film (that is, the mobility is sufficiently high) by annealing at a temperature of ℃ to 1200 ℃. Amorphous TFT using amorphous material for semiconductor film
However, mobility is 5 cm ² / Vs or less, usually 1 cm
^It is as small as ² / Vs, and in terms of operating speed, P
The use of the TFT of the channel type is greatly limited because it cannot be obtained. TF with mobility of 5 cm ² / Vs or more
Annealing at the above temperature was required to obtain T. Moreover, a P-channel TFT (PTFT) could be formed by such annealing. Alternatively, these thermal annealing steps were also performed by irradiation with laser light or intense light.

However, it has been pointed out that such a TFT has a problem in reliability when used as an active matrix due to a large leak current in an off state. Against this background, the present inventors have filed Japanese Patent Application No. 4-34194 or 4-30220.
As described in (1), the gate electrode is made of a low resistance metal material such as aluminum and the surface thereof is anodized to be coated with an oxide.
We proposed a method of forming an offset region by introducing impurities using an oxide structure as a main mask. As a result, it becomes possible to reduce the leak current and to strengthen the insulation between the layers by the anodic oxide film, thereby significantly reducing the short circuit at the cross portion.

That is, the anodic oxide film has few pinholes and has a very high withstand voltage (7 MV / cm).
Because of the above), the layers can be reliably insulated. Actually Japanese patent application 4
By adopting the technology of No. 34194 or No. 4-30220, it was possible to significantly reduce defects due to short-circuiting between wirings. In the active matrix region, it is particularly important because there are so many intersections of wiring.

[0008]

However, the present inventors have used this technique to form a device (for example, a device in which an active matrix and its peripheral drive circuit are formed monolithically).
It has been found that there are technically very difficult problems in producing a memory or an AM-LCD).

Generally, the configuration and wiring connection of the peripheral circuit are complicated, and even if an attempt is made to cover the metal electrode with anodic oxide, current cannot be supplied due to the complexity of the wiring, and However, if the wiring is forcibly formed only for anodic oxidation, an additional photolithography process for removing the wiring is required, resulting in a decrease in yield. Further, when the circuit is configured by providing the extra wiring as described above, the integration degree is remarkably reduced.

However, for example, a method has been proposed in which the anodizing process is adopted in the active matrix circuit part and the anodizing process is not adopted in other regions such as the peripheral circuit part, but the yield is remarkably low. This is because there are many pinholes mainly due to incomplete interlayer insulation, and the upper wiring and the lower wiring (gate electrode and its wiring, etc.) are short-circuited through such pinholes. It turned out to be

In particular, this was an essential problem as long as the metal wiring having a low melting point was used. It is a well-known fact that aluminum and its alloys are excellent as gate electrode materials, but if this method is used to introduce an impurity element in a self-aligned manner as a gate electrode, activation by thermal annealing is adopted. However, it was inevitable that a low temperature activation technique such as laser annealing had to be adopted for the activation of the impurity element. Further, formation of an interlayer insulating film at 450 ° C. or higher could not be used.

For example, by setting the substrate temperature to 450 ° C. or higher,
The interlayer insulating material such as silicon oxide formed by the LPCVD method or the APCVD method has very few pinholes and almost no short circuit between wirings. However, 4
At a low temperature of 50 ° C. or lower, only the sputtering method or the plasma CVD method can be adopted, and in these methods, a large amount of dust is poured into the film during film formation, resulting in very many pinholes.
It became a film with a problem of insulation. Even in the peripheral driving circuit section, there is an intersection of wirings. Therefore, it is desired to form the anodic oxide by some method in order to improve the yield.

[0013]

In view of the above problems, the present invention has been made as an attempt to provide an optimum device structure and manufacturing process. In the first place, Japanese Patent Application 4-3
The greatest feature obtained by providing an anodic oxide such as 4194 or 4-30220 is the leakage current when a reverse voltage is applied to the gate due to the effect of offset, as also shown in the specification. Was significantly reduced. Such characteristics have been necessary for the TFT in the active matrix region that performs a dynamic operation that needs to reliably hold the pixel voltage. Alternatively, it was necessary to reduce the power consumption of the flip-flop circuit during standby. In that sense, a TFT having such a structure is used as a pixel transistor of an AM-LCD, a memory bit selection transistor of a DRAM formed by SOI technology, or an SRAM (particularly a complete CMOS).
Type SRAM), a large effect was obtained by using it for the transistor that constitutes the inverter circuit of the memory bit.

However, in the peripheral circuit, the leak current is not a serious problem, especially if the circuit performs static or semi-static operation.
Therefore, the circuit operates sufficiently even if the anodic oxide is not provided on at least the side surface (without the offset structure).

However, if there is no dense coating such as anodic oxide on the upper surface of the gate electrode, the yield will be remarkably reduced due to leakage between the wirings. Further, as described in the specification of the above patent application, when the laser annealing is adopted, the presence of the anodic oxide on the upper surface of the gate electrode can minimize the damage due to the laser annealing process. did it.

According to the knowledge of the present inventors, since the aluminum metal film formed by the electron beam evaporation method has a flat surface and a particle size of submicron or less, the ultraviolet ray reflection is particularly good and direct laser irradiation is carried out. However, almost no damage was observed, but very large damage was observed in the coating having a large grain size (up to 1 μm) formed by a method such as the sputtering method. However, since the electron beam evaporation method is inferior in mass productivity, it is practically desired to manufacture it by the sputtering method. That is, the peripheral circuit does not require the anodic oxide on the side surface of the gate electrode, but does need it on the upper surface.

Therefore, in the present invention, it is proposed to form a TFT having a structure in which the anodic oxide does not substantially exist on the side surface of the gate electrode and the anodic oxide exists only on the upper surface together with the TFT in the active matrix region. To do. A method of manufacturing a TFT having such a structure and a device as an assembly thereof may be performed as follows.

First, a metal film of aluminum or the like is formed on the island-shaped semiconductor region and the gate insulating film. And
An oxide film is formed on the surface by the anodic oxidation method. According to the knowledge of the present inventors, when the thickness of the oxide is 100 nm or less, the composition is different from the stoichiometric ratio, and thus the insulating property is poor.
It was desirable that the thickness of the insulator be 100 nm or more.

After that, if the oxide and the metal film are etched to form a gate electrode having a desired shape, it is possible to leave the anodic oxide on the upper surface of the gate electrode and leave the anodic oxide on the side surface. it can.

A directional etching method such as reactive ion etching (RIE) is preferable for these etchings. This is because in the isotropic etching method, a difference in etching rate between the anodic oxide and the metal coating causes holes (cusps) near the interface, which easily causes disconnection of the upper wiring. is there. However, depending on the material, there are cases where all processes cannot be performed by RIE or the like.

For example, when the metal material is aluminum, the anodic oxide is aluminum oxide, which is RI.
Cannot be removed by E. Therefore, in this case, first, the aluminum oxide film may be etched by wet etching, and then the metal aluminum may be etched by RIE using the remaining aluminum oxide as a mask.

If the etching of metal aluminum is R
When the IE cannot be adopted and only the wet etching is used, it is desirable that the metal aluminum film be as thin as possible. Specifically, it is desired that the ratio of the film thickness of the aluminum oxide film to the film thickness of metal aluminum is 1: 3 or less, preferably 1: 2 or less.

If a monolithic matrix circuit is to be constructed using such TFTs, it may be performed as follows. The first method consists of the following processes. A metal film is similarly formed on the peripheral circuit and the matrix region. This is anodized to form an anodic oxide on the surface. Etch the anodic oxide where it is not needed. The metal film is etched using the remaining anodic oxide as a mask to form a gate electrode in the peripheral circuit section and the matrix section. An anodic oxide is formed only on the gate electrodes of the matrix portion and on the side surfaces of the matrix electrode by passing a current only through the matrix portion.

In this method, paying attention to the matrix portion, the second anodic oxidation is performed in the process while the anodic oxide formed in the first process remains on the gate electrode. There is a case where stress distortion occurs between the anodic oxide and the anodic oxide formed thereafter, and the anodic oxide on the upper part formed first may peel off.

To solve this, as shown in the first embodiment, after the process, the anodic oxide in the matrix portion is removed by masking only the'peripheral circuit portion. The above process may be added. Through these steps, the metal material is exposed over the entire surface of the gate electrode in the matrix portion, whereby anodic oxide is uniformly formed on the upper surface and the side surfaces. It is easy to mask only the matrix portion, and the addition of this step does not reduce the yield. However, depending on the type of etchant, the gate insulating film is also etched in this step. If the surface of the semiconductor region is exposed, it will cause a decrease in yield, so be careful. In any case, at least two anodic oxidation steps are required.

The second method is the method of the second embodiment,
It mainly consists of the following processes. A metal coating is entirely formed on the peripheral circuit portion, and a metal coating is formed on the matrix portion while keeping the shape of the gate electrode. An anodic oxide is formed by passing an electric current through the metal film in the peripheral circuit section and the gate electrode (and its wiring) in the matrix section. The anodic oxide and the metal film in the peripheral circuit section are etched to form a gate electrode in the peripheral circuit section.

In this method, the anodic oxidation process is performed once, but the photolithography process is required at least twice for (mainly) formation of the gate electrode in the matrix portion and formation of the gate electrode in the peripheral circuit portion. .

[0028]

EXAMPLES Example 1 Substrate (Corning 7059,
300 mm x 300 mm or 100 mm x 100 m
m) a thickness of 100 to 3 as an underlying oxide film 102 on 101
A silicon oxide film having a thickness of 00 nm was formed. As a method of forming this oxide film, a film obtained by decomposing and depositing a sputtering method in an oxygen atmosphere or TEOS by a plasma CVD method is used for 450 to 650.
It may be annealed at ° C.

After that, an amorphous silicon film of 30 to 150 n is formed by plasma CVD method or LPCVD method.
m, preferably 50 to 100 nm, and a thickness of 20 to 10 as a protective layer by a plasma CVD method.
A silicon oxide or silicon nitride film having a thickness of 0 nm, preferably 20 to 40 nm was formed. Then, by annealing at 550 to 650 ° C., preferably 600 ° C. for 72 hours,
The amorphous silicon film was crystallized. When the crystallinity of the silicon film crystallized in this way was examined by Raman scattering spectroscopy, a relatively broad peak was observed near 515 cm ⁻¹ , unlike the peak of single crystal silicon (521 cm ⁻¹ ). Was done.

Next, the protective layer is removed to expose the silicon layer, and the silicon layer is patterned into an island shape to form the TFT region 103 of the peripheral drive circuit and the TFT region 10 of the matrix circuit.
4 was formed. Further, a gate oxide film 105 having a thickness of 50 to 200 nm was formed by a sputtering method in an oxygen atmosphere. After that, an aluminum film 106 having a thickness of 200 nm to 5 μm, preferably 200 to 600 nm was formed over the entire surface of the substrate by an electron beam evaporation method. Then, this is oxidized by an anodic oxidation method to have a thickness of 100 to 3 on the surface.
A 00 nm anodic oxide 107 was formed. The conditions of anodic oxidation were those shown in Japanese Patent Application Nos. 4-30220, 4-38637 and 4-54322.

Further, as shown in FIG. 1B, after etching the anodic oxide with an etchant mainly containing hydrofluoric acid (for example, 1/10 buffer HF), the remaining anodic oxide is used as a mask. , The metal aluminum film 106 was etched by RIE. Further, the peripheral circuit region was masked, and the anodic oxide on the gate electrode of the matrix circuit portion was etched. Thus, the gate electrode 108 (NTFT) of the peripheral drive circuit section is
(For PTFT) and 109 (for PTFT), and gate electrodes 110 of the matrix circuit section were obtained. (Fig. 1 (B))

After that, a current is passed only through the gate electrodes of the matrix circuit section to obtain a thickness of 200 to 300 under the same conditions as above.
nm, for example 250 nm, of anodic oxide 111 was formed on the top and side surfaces of the gate electrode. (Fig. 1 (C))

After that, by the ion doping method, impurities were implanted into the island-shaped silicon film of each TFT in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the anodic oxide film around it) as a mask. At this time, first, phosphorus is injected into the entire surface by using phosphine (PH ₃ ) as a doping gas, and then only the left side of the island region 103 in the figure is covered with a photoresist and doped with diborane (B ₂ H ₆ ). Boron was injected into the island regions 103 and 104 as a gas. The dose amount was set to 2 to 8 × 10 ¹⁵ cm ⁻² for phosphorus and 4 to 10 × 10 ¹⁵ cm ⁻² for boron, and the dose amount of boron was set to exceed that of phosphorus.

Thereafter, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to introduce the above-mentioned impurity region to improve the crystallinity of the portion where the crystallinity was deteriorated. Laser energy density is 200
To 400 mJ / cm ² , preferably 250 to 300 mJ
/ Cm ² . As a result, an N-type region 112 and a P-type region 113 in the peripheral circuit, and a P-type region 114 of the matrix circuit were formed. The sheet resistance in these regions was 200 to 800 Ω / □. In this step, strong light irradiation having the same effect as irradiation with laser light may be used instead of pulsed laser light such as KrF excimer laser. This method is called RTA (Rapid Thermal Annealing), and is infrared light, particularly infrared light having a peak at 1 to 2 μm (preferably halogen light (1.3 μm).
m)) is utilized to selectively heat the silicon semiconductor. According to this method, the region in which the impurities are introduced can be heated to about 1000 to 1200 degrees, and effective annealing can be performed. Since such infrared light is selectively absorbed by the silicon semiconductor,
The silicon film can be annealed without causing thermal damage to the glass substrate. Further, it is also a feature that the effect can be enhanced by irradiation for a short time of several seconds to several minutes. The state so far is shown in FIG.

After that, an interlayer insulator 115 is formed on the entire surface.
A 300-nm-thick silicon oxide film was formed by a sputtering method. This may be a silicon oxide film or a silicon nitride film formed by the plasma CVD method.

After that, the ITO film formed on the matrix portion by the sputtering method is etched to form the pixel electrode 116.
Further, contact holes are formed in the source / drain of each TFT, and the chromium wiring 117 is formed by sputtering film formation and photolithography as shown in FIG.
.About.121 (each having a thickness of 800 nm) was formed. In this case, it is shown that the inverter circuit is formed by the NTFT and the PTFT in the peripheral circuit area. Finally, it was annealed in hydrogen at 350 ° C. for 2 hours to reduce dangling bonds in the silicon film. Through the above steps, the peripheral circuit and the active matrix circuit could be integrally formed.

[Embodiment 2] This embodiment is shown in FIG. First, the substrate (Corning 7059, 300 mm x 300 m
m or 100 mm × 100 mm) 201, a silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 202. As a method of forming this oxide film, a film obtained by decomposing and depositing TEOS by a plasma CVD method or a sputtering method in an oxygen atmosphere may be annealed at 450 to 650 ° C.

After that, the amorphous silicon film 203 is formed by 30 to 1 by the plasma CVD method or the LPCVD method.
50 nm, preferably 50 to 100 nm is deposited, and further as a protective layer 204 by plasma CVD method.
A silicon oxide or silicon nitride film having a thickness of 20 to 100 nm, preferably 50 to 70 nm was formed. And FIG.
As shown in (A), the KrF excimer laser (wavelength 2
Irradiation with 48 nm and a pulse width of 20 nsec) was performed to improve the crystallinity of the silicon film 203. The energy density of the laser is 200 to 400 mJ / cm ² , preferably 25.
It was set to 0 to 300 mJ / cm ² . When the crystallinity of the silicon film 203 thus formed was examined by Raman scattering spectroscopy, the peak (521c) of single crystal silicon was obtained.
In contrast to m ⁻¹ ), a relatively broad peak was observed around 515 cm ⁻¹ . After crystallization of the silicon film 203 by the irradiation of the KrF excimer laser, it is useful to irradiate the silicon film 203 with strong infrared light to further promote crystallization. Since infrared light is selectively absorbed by the silicon semiconductor, crystallization of the silicon film 203 can be effectively promoted without heating the glass substrate so much. Specifically, defects and dangling bonds can be reduced. In addition, crystallization may be performed only by irradiation with strong light. Then, it was annealed in hydrogen at 350 ° C. for 2 hours.

Next, the protective layer 204 is removed to expose the silicon layer 203, and this is patterned into an island shape.
A peripheral circuit region and an active matrix region were formed in the same manner as in Example 1. Furthermore, a film obtained by decomposing and depositing a sputtering method in an oxygen atmosphere or TEOS by a plasma CVD method is used.
A gate oxide film was formed by a method of annealing at 50 to 650 ° C. Especially when adopting the latter method,
Due to the temperature of this step, the substrate may be distorted or shrunk, which may make it difficult to align the mask later. Therefore, care must be taken when handling a large-area substrate. Although the substrate temperature can be set to 150 ° C. or lower by the sputtering method, it is desirable to anneal at about 300 to 450 ° C. in hydrogen in order to reduce dangling bonds and the like in the film and reduce the influence of fixed charges.

After that, an aluminum film having a thickness of 200 to 500 nm is formed by a sputtering method, and this is patterned, and as shown in FIG. 2B, the metal aluminum film 205 covering the peripheral circuit region and the gate of the active matrix region are formed. The electrode 206 was formed.

Further, as shown in FIG. 2C, the substrate was dipped in an electrolytic solution to pass a current through the aluminum coating 205 and the gate electrode 206 to form anodic oxide layers 207 and 208 on or around the surface thereof. . In this embodiment, the thickness of the anodic oxide film is 200 to 250 nm. As a result, the thickness of the remaining metallic aluminum is 1
It was 00-400 nm.

Then, as shown in FIG. 2D, gate electrodes 209 and 210 of the TFT in the peripheral circuit region are formed.
First, the anodic oxide layer is etched by a wet etching method with an etchant mainly containing hydrofluoric acid (for example, 1/10 buffer HF), and then,
Aluminum was etched with a mixed acid using the remaining anodic oxide as a mask. The gate electrodes were formed in this manner, but the anodic oxide remained on these gate electrodes as shown in the figure. On the other hand, the gate electrode 211 of the TFT in the active matrix region remains unchanged.

After that, impurities were injected into the island-shaped silicon film of each TFT in a self-aligned manner by ion doping using the gate electrode portion (that is, the gate electrode and the anodic oxide film around it) as a mask. At this time, first, phosphine (PH ₃ ) is used as a doping gas, and phosphorus is injected into the entire surface. Then, only the left side of the peripheral circuit region in the figure is covered with photoresist, and diborane (B ₂ H ₆ ) is used as a doping gas. As a result, boron was implanted only into the right side of the peripheral circuit region and the matrix region. The dose is 2-8 × 10 for phosphorus
¹⁵ cm ^-2, boron and 4~10 × 10 ¹⁵ cm ^-2, the dose of boron was set to exceed the phosphorous.

After that, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to introduce the above-mentioned impurity region to improve the crystallinity of the portion where the crystallinity was deteriorated. Laser energy density is 200
To 400 mJ / cm ² , preferably 250 to 300 mJ
/ Cm ² . Further, this step may be performed by annealing by irradiation with intense light (infrared light).

As a result, N-type regions 212 and P-type regions 213 and 214 were formed as shown in FIG. The sheet resistance of these areas is 200-800Ω
It was / □. After that, a silicon oxide film having a thickness of 300 nm was formed as an interlayer insulator 215 over the entire surface by a sputtering method. This may be a silicon nitride film formed by the plasma CVD method.

After that, the TFT of the active matrix section
A pixel electrode 216 was formed of a transparent conductive material (ITO or the like). Then, contact holes were formed in the source / drain of each TFT, and chromium wirings 217 to 221 were formed. In this case, NTFT and PTF in the peripheral circuit area
It is shown that the inverter circuit is formed by T. Finally, annealing was performed in hydrogen at 350 ° C. for 2 hours to reduce dangling bonds in the silicon film.
Through the above steps, the peripheral circuit and the active matrix circuit could be integrally formed.

[0047]

According to the present invention, T having a large OFF resistance is provided.
The FT was formed in the active matrix region, and the peripheral circuit region having a complicated structure was also formed with good yield, and both could be formed monolithically in the same process. Therefore, for example, with regard to AM-LCD, the cost is 3 compared to the case where the TAB connection is performed as in the conventional case.
We were able to reduce it by 0% or more. The conventional TFT has a problem that a TFT having high mobility cannot obtain a sufficient OFF resistance. Therefore, for example, when the TFT having the same structure is used for the matrix and the peripheral circuit by the high temperature process, one of the functions must be sacrificed.

On the other hand, according to the method described in Japanese Patent Application No. 4-34194 or 4-30220, an ideal TFT having high mobility and large OFF resistance was obtained. Digital gradation applied by people (for example, Japanese Patent Application Nos. 3-169306 and 3-2098).
Even if a high speed operation and a high ON / OFF ratio are required as in 69), there is no problem in displaying.

However, if the TFT described in Japanese Patent Application No. 4-34194 or 4-30220 is applied to a peripheral driving circuit having a complicated circuit, there is a great difficulty in manufacturing. The present invention gives a clear answer to this contradiction. In particular, the digital gradation display requires complicated signal processing as compared with a normal display method, so that the circuit configuration is extremely complicated. Therefore, in the past, the peripheral drive circuit was TA only because the anodic oxidation process was difficult.
I had to connect to the IC with the B connection.

According to the present invention, any complicated peripheral circuit can be formed with almost no deterioration in its capability.
Of course, the present invention is not limited to the digital gradation display method, but an LCD adopting a normal analog gradation display method.
It goes without saying that it is also effective. Especially, the number of rows is 1
With a high-definition LCD of 000 or more, the effect can be fully demonstrated. Although the AM-LCD is described in the embodiments, a device having an active matrix and a peripheral drive circuit in a broad sense (for example, DRAM or SRAM).
It will be clear that the same effect can be obtained by the present invention in all cases. Thus, the present invention is industrially
It is extremely beneficial.

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a TFT according to the present invention.

FIG. 2 shows a method for manufacturing a TFT according to the present invention.

[Explanation of symbols]

101 Insulating Substrate 102 Underlying Oxide Film 103 Semiconductor Region (for Peripheral Driving Circuit) 104 Semiconductor Region (for Active Matrix) 105 Gate Insulating Film 106 Metal Film 107 Anodic Oxide of Metal Film 108 Gate Electrode (for NTFT of Peripheral Circuit) 109 Gate Electrode (for PTFT of peripheral circuit) 110 Gate electrode (for PTFT of active matrix circuit) 111 Anodized film 112 N-type impurity region 113, 114 P-type impurity region 115 Interlayer insulator 116 Pixel electrode (ITO) 117-121 Metal wiring

Claims (5)

[Claims] 1. A step of forming an island-shaped semiconductor region on an insulating substrate, a step of forming an insulating film functioning as a gate insulating film on the semiconductor film, and a metal element as a main component on the insulating film. And a step of forming a anodic oxide layer having a thickness of 100 nm or more on the surface of the metal coating by passing a current through the metal coating in an electrolytic solution, and selectively selecting the metal coating and the anodic oxide. To form a gate electrode, a step of introducing an impurity element in a self-aligned manner using the gate electrode as a main mask, and after the step, a laser beam or an equivalent strong laser beam is used as the gate electrode as a main mask. And a step of irradiating light, the method for manufacturing a thin film semiconductor device. 2. A semiconductor device having a plurality of thin film transistors formed on an insulating substrate and having a metal material containing aluminum as a main component as a gate electrode / wiring, the device including an active matrix portion and a peripheral drive circuit portion. Then
The gate electrode of the thin film transistor in the active matrix portion has an aluminum oxide film with a thickness of 100 nm or more on the side surface and the upper surface thereof, and the gate electrode of the thin film transistor in the peripheral drive circuit portion has a thickness of 1 nm on the upper surface.
A thin film semiconductor device having an aluminum oxide film of 00 nm or more, but having substantially no aluminum oxide on its side surface. 3. A step of forming an active matrix circuit and a peripheral drive circuit on an insulating substrate, the step of forming a plurality of island-shaped semiconductor regions for the active matrix circuit and the peripheral drive circuit, and on the semiconductor region. A step of forming an insulating coating functioning as a gate insulating film, a step of forming a coating containing a metal element as a main component on the insulating coating, and applying a current to the coating in an electrolytic solution to form a surface of the coating. A step of forming an anodic oxide layer of 100 nm or more on the substrate, a step of patterning the film and the anodic oxide on the film to form a gate electrode, and an electrolyte solution only on the gate electrode of the active matrix circuit among the gate electrodes. A step of forming an anodic oxide on the top and side surfaces of the active matrix circuit and the peripheral drive circuit by passing a current therethrough. And a step of introducing an impurity into the semiconductor region in a self-aligning manner using the oxide electrode as a main mask in a self-aligning manner. 4. A step of forming a plurality of island-shaped semiconductor regions for an active matrix circuit and a peripheral drive circuit in the step of forming an active matrix circuit and a peripheral drive circuit on an insulating substrate, and on the semiconductor region. A step of forming an insulating coating functioning as a gate insulating film, a step of forming a coating containing a metal element as a main component on the insulating coating, and selectively patterning the coating to form a gate electrode of an active matrix circuit. And a step of forming a film covering the wiring and the peripheral circuit part, and a current is passed through the gate electrode of the active matrix circuit and the film covering the wire and the peripheral circuit part in an electrolytic solution to form the gate electrode and the film. 10 anodic oxide layer on the coating surface
Mainly forming the gate electrode of the active matrix circuit and the peripheral drive circuit, the step of forming 0 nm or more, the step of patterning the film covering the peripheral circuit section and the anodic oxide thereon to form the gate electrode of the peripheral drive circuit section. And a step of introducing impurities into the semiconductor region in a self-aligning manner as a mask. 5. The thin film shape according to claim 3 or 4, further comprising a step of irradiating a laser beam or strong light equivalent thereto with the gate electrode as a main mask after the impurity introducing step is completed. Manufacturing method of semiconductor device.