JPH0677334A - Manufacture and processor of electrode wiring - Google Patents

Manufacture and processor of electrode wiring

Info

Publication number
JPH0677334A
JPH0677334A JP22972392A JP22972392A JPH0677334A JP H0677334 A JPH0677334 A JP H0677334A JP 22972392 A JP22972392 A JP 22972392A JP 22972392 A JP22972392 A JP 22972392A JP H0677334 A JPH0677334 A JP H0677334A
Authority
JP
Japan
Prior art keywords
substrate
film
temperature
aluminum
electrode wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22972392A
Other languages
Japanese (ja)
Inventor
Kenji Hinode
憲治 日野出
Yoshio Honma
喜夫 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP22972392A priority Critical patent/JPH0677334A/en
Publication of JPH0677334A publication Critical patent/JPH0677334A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】 (修正有) 【目的】簡単な処理でアスペクト比の高い接続孔部に十
分な被覆率の信頼性の高い接続孔配線を形成する。 【構成】開口部41もしくは溝状の凹部を有する基板1
1上に、アルミニウムもしくはアルミニウム合金膜23
を形成した状態で、一気圧以上の圧力を印加しながら1
/2Tm(Tmは絶対温度で表したその材料の融点)以
上の温度に保持することもしくは表面酸化膜汚染物の無
い状態で1/2Tm以上の温度に保持する。 【効果】開口部内アルミ合金膜の空洞部を除去できる。
(57) [Summary] (Modified) [Purpose] To form a highly reliable contact hole wiring with a sufficient coverage in a contact hole portion with a high aspect ratio by a simple process. [Structure] Substrate 1 having an opening 41 or a groove-shaped recess
On top of the aluminum or aluminum alloy film 23
While applying pressure of 1 atm or more,
The temperature is maintained above / 2Tm (Tm is the melting point of the material expressed in absolute temperature) or above, or is maintained above 1 / 2Tm in the absence of surface oxide film contaminants. [Effect] The cavity of the aluminum alloy film in the opening can be removed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置などの電極配
線に係わり、特に高アスペクト比の縦方向の接続孔配線
の形成に好適な電極配線の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode wiring of a semiconductor device or the like, and more particularly to a method of manufacturing an electrode wiring suitable for forming a vertical connection hole wiring having a high aspect ratio.

【0002】[0002]

【従来の技術】半導体装置の高集積化に対応するため配
線は多層化という方法が採用されている。この多層配線
における層間の接続孔や、半導体基板内に形成された能
動部分との接続電極との接続孔は、集積度の増加ととも
にアスペクト比(深さ/径の比)が高くなっている。現在
の代表的な金属膜形成法であるスパッタ法では、このよ
うにアスペクト比の高い接続孔に十分な被覆率の膜を形
成することが困難であり、幾つかの新しい方法もしくは
従来法を改良した方法が検討され、適用され始めてい
る。その代表的なものを次にあげる。
2. Description of the Related Art In order to cope with high integration of semiconductor devices, a method of forming wiring in multiple layers is adopted. The aspect ratio (depth / diameter ratio) of the connection hole between the layers in the multilayer wiring and the connection hole with the connection electrode with the active portion formed in the semiconductor substrate is increased as the integration degree is increased. It is difficult to form a film with sufficient coverage in such a high aspect ratio contact hole by the sputtering method, which is the current typical metal film forming method, and some new methods or conventional methods have been improved. The methods have been studied and are being applied. The representative ones are listed below.

【0003】 CVD法によるブランケットのタング
ステンもしくはアルミニウム膜の形成 選択CVD法によるプラグ電極配線の形成(タング
ステンもしくはアルミニウム) バイアスもしくは高温スパッタ法による凹部の埋め
込み(アルミニウム合金) 膜形成後の高温処理による凹部の埋め込み(アルミ
ニウム合金)
Formation of Blanket Tungsten or Aluminum Film by CVD Method Formation of Plug Electrode Wiring by Selective CVD Method (Tungsten or Aluminum) Filling of Cavity by Bias or High Temperature Sputtering Method (Aluminum Alloy) Cavity of Cavity by High Temperature Treatment After Film Formation Embedded (aluminum alloy)

【0004】[0004]

【発明が解決しようとする課題】しかしこれらの新技
術,改良技術も万能ではなく課題は多い。それぞれの技
術に対し、(1)接着層が必要,高抵抗(タングステ
ン),表面起伏大、(2)選択デポの条件範囲狭くプロセ
スマージン小、下地材料が限られる、(3)バイアス制御
難(膜質劣化しやすい),埋込特性低い、(4)埋込特性
低い、等の問題点があげられる。また、前記は埋込
特性(どれだけアスペクト比の高い孔を埋め込めるか)
が相対的に良いがプロセスの制御性が悪い。はプロ
セス自身は比較的簡単だが埋込特性が低く、一長一短で
ある。
However, these new and improved technologies are not universal and have many problems. For each technology, (1) adhesive layer required, high resistance (tungsten), large surface undulation, (2) narrow range of conditions for selective deposition, small process margin, limited base material, (3) difficult bias control ( There are problems such as deterioration of film quality), poor embedding characteristics, and (4) poor embedding characteristics. Also, the above is the embedding characteristics (how high the aspect ratio holes can be embedded)
Is relatively good, but process controllability is poor. The process itself is relatively simple, but the embedding characteristics are low, and there are advantages and disadvantages.

【0005】本発明の目的は、上記のような問題を解決
し、プロセスが簡単で制御性が良く、かつ埋込特性が良
い電極配線の製造方法を提供することにある。
An object of the present invention is to solve the above-mentioned problems, and to provide a method for manufacturing an electrode wiring which has a simple process, good controllability, and good burying characteristics.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、本発明では、真空もしくは減圧下での金属、特に低
融点のアルミニウムもしくはアルミニウムを主成分とす
る合金膜形成工程と、それに引き続く高温加圧処理によ
り基板表面の凹部へ電極配線を形成するものである。そ
の際、特に表面酸化膜もしくは汚染物領域を除去する
と、処理の低温化,低圧化を図ることが出来る。
In order to achieve the above object, according to the present invention, a step of forming a metal, particularly aluminum having a low melting point or an alloy film containing aluminum as a main component under vacuum or reduced pressure, and a subsequent high temperature treatment. The electrode wiring is formed in the concave portion of the substrate surface by pressure treatment. At that time, particularly by removing the surface oxide film or the contaminant region, it is possible to lower the processing temperature and lower the pressure.

【0007】[0007]

【作用】金属、特に低融点のアルミニウムもしくはアル
ミニウムを主成分とする合金膜は十分高温に保てば融点
より低くても(特に真空中では)ある程度の流動性を示
し、基板表面の凹部に入る等、表面が滑らかになる方向
に変化する。温度の目安は絶対温度で表した融点の1/
2以上である。この温度以上ではほとんどの金属につい
て拡散による物質移動が顕著になることが知られてい
る。その際、基板外部から膜に圧力を加えれば、膜の一
部を基板表面の凹部に押し込む効果は著しく向上し、さ
らにその際必要となる温度も低温化できる。また、金属
の移動の妨げとなる表面酸化膜,汚染物質層を除去すれ
ば、さらにその効果が高まる。
[Function] A metal, particularly aluminum having a low melting point or an alloy film containing aluminum as a main component, exhibits a certain degree of fluidity even if the temperature is lower than the melting point (especially in a vacuum) and enters a concave portion of the substrate surface if kept at a sufficiently high temperature. And so on, the surface changes to become smooth. A guideline for temperature is 1 / of the melting point expressed in absolute temperature.
It is 2 or more. It is known that above this temperature, most metals undergo remarkable mass transfer due to diffusion. At this time, if a pressure is applied to the film from the outside of the substrate, the effect of pushing a part of the film into the concave portion of the substrate surface is significantly improved, and the temperature required at that time can be lowered. Further, the effect is further enhanced by removing the surface oxide film and the contaminant layer which hinder the movement of the metal.

【0008】[0008]

【実施例】〈実施例1〉図1〜図3は本発明の実施例を
示すシリコン半導体装置配線系の図である。図1から図
3の順に工程を経て配線系を製造した。
EXAMPLE 1 FIG. 1 to FIG. 3 are views of a wiring system of a silicon semiconductor device showing an example of the present invention. A wiring system was manufactured through steps in the order of FIG. 1 to FIG.

【0009】この配線系は次のような通常のシリコン半
導体素子製造工程および本発明の処理とで作成した。即
ち、シリコン基板11表面に能動部分を作成した後、絶
縁膜層を介しながら多結晶シリコンの電極配線21,タ
ングステン配線22を形成し、本発明の配線を形成する
ための下地絶縁膜32を形成し、下層との接続孔41を
開口した。引き続き、アルミニウム−1%Si合金膜を
スパッタ法で形成した。スパッタ法では段差被覆率が低
いため、図1に示すように接続孔内部は埋まらずに空洞
が残った。続いて、この基板に加圧処理を施した。まず
基板を入れたチャンバを不活性の高純度アルゴンガスで
満たし、所定の圧力を加えた。この状態で基板を加熱し
所定の温度で一定時間(いまの場合10分)保持した
後、室温まで冷却し、アルゴンガスを減圧排気した後、
基板を取り出した(図2)。
This wiring system was prepared by the following ordinary silicon semiconductor device manufacturing process and the process of the present invention. That is, after forming an active portion on the surface of the silicon substrate 11, the polycrystalline silicon electrode wiring 21 and the tungsten wiring 22 are formed with the insulating film layer interposed therebetween, and the base insulating film 32 for forming the wiring of the present invention is formed. Then, the connection hole 41 with the lower layer was opened. Subsequently, an aluminum-1% Si alloy film was formed by the sputtering method. Since the step coverage is low in the sputtering method, as shown in FIG. 1, the inside of the connection hole was not filled and a cavity remained. Subsequently, the substrate was subjected to pressure treatment. First, the chamber containing the substrate was filled with an inert high-purity argon gas, and a predetermined pressure was applied. After heating the substrate in this state and maintaining it at a predetermined temperature for a certain time (10 minutes in this case), it is cooled to room temperature, and the argon gas is exhausted under reduced pressure.
The substrate was taken out (Fig. 2).

【0010】その後フォトエッチング法で図3に示すよ
うな目的の配線パターンに加工した。
After that, a target wiring pattern as shown in FIG. 3 was processed by photoetching.

【0011】上記の加圧高温処理で温度と圧力が適正な
範囲にあると、図2に示すように接続孔が埋め込まれ、
高い信頼性が実現できる。温度と圧力の範囲は次の表1
及び表2に示す。
When the temperature and the pressure are within the proper ranges in the above pressurizing and high temperature treatment, the connection holes are filled as shown in FIG.
High reliability can be realized. Table 1 below shows the temperature and pressure ranges.
And shown in Table 2.

【0012】[0012]

【表1】 [Table 1]

【0013】[0013]

【表2】 [Table 2]

【0014】上記の二つの表からわかるように、十分な
信頼度を保つには、温度300℃,圧力100気圧程度
が必要だが、特に温度を400℃以上に上げれば30気
圧程度でも埋め込みができた。
As can be seen from the above two tables, a temperature of 300 ° C. and a pressure of about 100 atm are required to maintain sufficient reliability, but if the temperature is raised to 400 ° C. or higher, the embedding can be performed at about 30 atm. It was

【0015】本実験はアルミニウム−1%Si合金膜を
用いて行なったが、純アルミニウム,アルミニウム−C
u(−Si)合金等でもほぼ同様な条件で埋め込みがで
きる。また、アルミニウム−Ge等、非常に低い共晶温
度(424℃)を有する合金では上記の条件よりさらに
低温で埋め込みができる。また同一の材料でも、十分装
置を排気し高真空状態に達した後に形成した低比抵抗の
膜ほど埋込特性,歩留が良くなる傾向があった。このよ
うに材料および膜形成条件による多少の変動はあるが、
アルミニウムを主成分とする合金ではこの処理法により
十分な信頼度のある埋め込みができる。
This experiment was conducted using an aluminum-1% Si alloy film, but pure aluminum and aluminum-C were used.
A u (-Si) alloy or the like can be embedded under almost the same conditions. Further, alloys having a very low eutectic temperature (424 ° C.) such as aluminum-Ge can be embedded at a temperature lower than the above conditions. Further, even with the same material, the lower the specific resistance film formed after the device was sufficiently evacuated to reach the high vacuum state, the better the embedding characteristics and yield tended to be. Although there are some variations depending on the material and film forming conditions,
With an alloy containing aluminum as a main component, this treatment method enables filling with sufficient reliability.

【0016】また下地基板への影響等の問題がなければ
アルミニウム合金より融点の材料についても同様に適用
することができる。たとえば銅では400〜500℃以
上で同様の効果を得ることができた。
Further, a material having a melting point higher than that of an aluminum alloy can be similarly applied as long as there is no problem such as influence on the base substrate. For example, with copper, a similar effect could be obtained at 400 to 500 ° C. or higher.

【0017】〈実施例2〉図1および図4〜図6は本発
明の実施例を示すシリコン半導体装置配線系の図であ
る。図1(実施例1と同じ)→図4→図5→図6の順に
工程を経て配線系を製造した。
<Embodiment 2> FIGS. 1 and 4 to 6 are views of a wiring system of a silicon semiconductor device showing an embodiment of the present invention. A wiring system was manufactured through steps in the order of FIG. 1 (same as Example 1) → FIG. 4 → FIG. 5 → FIG.

【0018】この配線系は次のような通常のシリコン半
導体素子製造工程および本発明の処理とで作成した。即
ち、シリコン基板11表面に能動部分を作成した後、絶
縁膜層を介しながら多結晶シリコンの電極配線21,タ
ングステン配線22を形成し、本発明の配線を形成する
ための下地絶縁膜32を形成し、下層との接続孔41を
開口した。引き続き、アルミニウム−1%Si合金膜を
スパッタ法で形成した。スパッタ法では段差被覆率が低
いため、図1に示すように接続孔内部は埋まらずに空洞
が残った。
This wiring system was created by the following ordinary silicon semiconductor device manufacturing process and the process of the present invention. That is, after forming an active portion on the surface of the silicon substrate 11, the polycrystalline silicon electrode wiring 21 and the tungsten wiring 22 are formed with the insulating film layer interposed therebetween, and the base insulating film 32 for forming the wiring of the present invention is formed. Then, the connection hole 41 with the lower layer was opened. Subsequently, an aluminum-1% Si alloy film was formed by the sputtering method. Since the step coverage is low in the sputtering method, as shown in FIG. 1, the inside of the connection hole was not filled and a cavity remained.

【0019】続いて、通常のフォトエッチング法で図4
に示すような目的の配線パターンに加工した。この処理
をするために基板を真空ないしは減圧容器から取りだし
て大気にさらすことまた各種の化学薬品にさらすことの
結果としてアルミニウム合金膜パターンの表面に酸化膜
が形成され、場合によっては酸化膜以外の汚染物質が付
着した状態になっている。図4はこの状況を示してお
り、酸化膜もしくは汚染物質層51が表面を覆ってい
る。アルミニウム合金の場合、酸化膜の厚さは数nm〜
10nmである。この状況で実施例1と同じ処理をして
も十分な埋め込み効果が得られないため次に述べる酸化
膜除去処理を施す。
Then, by a normal photoetching method, as shown in FIG.
The wiring pattern was processed into the intended wiring pattern as shown in. In order to perform this treatment, an oxide film is formed on the surface of the aluminum alloy film pattern as a result of removing the substrate from a vacuum or decompression container and exposing it to the atmosphere and various chemicals. Contaminants are attached. FIG. 4 shows this situation, where the oxide film or contaminant layer 51 covers the surface. In the case of aluminum alloy, the thickness of the oxide film is several nm ~
It is 10 nm. In this situation, a sufficient filling effect cannot be obtained even if the same process as in Example 1 is performed, so the oxide film removing process described below is performed.

【0020】基板を真空チャンバ内の電極に装着し、ア
ルゴンガスを導入した後、高周波の電圧を印加し、いわ
ゆるスパッタクリーニングを施した。通常パターン表面
に比べてパターン側面の酸化膜,汚染物層は除去しにく
い。表面で約100nmの層を除去するまでスパッタク
リーニング処理をすると側面で10nmの層を除去する
ことが出来、ほぼきれいな表面が露出した(図5)。
The substrate was mounted on an electrode in a vacuum chamber, an argon gas was introduced, a high frequency voltage was applied, and so-called sputter cleaning was performed. It is more difficult to remove the oxide film and the contaminant layer on the side of the pattern than on the surface of the pattern. When the sputter cleaning treatment was performed until the layer of about 100 nm was removed on the surface, the layer of 10 nm could be removed on the side surface, and a nearly clean surface was exposed (FIG. 5).

【0021】この基板を大気にさらすことなく引き続き
加熱処理を施した。まず基板を入れたチャンバを不活性
の高純度アルゴンガスで満たし、所定の圧力を加えた。
この状態で基板を加熱し所定の温度で一定時間(いまの
場合10分)保持した後、室温まで冷却し、アルゴンガ
スを減圧排気した後、基板を取り出した(図6)。
This substrate was subsequently subjected to heat treatment without being exposed to the atmosphere. First, the chamber containing the substrate was filled with an inert high-purity argon gas, and a predetermined pressure was applied.
In this state, the substrate was heated and kept at a predetermined temperature for a certain period of time (10 minutes in this case), then cooled to room temperature, the argon gas was exhausted under reduced pressure, and then the substrate was taken out (FIG. 6).

【0022】上記の加圧高温処理で温度と圧力が適正な
範囲にあると、図6に示すように接続孔が埋め込まれ、
高い信頼性が実現できる。温度と圧力の範囲は次の表3
及び表4に示す。
When the temperature and the pressure are within the proper range in the above-mentioned pressurizing and high temperature treatment, the connection hole is filled as shown in FIG.
High reliability can be realized. The range of temperature and pressure is shown in Table 3 below.
And shown in Table 4.

【0023】[0023]

【表3】 [Table 3]

【0024】[0024]

【表4】 [Table 4]

【0025】上記の二つの表からわかるように、十分な
信頼度を保つには、温度300℃,圧力30気圧程度が
必要だが、特に温度を400℃以上に上げれば真空中で
も埋め込みができた。
As can be seen from the above two tables, a temperature of about 300 ° C. and a pressure of about 30 atm are required to maintain sufficient reliability, but if the temperature is raised to 400 ° C. or higher, the filling can be performed even in vacuum.

【0026】本実験はアルミニウム−1%Si合金膜を
用いて行なったが、純アルミニウム,アルミニウム−C
u(−Si)合金等でもほぼ同様な条件で埋め込みがで
きる。また、アルミニウム−Ge等、非常に低い共晶温
度(424℃)を有する合金では上記の条件よりさらに
低温で埋め込みができる。また同一の材料でも、十分装
置を排気し高真空状態に達した後に形成した低比抵抗の
膜ほど埋込特性,歩留が良くなる傾向があった。このよ
うに材料および膜形成条件による多少の変動はあるが、
アルミニウムを主成分とする合金ではこの処理法により
十分な信頼度のある埋め込みができる。
This experiment was conducted using an aluminum-1% Si alloy film, but pure aluminum and aluminum-C were used.
A u (-Si) alloy or the like can be embedded under almost the same conditions. Further, alloys having a very low eutectic temperature (424 ° C.) such as aluminum-Ge can be embedded at a temperature lower than the above conditions. Further, even with the same material, the lower the specific resistance film formed after the device was sufficiently evacuated to reach the high vacuum state, the better the embedding characteristics and yield tended to be. Although there are some variations depending on the material and film forming conditions,
With an alloy containing aluminum as a main component, this treatment method enables filling with sufficient reliability.

【0027】また下地基板への影響等の問題がなければ
アルミニウム合金より融点の材料についても同様に適用
することができる。たとえば銅では400〜500℃以
上で同様の効果を得ることができた。
Further, a material having a melting point higher than that of an aluminum alloy can be similarly applied if there is no problem such as an influence on the base substrate. For example, with copper, a similar effect could be obtained at 400 to 500 ° C. or higher.

【0028】[0028]

【発明の効果】以上説明したように、本発明によれば、
高アスペクト比の接続孔をアルミニウム合金による簡単
な処理で埋め込むことができ、接続孔配線の信頼性向上
を実現することができるので、集積密度の高い各種半導
体装置の実現に極めて有用である。
As described above, according to the present invention,
Since it is possible to fill the connection holes with a high aspect ratio by a simple treatment with an aluminum alloy and improve the reliability of the connection hole wiring, it is extremely useful for realizing various semiconductor devices with high integration density.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の配線部断面図。FIG. 1 is a sectional view of a wiring portion according to an embodiment of the present invention.

【図2】本発明の一実施例の配線部断面図。FIG. 2 is a sectional view of a wiring portion according to an embodiment of the present invention.

【図3】本発明の一実施例の配線部断面図。FIG. 3 is a sectional view of a wiring portion according to an embodiment of the present invention.

【図4】本発明の一実施例の配線部断面図。FIG. 4 is a sectional view of a wiring portion according to an embodiment of the present invention.

【図5】本発明の一実施例の配線部断面図。FIG. 5 is a sectional view of a wiring portion according to an embodiment of the present invention.

【図6】本発明の一実施例の配線部断面図。FIG. 6 is a sectional view of a wiring portion according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11…シリコン基板、21…多結晶シリコン電極配線、
22…タングステン配線、23…アルミニウム−1%S
i合金配線、31,32…層間絶縁膜、41…接続孔
部、51…酸化膜もしくは汚染物質層。
11 ... Silicon substrate, 21 ... Polycrystalline silicon electrode wiring,
22 ... Tungsten wiring, 23 ... Aluminum-1% S
i alloy wiring, 31, 32 ... Interlayer insulating film, 41 ... Connection hole part, 51 ... Oxide film or contaminant layer.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】基板上に、膜状もしくは所定の形状に加工
したパターン状の金属の領域を形成した状態で、一気圧
以上の圧力を印加しながら上記金属の絶対温度で表した
融点の1/2以上の温度に保持することを特徴とする電
極配線の製造方法。
1. A film-shaped or patterned metal region processed into a predetermined shape is formed on a substrate, and a melting point of the metal represented by an absolute temperature of 1 is applied while applying a pressure of 1 atm or more. A method for manufacturing an electrode wiring, which is characterized by holding at a temperature of / 2 or more.
【請求項2】基板上に、膜状もしくは所定の形状に加工
したパターン状の金属の領域を形成し、この領域の表面
に形成された酸化膜もしくは汚染物質を除去し、非酸化
性もしくは汚染物質の付着のない雰囲気に保ちながら
(真空も含む)上記金属の絶対温度で表した融点の1/
2以上の温度に保持することを特徴とする電極配線の製
造方法。
2. A film-shaped or patterned metal region processed into a predetermined shape is formed on a substrate, and an oxide film or contaminants formed on the surface of this region is removed to obtain non-oxidizing or contamination. 1 / of the melting point expressed by the absolute temperature of the above metal (including vacuum) while keeping the atmosphere free from substances
A method for manufacturing an electrode wiring, which is characterized by holding at a temperature of 2 or more.
【請求項3】基板上に、膜状もしくは所定の形状に加工
したパターン状の金属の領域を形成し、この領域の表面
に形成された酸化膜もしくは汚染物質を除去し、非酸化
性もしくは汚染物質の付着のない雰囲気に保ち、一気圧
以上の圧力を印加しながら、上記金属の絶対温度で表し
た融点の1/2以上の温度に保持することを特徴とする
電極配線の製造方法。
3. A film-shaped or patterned metal region processed into a predetermined shape is formed on a substrate, and an oxide film or contaminants formed on the surface of this region is removed to make it non-oxidizing or contaminating. A method for producing electrode wiring, which is characterized in that the temperature is maintained at ½ or more of the melting point expressed by the absolute temperature of the metal while applying a pressure of 1 atm or more in an atmosphere free from adhesion of substances.
【請求項4】請求項1または2または3記載の金属の領
域がアルミニウムもしくはアルミニウムを主成分とする
合金であることを特徴とする電極配線の製造方法。
4. A method of manufacturing an electrode wiring, wherein the metal region according to claim 1, 2 or 3 is aluminum or an alloy containing aluminum as a main component.
【請求項5】上記の請求項4に記載のアルミニウムもし
くはアルミニウムを主成分とする領域が基板表面の少な
くとも一つ以上の開口部もしくは溝状の凹部を完全に覆
い、内部にアルミニウムの空洞部が残されていることを
特徴とする電極配線の製造方法。
5. The aluminum or the region containing aluminum as a main component according to claim 4 completely covers at least one opening or groove-shaped recess on the surface of the substrate, and an aluminum cavity is provided inside. A method for manufacturing an electrode wiring, which is characterized by being left.
【請求項6】上記の請求項1〜5の、一気圧以上の圧力
を印加する媒体が水素,アルゴン,窒素等の不活性ガ
ス、もしくはオイル等反応性の低い液体であることを特
徴とする請求項1〜5に記載の電極配線の製造方法。
6. The medium according to any one of claims 1 to 5 to which a pressure of 1 atm or more is applied is an inert gas such as hydrogen, argon or nitrogen, or a liquid having low reactivity such as oil. The method for manufacturing the electrode wiring according to claim 1.
【請求項7】基板上に形成された膜状もしくはパターン
状の金属の領域の表面に存在する酸化膜もしくは汚染物
領域を除去する機能を有する部分,基板を加熱し加圧す
る機能を有する部分、および両部分の間を、真空もしく
は非酸化性の雰囲気で基板を搬送する機能をもった基板
処理装置。
7. A portion having a function of removing an oxide film or a contaminant region existing on the surface of a film-shaped or patterned metal region formed on a substrate, a portion having a function of heating and pressing the substrate, And a substrate processing apparatus having a function of transporting the substrate between the two portions in a vacuum or a non-oxidizing atmosphere.
JP22972392A 1992-08-28 1992-08-28 Manufacture and processor of electrode wiring Pending JPH0677334A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22972392A JPH0677334A (en) 1992-08-28 1992-08-28 Manufacture and processor of electrode wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22972392A JPH0677334A (en) 1992-08-28 1992-08-28 Manufacture and processor of electrode wiring

Publications (1)

Publication Number Publication Date
JPH0677334A true JPH0677334A (en) 1994-03-18

Family

ID=16896694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22972392A Pending JPH0677334A (en) 1992-08-28 1992-08-28 Manufacture and processor of electrode wiring

Country Status (1)

Country Link
JP (1) JPH0677334A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329284B2 (en) 1995-10-17 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Manufacturing process of a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6329284B2 (en) 1995-10-17 2001-12-11 Mitsubishi Denki Kabushiki Kaisha Manufacturing process of a semiconductor device

Similar Documents

Publication Publication Date Title
US5679983A (en) Highly purified metal material and sputtering target using the same
JP2828540B2 (en) Method for forming low resistance and low defect density tungsten contacts for silicon semiconductor wafers
EP0596364B1 (en) Method of producing semiconductor device having buried contact structure
KR100303873B1 (en) A method of forming a low resistance aluminum plug in a via that is electrically connected to a bottom patterned metal layer of an integrated circuit structure.
JP3631392B2 (en) Method for forming wiring film
JP2000195954A (en) Semiconductor device and manufacturing method thereof
JPH02230739A (en) Method of applying fire-resistant metal
JPH1187349A (en) Semiconductor device manufacturing method and semiconductor device
JP2718842B2 (en) Method for manufacturing wiring metal film for semiconductor integrated circuit
JP3272325B2 (en) Method of forming metal-filled structure
JP3449333B2 (en) Method for manufacturing semiconductor device
JP2950218B2 (en) Method for manufacturing semiconductor device
JPH0677334A (en) Manufacture and processor of electrode wiring
US5106779A (en) Method for widening the laser planarization process window for metalized films on semiconductor wafers
JPH0766125A (en) Decompression processing device
JP3282496B2 (en) Method for manufacturing semiconductor device
JP2694950B2 (en) Method of forming high melting point metal film
JP3263611B2 (en) Copper thin film manufacturing method, copper wiring manufacturing method
JPH0613380A (en) Al-based material forming method, Al-based wiring structure, semiconductor device manufacturing method, and semiconductor device
JPH1079428A (en) Manufacturing method and processing apparatus for electrode wiring
JP3082161B2 (en) Wiring layer formation method
JPH01270333A (en) Manufacture of semiconductor device
JP2003309124A (en) Semiconductor device
JPH04291763A (en) Semiconductor device and manufacture thereof
JPH1187495A (en) Wiring formation method