JPH0677790A - Bit string compensation circuit - Google Patents

Abstract

PURPOSE:To compensate a bit string of sent multiplexed data even when the multiplexed data are sent through time division multiplexing. CONSTITUTION:A polyphase clock latch circuit 12 latches received data based on plural clocks whose phases differ from each other to output plural latch data L1-L4, and a reception data change point detection circuit 14 and a latch data selection circuit 16 of a succeeding stage obtain a selection output S6 of latch data based on a timing when a logic level of each latch data is changed. A re-sampling circuit 32 resamples the signal S6 with a reference clock CLK1 or CLK3 to output data DO in which the bit string is compensated as specified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit string compensating circuit, and more particularly to a multiplexed data obtained by time-division-multiplexing transmission data transmitted from a plurality of terminals in a bit unit of a predetermined cycle on the basis of a predetermined clock. It is suitable to be applied when given.

[0002]

2. Description of the Related Art Conventionally, when a digital signal sent from a subscriber's house is transmitted to a station, time division multiplexing (TDMA:
Time Division Multiple Ac
(Cess) method is used to transmit a digital signal so that the digital signal can be efficiently transmitted.

That is, when a digital signal is transmitted by applying the time division multiplexing technique, the number of lines can be reduced and the digital signal can be transmitted efficiently by that amount.

[0004]

By the way, in the optical fiber transmission, there is a feature that the transmission speed can be improved as compared with the case where a digital signal is transmitted using a transmission line such as a coaxial cable.

Further, in the optical fiber transmission, there is a feature that the light used for transmission can be easily combined through an optical coupler.

Therefore, when a digital signal is transmitted using an optical fiber, a time division multiplexing method can be easily applied. Further, by applying the time division multiplexing method, the digital signal can be transmitted more efficiently. It is considered possible to transmit.

That is, in FIG. 2, 1 is P as a whole.
An optical subscriber network of an SD (Passive Double Star) type is shown. In this optical subscriber network 1,
The digital signals sent from the subscriber home terminals 2A, 2B, 2C are sent to the network unit 4 and sent from this network unit 4 to a desired transmission target.

At this time, each subscriber home terminal 2A, 2B, 2C
The digital signal is transmitted between the network unit 4 and the network unit 4 through the optical fiber, and the optical fiber is connected by the coupler 6.

As shown in FIG. 3, each subscriber home terminal 2A, 2
B and 2C are optical data S2A, S2B, and S2 at predetermined timings assigned to the terminals 2A, 2B, and 2C, respectively.
C is transmitted (FIGS. 3A, 3B, and 3C), and the coupler 6 optically combines the optical data S2A, S2B, and S2C and outputs transmission data ST (FIG. 3D).

As a result, in this type of optical subscriber network 1, the digital signals of the terminals 2A, 2B and 2C can be easily time-division multiplexed and transmitted simply by connecting the optical fibers with the coupler 6.

However, if the distances between the terminals 2A, 2B, 2C and the coupler 6 are different, the optical data S2A, S2B, S2C sent from the terminals 2A, 2B, 2C have different time delays for the coupler 6. Reach by.

Therefore, when the subscriber network 1 is operated in synchronization with a single clock, the network unit 4
In the time-division multiplexed signal ST which arrives at, the intra-bit delay, the irregularity of the transmission path band, the jitter due to the phase fluctuation, etc. occur depending on the difference in the distance, and the arrangement of the bit strings becomes irregular intervals. In the network unit 4, if the irregular intervals due to the intra-bit delay, the jitter, etc. become large, the optical data S2A, S2B, S2C cannot be correctly processed, and the optical multiplexed signal ST is converted into the multiplexed data of the electric signal. However, if the data is output as a transmission, the problem arises that the transmission device at the destination cannot correctly process it.

In order to solve the above problems, for example, a PLL (phase locked loop) circuit is used to convert the optical multiplexed data into electrical multiplexed data, and the electrical multiplexed data is then transferred to a PLL circuit. A method of extracting a clock of a constant cycle and compensating the data with this clock to a constant cycle is also conceivable. However, in this method, the operating frequency range of the PLL circuit, the capture range, the jitter resistance characteristic, etc. In order to set to a practical range, the time constant of the loop filter must be set to a very large value, which makes the component shape for setting a large time constant large and allows the circuit to be miniaturized. There is also a problem that it is difficult to integrate.

Further, there is also a problem that the structure for stabilizing the VCO inside the PLL circuit at high speed is not easy, and the analog element is also required, so that the integration is not easy.

The present invention has been made in consideration of the above points, and an object thereof is to compensate a bit string of transmitted multiplexed data even when transmitting multiplexed data by time division multiplexing. It is to provide a bit string compensation circuit capable of

[0016]

In order to solve the above problems, the present invention is obtained by time-division-multiplexing transmission data transmitted from a plurality of terminals in a bit unit of a predetermined cycle on the basis of a predetermined clock. Given multiplexed data,
Detecting the multiplexed data with a plurality of clocks each having a different predetermined phase, and detecting means for outputting each detection signal,
Selection means for detecting a level change of each of the detection signals, selecting and outputting the detection signal having a phase closest to the phase of the transmitted data from the detection signals, and a plurality of clocks each different by a predetermined phase Sampling means for compensating for bit deviation by sampling the output bit string of the selecting means at any one of the clocks, and the bit string from the output of the sampling means in synchronization with any of the clocks. It is characterized by obtaining compensated multiplexed data.

[0017]

According to the present invention, by the detecting means and the selecting means, even if the bit width or the cycle is not constant, the compensation is performed in synchronization with the reference clock. Moreover, since the output bit string of the selecting means is sampled at any one of a plurality of clocks that differ by a predetermined phase, even if the influence of jitter remains on the output of the selecting means and the bits are shifted, It is possible to perform compensation (removal of jitter) and synchronize with any one of the reference clocks to compensate for the shift of the bit string.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the bit string compensating circuit of the present invention will be described with reference to the drawings. In this embodiment, the network unit (Office Subscriber U) is used in the optical fiber transmission system shown in FIG.
(nit) The following shows how the bit string is compensated for the multiplexed data of four outputs.

FIG. 1 is a functional block of the bit string compensating circuit of this embodiment.

In FIG. 1, the bit string compensating circuit comprises a multi-phase clock latch circuit 12, a received data change point detecting circuit 14, a latch data selecting circuit 16, a resampling circuit 32, and a judging circuit 50. There is.

In this embodiment, the network unit 4 operates on the basis of a single reference clock common to the entire optical fiber transmission system.

That is, the duty ratio of each terminal 2A, 2B, 2C synchronized with this reference clock is, for example, 50%.
Of the optical data, and at this time, the optical data is transmitted in time division for each period allocated to each terminal in a predetermined bit unit.

The network unit 4 includes terminals 2A,
Optical data sent from 2B and 2C are combined by a coupler 6 and time-division multiplexed, and then converted into input data DI by a predetermined photoelectric conversion circuit. Then, the network unit 4 gives the input data DI to the multi-phase clock latch circuit 12 of the bit string compensating circuit.

FIG. 4 is a logic circuit diagram of an example of the multi-phase clock latch circuit 12.

In FIG. 4, the multi-phase clock latch circuit 12 is composed of D type flip-flops 18A to 18D, and the received data DI is supplied to the data input D of the D type flip-flops 18A to 18D. (Fig. 5
(A) shows the timing).

The clock input C of the D-type flip-flop 18A is supplied with the 0-phase clock CLK1 (the timing is shown in FIG. 5B). A clock CLK2 with a 90 ° phase delay is supplied to the clock input C of the D flip-flop 18B (FIG. 5).
(C) shows the timing). Further, the clock CLK3 having a phase delay of 180 ° is supplied to the clock input C of the D-type flip-flop 18C (the timing is shown in FIG. 5D). Moreover, the clock input C of the D-type flip-flop 18D has a clock CLK with a phase delay of 270 °.
4 is supplied (the timing is shown in FIG. 5 (E)).

The multi-phase clock latch circuit 12
Inputs the input data DI into the four-phase clock CLK1
To CLK4, the latch data L1 to L4 are supplied to the reception data change point detection circuit 14 and the latch data selection circuit 16.

Here, the four-phase clocks CLK1 to CL
Of K4, the first clock CLK1 is a reference clock signal of the network unit 4 and is an operation reference clock signal used in a receiving circuit (not shown) to which the output of the bit string compensating circuit is connected.

On the other hand, each of the remaining phase clocks CLK
2 to CLK4 are different in phase from the first clock CLK1 by 90 °, 180 ° and 270 °, respectively.

As a result, the multi-phase clock latch circuit 12
Latches the input data DI with the first clock CLK1 which is a reference clock, and at the same time, the first clock C
Second to fourth held in a predetermined phase relationship with LK1
The input data DI is latched by the clocks CLK2 to CLK4, and the latch result outputs L1 to L4 are supplied to the subsequent reception data change point detection circuit 14 and the latch data selection circuit 16.

FIG. 6 is a logic circuit diagram of the reception data change point detection circuit 14 of this embodiment.

In FIG. 6, the reception data change point detection circuit 14 includes D-type flip-flops 20A to 20D.
And exclusive-OR gates 22A to 22D and a NOR (negative logical sum) gate 24.

Then, the D-type flip-flop 20A is
The latch data L1 is supplied to the data input D, the clock CLK2 is supplied to the clock input C, and the latch data L1D is supplied from the data output Q to the exclusive OR gate 22A. Further, in the D-type flip-flop 20B, the latch data L2 is given to the data input D, and the clock input C
Is supplied with the clock CLK3, and the latch data L2D is supplied from the data output Q to the exclusive OR gate 22B.

In the D-type flip-flop 20C, the data input D is supplied with the latch data L3, the clock input C is supplied with the clock CLK4, and the data output Q supplies the latch data L3D to the exclusive OR gate 22C. . Further, in the D-type flip-flop 20D, the latch data L4 is supplied to the data input D, the clock CLK1 is supplied to the clock input C, and the latch data L4D is supplied from the data output Q to the exclusive OR gate 22D.

Then, the received data change point detection circuit 14
Detects a clock held in a correct phase relationship with respect to the input data DI by detecting the timing when the logic level changes for each latch data L1 to L4, and based on the detection result, the signals S1 to S5 are detected. Is output selectively.

That is, as shown in FIG. 6, in the received data change point detection circuit 14, each latch data L1 to L4 is given to the latch circuits 20A to 20D, and the latch circuits 20A to 20D.
0D is a clock signal CL of each latch data L1 to L4
Latch data L1 to L4 are latched by clocks CLK2, CLK3, CLK4, and CLK1 whose phases are delayed by 90 ° with respect to K1 to CLK4.

As a result, the reception data change point detection circuit 14
, The phases of the latch data L1 to L4 are delayed by 90 ° (FIGS. 5F to 5M), and the latch data L1 to L4 are delayed.
4 and a clock C that is delayed by 90 ° from each other.
Timings are matched with the latch data L2, L3, L4, and L1 latched by LK2, CLK3, CLK4, and CLK1, and exclusive OR gates 22A to 22D that follow perform exclusive OR. As a result, in the reception data change point detection circuit 14, the first and second clocks CL
When the logic level of the input data DI is changing during the rising period of K1 and CLK2, the logic level of the output signal S1 output from the exclusive OR gate 22A is raised (FIG. 5 (N)).

Further, in the reception data change point detection circuit 14, the second and third clock signals CLK2 and CL
When the logic level of the input data DI is changing during the rising period of K3, the logic level of the output signal S2 output from the exclusive OR gate 22B is raised (FIG. 5 (O)), And the fourth clock CLK3 and CL
When the logic level of the input data D1 is changing between the rising edges of K4, the logic level of the output signal S3 output from the exclusive OR gate 22C is raised (FIG. 5).
(P)).

Further, in the reception data change point detection circuit 14, the fourth and first clocks CLK4 and CLK1
When the logic level of the input data DI is changing during the rising period of, the logic level of the output signal S4 output from the exclusive OR gate 22D rises (see FIG. 5).
(R)).

When no change in the logic level of the received data DI is detected between any two clock phases of the clocks CLK1 to CLK4, all of the logic levels S1 to S4 are low level. Outputs the output signals S1 to S4 to the NOR gate 24, performs a NOR operation, and raises the logic level of the output signal S5 (FIG. 5 (R)). Therefore, if a change in the logic level of the received data DI is detected during any two clock phases of the clocks CLK1 to CLK4, the signal S5 becomes low level.

The above-mentioned S1 to S5 thus obtained are
It is applied to the latch data selection circuit 16.

FIG. 7 is a logic circuit diagram of the latch data selection circuit 16 and the resampling circuit 32.

In FIG. 7, the latch data selection circuit 16 is composed of AND gates 28, 26A to 26D, and an OR gate 30.

Then, the latch data selection circuit 16 receives the signals S1 to S1 supplied from the reception data change point detection circuit 14.
Latch data L1 to L4 are selected and output based on S5. That is, the first and second clocks CLK1 and CLK
When the logic level of the received data DI changes during the rising period of 2, if the input data DI is latched at the rising timing of the third clock CLK3, when the logical level of the received data becomes stable, it can be ensured. The received data D1 can be latched and output.

As a result, as shown in FIG. 8, the latch data selection circuit 16 outputs the signal when the logic level of the input data DI changes during the rising period of the first and second clocks CLK1 and CLK2. The latch data L3 is selectively output by S1. On the other hand, when the logic level of the input data DI changes during the rising period of the second and third clocks CLK2 and CLK3, the input data DI may be latched at the rising timing of the fourth clock CLK4. For example, the input data DI can be reliably latched and output when the logical level of the received data is stable.

As a result, the latch data selection circuit 16
Selectively outputs the latch data L4 by the signal S2 when the logic level of the input data DI is changing between the rising periods of the second and third clocks CLK2 and CLK3.

Similarly, during rising periods of the third and fourth clocks CLK3 and CLK4, and between the fourth and first clocks.
When the logic level of the input data DI is changing during the rising period of the clocks CLK4 and CLK1 of
If the input data DI is latched at the timings of the first clock CLK1 and the second clock signal CLK2, respectively, the input data DI can be surely latched when the logic level of the received data is stable, and thus the latch is performed. The data selection circuit 16 selectively outputs the latch data L1 and L2 according to the signals S3 and S4.

On the other hand, when the logic level of the input data DI has not changed, the latch data selection circuit 16
Selectively outputs the latch data L1 by the signal S5.

That is, as shown in FIG. 7, the latch data selection circuit 16 gives the output signals S1 to S4 of the reception data change point detection circuit 14 to the AND gates 26A to 26D, where the latch data L1 to L4 are respectively supplied. Detect the logical product of.

Further, the latch data selection circuit 16 gives the output signal S5 of the reception data change point detection circuit 14 to the AND gate 28, where it performs a logical product with the latch data L1 and outputs it.

Further, the latch data selection circuit 16 gives the output signals of the AND gates 26A to 26D and the AND gate 28 to the OR gate 30, and supplies the output signal S6 to the subsequent resampling circuit 32 (FIG. 5 (S ) Timing).

As a result, the latch data selection circuit 16 is
The latch data L1 to L4 are selected based on the detection result of the reception data change point detection circuit 14, and the selection result is output as the output signal S.
Then, it is sent to the resampling circuit 32 as 6.

In FIG. 7, the resampling circuit 32 is shown.
Is composed of D-type flip-flops 38 and 48, AND gates 40 and 46, an inverter 42, and an OR gate 44.

The resampling circuit 32 is
The signal S6 supplied from the latch data selection circuit 16 is resampled with the reference clock CLK1 or CLK3 and output.

As a result, in the bit string compensating circuit of this embodiment, the input data DI is latched by the clocks having different phases to generate a plurality of latch data L1 to L4, and then the selected output of the latch data L1 to L4 is performed. By re-sampling with the reference clock and outputting
Even if the optical data of each terminal is delayed by a different delay time by the length of the optical fiber or is affected by the jitter, it can be output in synchronization with the reference clock CLK1. It can be processed reliably.

At this time, the re-sampling circuit 32 re-samples the signal S6 with the clock signal CLK3 whose phase is 180 ° different from that of the reference clock CLK1 (FIG. 5).
(Timing (T)), based on the judgment detection result SL (timing in FIG. 5 (U)) of the influence of the jitter of the input data DI, this signal SK and the output signal resampled by the reference clock CLK1 are selectively output, This eliminates the influence of bit shift due to jitter (timing in FIG. 5 (V)).

That is, the resampling circuit 32 supplies the signal S6 supplied from the latch data selection circuit 16 to the D-type flip-flop 38 which latches with the clock CLK3, and thereby resamples the signal S6 with the clock CLK3.

Further, the resampling circuit 32 outputs the output signal SK of the D-type flip-flop 38 to the AND gate 40.
, And outputs an AND signal with the inverted signal of the resampling selection signal SL supplied via the inverter circuit 42.

Here, the resampling selection signal SL is
The determination data (for example, the alternating pattern data of 01) sent from the terminals 2A to 22C is given as the input of the determination circuit 50 and the received data input DI, and the signal S
Depending on the states of 1 to S4, the resampling selection signal SL
The logic level of is determined.

For example, the judgment circuit 50 receives the signal for receiving the judgment data from the terminal whose signal S2 or S3 is at the high level, and then receives the resampling selection signal SL.
Is set to a low level, and the AND gate 40 outputs the signal SK sampled by the clock CLK3, and the signal SK is supplied to the D flip-flop 48.

Further, the decision circuit 50 sets the resampling selection signal SL to the high level when the signal S1 or S4 is at the high level at the time of receiving the above-mentioned decision data and receives the signal from the terminal, and the AND gate 46. Then, the signal S6 is output, and the signal S6 is controlled so as to be given to the D-type flip-flop 48.

As a result, the resampling circuit 32
Outputs the output signal of the AND gate 40 through the OR gate 44 when the logic level of the resampling selection signal SL is low level.

On the other hand, the resampling circuit 32 is
The output signal S6 of the latch data selection circuit 16 is input to the AND gate 46, and the logical product signal with the resampling selection signal SL is obtained here, so that the logical sum gate is obtained when the logical level of the resampling selection signal SL is high level. Four
The signal S6 is selectively output via the signal line 4.

Further, the resampling circuit 32 gives the output signal of the OR gate 44 to the D-type flip-flop 48 which operates by the clock signal CLK1, and thereby the received data is received by the receiving circuit and the like which follow at the timing synchronized with the clock signal CLK1. Send DO.

According to the above embodiment, the received data is latched by the clocks CLK1 to CLK4 having different phases to generate a plurality of latched data, and the selected output of the latched data is resampled by the reference clock. ,
Even when the optical data of each terminal is delayed by a different delay time by the length of the optical fiber or is affected by the jitter, the received data (multiplexed data) without the bit deviation is synchronized with the reference clock signal CLK1. The data can be output, so that the data can be provided to the receiving circuit and the like to be processed properly.

In the above one embodiment, the case where the input data is latched by four kinds of clocks having different phases has been described, but the present invention is not limited to this. For example, the compensation accuracy can be improved by increasing the types of clocks having different phases as necessary.

Further, in the above embodiment, the case where the input reception data time-division multiplexed and transmitted via the optical fiber is processed has been described, but the present invention is not limited to this. For example, it can be widely applied even when processing data transmitted through a coaxial cable or the like.

Further, in the resampling circuit 32 of FIG. 7 of the above embodiment, the clock CLK1 or CLK is used.
The re-sampling was performed according to No. 3, but the present invention is not limited to this.

[0069]

As described above, according to the present invention, input data is latched by a plurality of clock signals having different phases to generate a plurality of latch data, and the timing at which the logic level of each latch data changes is used as a reference. Then, the selected output of this latched data is obtained, and by re-sampling this selected output with the reference clock, the optical data of each terminal is delayed by a delay time different by the length of the optical fiber, or the influence of jitter is affected. Even when receiving, it is possible to obtain a bit string compensating circuit capable of compensating a bit string of transmitted data constantly.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a bit string compensating circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a conventional optical fiber transmission system.

FIG. 3 is a timing chart of transmission data transmitted from each terminal in the conventional optical fiber transmission system.

FIG. 4 is a logic circuit diagram of a multi-phase clock latch circuit according to an embodiment.

FIG. 5 is an operation timing chart of the bit string compensating circuit according to the embodiment.

FIG. 6 is a logic circuit diagram of a reception data change point detection circuit according to an embodiment.

FIG. 7 is a logic circuit diagram of a latch data selection circuit and a resampling circuit according to an embodiment.

FIG. 8 is a logic diagram of a latch data selection circuit according to an embodiment.

[Explanation of symbols]

12 ... Multi-phase clock latch circuit, 14 ... Received data change point detection circuit, 16 ... Latch data selection circuit, 32 ... Resampling circuit.

Claims (1)

[Claims] 1. Multiplexed data obtained by time-division-multiplexing transmitted data sent from a plurality of terminals in bit units of a predetermined cycle on the basis of a predetermined clock is given, and each of these multiplexed data has a predetermined phase. Detection means for detecting each of a plurality of different clocks and outputting each detection signal, and detecting the level change of each detection signal, the detection signal having the phase closest to the phase of the transmitted data among the detection signals. And a sampling means for compensating for bit deviation by sampling the output bit string of the selecting means with any one of a plurality of clocks that differ by a predetermined phase. , A bit string-compensated multiplexed data is obtained from the output of the sampling means in synchronization with any one of the clocks. Column compensation circuit.